Using LPC11Axx EEPROM (with IAP)

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Rev. 2 1 July 2012 Application note Document information Info Content Keywords LPC11A02UK ; LPC11A04UK; LPC11A11FHN33; LPC11A12FHN33; LPC11A12FBD48; LPC11A13FHI33; LPC11A14FHN33; LPC11A14FBD48; LPC11Axx, EEPROM, IAP, Abstract This application note will detail how to use IAP commands to access and modify the internal non-volatile EEPROM of the LPC11Axx device family.

Revision history Rev Date Description 2 20120701 Added EEPROM usability size. 1 20120501 Initial version. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Application note Rev. 2 1 July 2012 2 of 10

1. Introduction The LPC11Axx devices can be equipped with up to 4 kb 1 of Electrically Erasable Programmable Read-Only Memory (EEPROM). Unlike the flash memory typically used to store a program image, the EEPROM can be modified in more discrete sizes down to single byte operations. EEPROM is commonly used for storing small amounts of data that are used by an application. This can include: Calibration information A device s hardware configuration settings Operating lifetime of a device Error logging information Service history Serial numbers By integrating EEPROM memory into the LPC11Axx, two major benefits are achieved: reduced BOM on PCBs, and a radically simplified interface for software. A secondary benefit of having a reduced BOM is that designs which use the LPC11Axx can also meet more strenuous size constraints. To simplify the use of the EEPROM, the LPC11Axx devices feature functionality stored in ROM to enable users to quickly and easily integrate EEPROM into their applications. By using IAP routines, users aren t forced to learn the details of the EEPROM peripheral, and can implement their design requirements in near record time. 1. The uppermost 64 bytes are reserved and cannot be written to. All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Application note Rev. 2 1 July 2012 3 of 10

2. In-Application Programming EEPROM functions The EEPROM IAP support reading and writing for the EEPROM. As such, there are two functions that can be used which make use of the IAP calls to read and write. 2.1.1 EEPROM IAP calling convention In order to use EEPROM IAP, a function pointer must be declared which points to the IAP table entry in ROM. The declaration consists of defining the IAP entry point, defining the pointer to the function type, and setting the function pointer. The code example is shown in Fig 1. #define IAP_LOCATION 0x1FFF1FF1 typedef void (*IAP)(unsigned int command[], unsigned int result[]); static const IAP iap_entry = (IAP) IAP_LOCATION; Fig 1. Definition of IAP function pointer The IAP calls expect two arguments consisting of two integer array. The Command Array is an integer array consisting of five elements. The Return Code is an integer array consisting of a maximum of four elements. The format for the Command Array is as follows: Command[0] Command Code. Write = 61 10. Read = 62 10 Command[1] EEPROM Address Command[2] RAM Address Command[3] Number of Bytes to Process Command[4] System Clock Frequency (CCLK) in khz The Return Code is a four element integer array. For the EEPROM IAP, only the first element contains relevant information. The possible return codes are: CMD_SUCCESS 0 SRC_ADDR_NOT_MAPPED 4 DST_ADDR_NOT_MAPPED 5 The symbol iap_entry is used in the EEPROM read and write operations. 2.1.2 Usable EEPROM Size On parts with 4 kb of EEPROM, the top 64 bytes are reserved and cannot be written to or read from. Thus, the maximum usable EEPROM size is 4032 bytes, not 4096 bytes. 2.1.3 Reading EEPROM A simple IAP call has been created to facilitate reading multiple bytes of EEPROM data and storing them into a buffer. A CMSIS compliant wrapper routine can be seen in Fig 2. The EEPROM IAP routines use the CMSIS variable SystemCoreClock. For applications that are not CMSIS compliant, the last operand of the IAP call is the core operating frequency in khz units. All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Application note Rev. 2 1 July 2012 4 of 10

void readeeprom( uint8_t* eeaddress, uint8_t* buffaddress, uint32_t bytecount ) unsigned int command[5], result[4]; command[0] = 62; command[1] = (uint32_t) eeaddress; command[2] = (uint32_t) buffaddress; command[3] = bytecount; command[4] = SystemCoreClock/1000; /* Invoke IAP call...*/ iap_entry( command, result); } if (0!= result[0]) //Trap error while(1); } return; Fig 2. Routine to invoke IAP command to read EEPROM All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Application note Rev. 2 1 July 2012 5 of 10

2.1.4 Writing EEPROM A similar IAP call is used to store data from RAM or flash into EEPROM. Please note that writing to EEPROM does not require an erase cycle; data can be directly written using the IAP command. Again, a simple wrapper routine can be seen in Fig 3. void writeeeprom( uint8_t* eeaddress, uint8_t* buffaddress, uint32_t bytecount ) unsigned int command[5], result[4]; command[0] = 61; command[1] = (uint32_t) eeaddress; command[2] = (uint32_t) buffaddress; command[3] = bytecount; command[4] = SystemCoreClock/1000; /* Invoke IAP call...*/ iap_entry( command, result); } if (0!= result[0]) //Trap error while(1); } return; Fig 3. Routine to invoke IAP command to write EEPROM All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Application note Rev. 2 1 July 2012 6 of 10

3. Example application An example project is included with this application note. It demonstrates how to use the wrapper functions detailed above to perform several operations. It can fill the entire EEPROM memory with 0x00, 0xFF, an incrementing pattern of bytes, or the value of a free running timer. For illustrative purposes a portion of the example source is shown in Fig 4. switch(cmd) case CMD_FF: eefill(0xff); eedump(); break; case CMD_00: eefill(0x00); eedump(); break; case CMD_TIME: for (i=0; i<ee_size; i+=4) LPC_TMR32B0->TCR = 0; hold = LPC_TMR32B0->TC; LPC_TMR32B0->TCR = 1; writeeeprom( (uint8_t*) i, (uint8_t*) &hold, 4 ); } LPC_TMR32B0->TCR = 2; eedump(); break; } Fig 4. A portion of code to fill EEPROM with different patterns. 4. Conclusion The #define EE_SIZE needs to be changed depending on which LPC11Axx device is used. By applying the concepts outlined in this application note users of the LPC11Axx family of Cortex-M0 devices will be able to rapidly implement designs which make use of the on-chip EEPROM. The EEPROM features of LPC11Axx can open new doors in designs by enabling developers to quickly and easily store and update non-volatile memory on a byte at a time basis. All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Application note Rev. 2 1 July 2012 7 of 10

5. Legal information 5.1 Definitions Draft The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. 5.2 Disclaimers Limited warranty and liability Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer s own risk. Applications Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer s applications and products planned, as well as for the planned application and use of customer s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer s applications or products, or the application or use by customer s third party customer(s). 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In no event shall NXP Semiconductors, its affiliates or their suppliers be liable to customer for any special, indirect, consequential, punitive or incidental damages (including without limitation damages for loss of business, business interruption, loss of use, loss of data or information, and the like) arising out the use of or inability to use the product, whether or not based on tort (including negligence), strict liability, breach of contract, breach of warranty or any other theory, even if advised of the possibility of such damages. Notwithstanding any damages that customer might incur for any reason whatsoever (including without limitation, all damages referenced above and all direct or general damages), the entire liability of NXP Semiconductors, its affiliates and their suppliers and customer s exclusive remedy for all of the foregoing shall be limited to actual damages incurred by customer based on reasonable reliance up to the greater of the amount actually paid by customer for the product or five dollars (US$5.00). The foregoing limitations, exclusions and disclaimers shall apply to the maximum extent permitted by applicable law, even if any remedy fails of its essential purpose. 5.3 Trademarks Notice: All referenced brands, product names, service names and trademarks are property of their respective owners. All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Application note Rev. 2 1 July 2012 8 of 10

6. List of figures Fig 1. Definition of IAP function pointer... 4 Fig 2. Routine to invoke IAP command to read EEPROM... 5 Fig 3. Routine to invoke IAP command to write EEPROM... 6 Fig 4. A portion of code to fill EEPROM with different patterns.... 7 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Application note Rev. 2 1 July 2012 9 of 10

7. Contents 1. Introduction... 3 2. In-Application Programming EEPROM functions... 4 2.1.1 EEPROM IAP calling convention... 4 2.1.2 2.1.3 Usable EEPROM Size... 4 Reading EEPROM... 4 2.1.4 Writing EEPROM... 6 3. Example application... 7 4. Conclusion... 7 5. Legal information... 8 5.1 Definitions... 8 5.2 5.3 Disclaimers... 8 Trademarks... 8 6. List of figures... 9 7. Contents... 10 Please be aware that important notices concerning this document and the product(s) described herein, have been included in the section 'Legal information'. NXP B.V. 2012. All rights reserved. For more information, visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 1 July 2012 Document identifier: