Data Acquisition Systems. Niko Neufeld, CERN-PH

Similar documents
Trigger and Data Acquisition at the Large Hadron Collider

2008 JINST 3 S Online System. Chapter System decomposition and architecture. 8.2 Data Acquisition System

The CMS Event Builder

Detector Control LHC

Vertex Detector Electronics: ODE to ECS Interface

The FTK to Level-2 Interface Card (FLIC)

Velo readout board RB3. Common L1 board (ROB)

PoS(High-pT physics09)036

Trigger and Data Acquisition: an ATLAS case study

Level 0 trigger decision unit for the LHCb experiment

LHC Detector Upgrades

Electronics, Trigger and Data Acquisition part 3

ECE 485/585 Microprocessor System Design

RT2016 Phase-I Trigger Readout Electronics Upgrade for the ATLAS Liquid-Argon Calorimeters

LHCb Online System BEAUTY-2002

ATLAS TDAQ RoI Builder and the Level 2 Supervisor system

The LHCb upgrade. Outline: Present LHCb detector and trigger LHCb upgrade main drivers Overview of the sub-detector modifications Conclusions

1 MHz Readout. LHCb Technical Note. Artur Barczyk, Guido Haefeli, Richard Jacobsson, Beat Jost, and Niko Neufeld. Revision: 1.0

Buses. Disks PCI RDRAM RDRAM LAN. Some slides adapted from lecture by David Culler. Pentium 4 Processor. Memory Controller Hub.

The CMS Computing Model

Data Acquisition in Particle Physics Experiments. Ing. Giuseppe De Robertis INFN Sez. Di Bari

ATLAS PILE-UP AND OVERLAY SIMULATION

Evaluation of network performance for triggering using a large switch

Trigger Report. W. H. Smith U. Wisconsin. Calorimeter & Muon Trigger: Highlights Milestones Concerns Near-term Activities CMS

The GAP project: GPU applications for High Level Trigger and Medical Imaging

Improving Packet Processing Performance of a Memory- Bounded Application

Update on PRad GEMs, Readout Electronics & DAQ

RPC Trigger Overview

Alternative Ideas for the CALICE Back-End System

The ATLAS Level-1 Muon to Central Trigger Processor Interface

Storage Systems. Storage Systems

Centre de Physique des Particules de Marseille. The PCIe-based readout system for the LHCb experiment

The ALICE TPC Readout Control Unit 10th Workshop on Electronics for LHC and future Experiments September 2004, BOSTON, USA

Trigger and DAQ systems (at the LHC)

Computer buses and interfaces

Module 6: INPUT - OUTPUT (I/O)

Computer Science 146. Computer Architecture

First LHCb measurement with data from the LHC Run 2

THE ATLAS DATA ACQUISITION SYSTEM IN LHC RUN 2

PoS(EPS-HEP2017)523. The CMS trigger in Run 2. Mia Tosi CERN

A generic firmware core to drive the Front-End GBT-SCAs for the LHCb upgrade

MiniDAQ1 A COMPACT DATA ACQUISITION SYSTEM FOR GBT READOUT OVER 10G ETHERNET 22/05/2017 TIPP PAOLO DURANTE - MINIDAQ1 1

IBM Network Processor, Development Environment and LHCb Software

Lecture 28: Networks & Interconnect Architectural Issues Professor Randy H. Katz Computer Science 252 Spring 1996

The performance of the ATLAS Inner Detector Trigger Algorithms in pp collisions at the LHC

The Intelligent FPGA Data Acquisition

Tracking and flavour tagging selection in the ATLAS High Level Trigger

Chapter Operation Pinout Operation 35

How to Choose the Right Bus for Your Measurement System

An Upgraded ATLAS Central Trigger for 2015 LHC Luminosities

CS 162 Operating Systems and Systems Programming Professor: Anthony D. Joseph Spring Lecture 19: Networks and Distributed Systems

TCP Strategies. Keepalive Timer. implementations do not have it as it is occasionally regarded as controversial. between source and destination

ELEC / COMP 177 Fall Some slides from Kurose and Ross, Computer Networking, 5 th Edition

b-jet identification at High Level Trigger in CMS

High Bandwidth Electronics

Introduction Electrical Considerations Data Transfer Synchronization Bus Arbitration VME Bus Local Buses PCI Bus PCI Bus Variants Serial Buses

A closer look at network structure:

Level-1 Regional Calorimeter Trigger System for CMS

L1 and Subsequent Triggers

Data Reconstruction in Modern Particle Physics

An ATCA framework for the upgraded ATLAS read out electronics at the LHC

The Network Layer and Routers

1. Introduction 2. Methods for I/O Operations 3. Buses 4. Liquid Crystal Displays 5. Other Types of Displays 6. Graphics Adapters 7.

Stefan Koestner on behalf of the LHCb Online Group ( IEEE - Nuclear Science Symposium San Diego, Oct.

Fast pattern recognition with the ATLAS L1Track trigger for the HL-LHC

A Fast Ethernet Tester Using FPGAs and Handel-C

Status and Prospects of LHC Experiments Data Acquisition. Niko Neufeld, CERN/PH

Electronics on the detector Mechanical constraints: Fixing the module on the PM base.

Chapter 1. Computer Networks and the Internet

SPECS : A SERIAL PROTOCOL FOR EXPERIMENT CONTROL SYSTEM IN LHCB.

CMSC 611: Advanced. Interconnection Networks

More on IO: The Universal Serial Bus (USB)

Control and Monitoring of the Front-End Electronics in ALICE

2/29/2012. Part 1: Networking overview Part 2: Data transfer methods Part 3: Communication Channels

CS455: Introduction to Distributed Systems [Spring 2018] Dept. Of Computer Science, Colorado State University

Implementing Online Calibration Feed Back Loops in the Alice High Level Trigger

The ATLAS Trigger System: Past, Present and Future

PETsys SiPM Readout System

Track reconstruction with the CMS tracking detector

DESIGN AND IMPLEMENTATION OF AN AVIONICS FULL DUPLEX ETHERNET (A664) DATA ACQUISITION SYSTEM

Modules and Front-End Electronics Developments for the ATLAS ITk Strips Upgrade

STANDARD I/O INTERFACES

Dominique Gigi CMS/DAQ. Siena 4th October 2006

Stephen J. Gowdy (CERN) 12 th September 2012 XLDB Conference FINDING THE HIGGS IN THE HAYSTACK(S)

Scenarios for a ROB system built with SHARC processors. Jos Vermeulen, 7 September 1999 Paper model results updated on 7 October 1999

TOF Electronics. J. Schambach University of Texas Review, BNL, 2 Aug 2007

Modeling and Validating Time, Buffering, and Utilization of a Large-Scale, Real-Time Data Acquisition System

CS 162 Operating Systems and Systems Programming Professor: Anthony D. Joseph Spring Lecture 20: Networks and Distributed Systems

A generic firmware core to drive the Front-End GBT-SCAs for the LHCb upgrade

Network Superhighway CSCD 330. Network Programming Winter Lecture 13 Network Layer. Reading: Chapter 4

Interconnection Structures. Patrick Happ Raul Queiroz Feitosa

Lectures More I/O

Module Performance Report. ATLAS Calorimeter Level-1 Trigger- Common Merger Module. Version February-2005

Advanced Computer Networks

Software and computing evolution: the HL-LHC challenge. Simone Campana, CERN

DAQ and ECS Ethernet cabling in UXA85

The Track-Finding Processor for the Level-1 Trigger of the CMS Endcap Muon System

Lecture 9: Bridging. CSE 123: Computer Networks Alex C. Snoeren

Commissioning of the ALICE data acquisition system

Distributed Queue Dual Bus

Transcription:

Data Acquisition Systems CERN Summerstudent Programme 2008 Niko Neufeld, CERN-PH

Introduction Data Acquisition is a specialized engineering discipline thriving mostly in the eco-system of large science experiments, particularly in HEP It consists mainly of electronics, computer science, networking and (we hope) a little bit of physics Some material and lots of inspiration for this lecture was taken from lectures by my predecessors Many thanks to S. Suman for his help with the drawings! Data Acquisition Systems, CERN Summerstudent Lecture 2008 2

Outline Introduction Data acquisition The first data acquisition campaign A simple DAQ system One sensor More and more sensors Read-out with buses Crates & Mechanics The VME Bus Read-out with networks A DAQ for a large experiment Sizing it up Trigger Front-end Electronics Readout with networks Event building in switched networks Problems in switched networks A lightning tour of ALICE, ATLAS, CMS and LHCb DAQs Data Acquisition Systems, CERN Summerstudent Lecture 2008 3

Disclaimer Trigger and DAQ are two vast subjects covering a lot of physics and electronics Based entirely on personal bias I have selected a few topics While most of it will be only an overview at a few places we will go into some technical detail Some things will be only touched upon or left out altogether information on those you will find in the references at the end Electronics (lectures by J. Christiansen) High Level Trigger (lectures by G. Dissertori) DAQ of experiments outside HEP/LHC Management of large networks and farms High-speed mass storage Experiment Control (= Run Control + Detector Control / DCS) Data Acquisition Systems, CERN Summerstudent Lecture 2008 4

Tycho Brahe and the Orbit of Mars I've studied all available charts of the planets and stars and none of them match the others. There are just as many measurements and methods as there are astronomers and all of them disagree. What's needed is a long term project with the aim of mapping the heavens conducted from a single location over a period of several years. Tycho Brahe, 1563 (age 17). First measurement campaign Systematic data acquisition Controlled conditions (same time of the day and month) Careful observation of boundary conditions (weather, light conditions etc ) - important for data quality / systematic uncertainties Data Acquisition Systems, CERN Summerstudent Lecture 2008 5

The First Systematic Data Acquisition Data acquired over 18 years, normally e every month Each measurement lasted at least 1 hr with the naked eye Red line (only in the animated version) shows comparison with modern theory Data Acquisition Systems, CERN Summerstudent Lecture 2008 6

Tycho s DAQ in Today s Terminology Bandwith (bw) = Amount of data transferred / per unit of time Transferred = written to his logbook unit of time = duration of measurement bw Tycho = ~ 100 Bytes / h (compare with LHCb 40.000.000.000 Bytes / s) Trigger = in general something which tells you when is the right moment to take your data In Tycho s case the position of the sun, respectively the moon was the trigger the trigger rate ~ 3.85 x 10-6 Hz (compare with LHCb 1.0 x 10 6 Hz) Data Acquisition Systems, CERN Summerstudent Lecture 2008 7

Some More Thoughts on Tycho Tycho did not do the correct analysis of the Mars data, this was done by Johannes Kepler (1571-1630), eventually ypaving the way for Newton s laws Morale: the size & speed of a DAQ system are not correlated with the importance of the discovery! Data Acquisition Systems, CERN Summerstudent Lecture 2008 8

A Very Simple Data Acquisition System

Measuring Temperature Suppose you are given a Pt100 thermo-resistor We read the temperature as a voltage with a digital voltmeter Data Acquisition Systems, CERN Summerstudent Lecture 2008 10

Reading Out Automatically Note how small the sensor has become. In DAQ we normally need not worry about the details of the things we readout #include <libusb.h> struct usb_bus *bus; struct usb_device *dev; usb_dev_handle *vmh = 0; usb_find_busses(); usb_find_devices(); for (bus = usb_busses; bus; bus = bus->next) for (dev = bus->devices; dev; dev = dev- >next) if (dev->descriptor.idvendor descriptor idvendor == HOBBICO) vmh = usb_open(dev); usb_bulk_read(vmh,3,&u,sizeof(float),500); USB/RS232 Data Acquisition Systems, CERN Summerstudent Lecture 2008 11

Read-out 16 Sensors Buy 4 x 4-port USB hub (very cheap) (+ 3 more voltmeters) Adapt our little DAQ p g program No fundamental (architectural) change h to t our DAQ Data Acquisition Systems, CERN Summerstudent Lecture 2008 12

Read-out 160 Sensors For a moment we (might) consider to buy 52 USB hubs, 160 Voltmeters but hopefully we abandon the idea very yquickly, before we start cabling this! Expensive, cumbersome, fragile our data acquisition system is not scalable Data Acquisition Systems, CERN Summerstudent Lecture 2008 13

Read-out with Buses

A Better DAQ for Many (temperature) Sensors 7U VME Crate (a.k.a. Subrack ) 19 VME Board Plugs into Backplane 7U Backplane Connectors (for power and data) Buy or build a compact multi-port volt-meter module, e.g. 16 inputs Put many of these multi-port modules together in a common chassis or crate The modules need Mechanical support Power A standardized way to access their data (our measurement values) All this is provided by standards for (readout) electronics such as VME (IEEE 1014) Data Acquisition Systems, CERN Summerstudent Lecture 2008 15

DAQ for 160 Sensors Using VME Readout boards in a VME-crate mechanical standard for electrical standard for power on the backplane signal and protocol standard for communication on a bus Data Acquisition Systems, CERN Summerstudent Lecture 2008 16

A Word on Mechanics and Pizzas The width and height of racks and crates are measured in US units: inches (in, '') and U 1 in = 25.4 mm 1 U = 1.75 in = 44.45 mm The width of a "standard" rack is 19 in. The height of a crate (also sub-rack) is measured in Us Rack-mountable things, in particular computers, which are 1 U high are often called pizza-boxes At least in Europe, the depth is measured in mm Gory details can be found in IEEE 1101.x (VME mechanics standard) 49 U Data Acquisition Systems, CERN Summerstudent Lecture 2008 17

Communication in a Crate: Buses A bus connects two or more devices and allows them to communicate The bus is shared between all devices on the bus arbitration is required Devices can be masters or slaves (some can be both) Devices can be uniquely identified ("addressed") on the bus Master Slave Slave Master Device 1 Device 22 Device 3 Device 4 Data Lines Data Acquisition Systems, CERN Summerstudent Lecture 2008 Select Line 18

Buses Famous examples: PCI, USB, VME, SCSI older standards: CAMAC, ISA upcoming: ATCA many more: FireWire, I2C, Profibus, etc Buses can be local: PCI external peripherals: USB in crates: VME, compactpci, ATCA long distance: CAN, Profibus Data Acquisition Systems, CERN Summerstudent Lecture 2008 19

The VME Bus 0x000-0x1ff 0x200-0x2ff 0x300-0x3ff 0x400-0x4ff 0x500-0x5ff 0 5 0x600-0x6ff In a VME crate we can find three main types of modules The controller which monitors and arbitrates the bus Masters read data from and write data to slaves Slaves send data to and receive data from masters Addressing of modules In VME each module occupies a part of a (flat) range of addresses (24 bit to 32 bit) Address range of modules is hardwired (conflicts!) Data Acquisition Systems, CERN Summerstudent Lecture 2008 20

VME protocol 1) Arbitration Abit Arbitration: ti Master asserts *) BR#, Controller answers by asserting BG# If there are several masters requesting at the same time the one physically closest to the controller wins The winning master drives BBSY* high to indicate that the bus is now in use Pictures from http://www.interfacebus.com com *) assert means driving the line to logical 0 (VME control lines are inverted or active-low) Data Acquisition Systems, CERN Summerstudent Lecture 2008 21

VME protocol 2) Write transfer The Master writes data and address to the data a / respectively e data bus It asserts DS* and AS* to signal that the data and address are valid The slave reads and acknowledges by asserting DTACK The master releases DS*, AS* and BSBSY*, the cycle is complete Note: there is no clock! The slave can respond whenever it wants. VME is an asynchronous bus Data Acquisition Systems, CERN Summerstudent Lecture 2008 22

Speed Considerations Theoretically ~ 16 MB/s can be achieved assuming the databus to be full 32-bit wide the master never has to relinquish i bus master ship Better performance by using blocktransfers Data Acquisition Systems, CERN Summerstudent Lecture 2008 23

VME protocol 3) Block transfer After an address cycle several (up to 256) data cycles are performed The slave is supposed to increment the address counter The additional delays for asserting and Block transfers are essential acknowledging the for Direct Memory Access address are removed (DMA) Performance goes More performance can be up to 40 MB/s gained by using the address In PCI this is referred bus also for data (VME64) to as "burst-transfer" transfer Data Acquisition Systems, CERN Summerstudent Lecture 2008 24

Advantages of buses Relatively l simple to implement Constant number of lines Each device implements the same interface Easy to add new devices topological l information of the bus can be used for automagically choosing addresses for bus devices: this is what plug and play is all about. Data Acquisition Systems, CERN Summerstudent Lecture 2008 25

Buses for DAQ at LHC? A bus is shared between all devices (each new active device slows everybody down) Bus-width can only be increased up to a certain point (128 bit for PC-system bus) Bus-frequency (number of elementary operations per second) can be increased, but decreases the physical bus-length Number of devices and physical bus-length is limited (scalability!) For synchronous high-speed buses, physical length is correlated with the number of devices (e.g. PCI) Typical buses have a lot of control, data and address lines (look at a SCSI or ATA cable) Buses are typically y useful for systems < 1 GB/s Data Acquisition Systems, CERN Summerstudent Lecture 2008 26

Network based DAQ In large (HEP) experiments we typically y have thousands of devices to read, which are sometimes very far from each other Network technology solves the scalability issues of buses In a network devices are equal ("peers") In a network devices communicate directly with each other no arbitration necessary bandwidth guaranteed data and control use the same path much fewer lines (e.g. in traditional Ethernet t only two) At the signaling level buses tend to use parallel copper lines. Network technologies can be also optical, wire-less and are typically (differential) serial Data Acquisition Systems, CERN Summerstudent Lecture 2008 27

Network Technologies Examples: The telephone network Ethernet (IEEE 802.3) ATM (the backbone for GSM cell-phones) Infiniband Myrinet many, many more Note: some of these have "bus"-features as well (Ethernet, Infiniband) Network technologies are sometimes functionally grouped Cluster interconnect (Myrinet, Infiniband) 15 m Local area network (Ethernet), 100 m to 10 km Wide area network (ATM, SONET) > 50 km Data Acquisition Systems, CERN Summerstudent Lecture 2008 28

Connecting Devices in a Network On an network a device is identifed by a network address eg: our phone-number, the MAC address of your computer Devices communicate by sending messages (frames, packets) to each other Some establish a connection lilke the telephone network, some simply send messages Modern networks are switched with point-to- point links circuit switching, packet switching Data Acquisition Systems, CERN Summerstudent Lecture 2008 29

Switched Networks In a switched network each node is connected either to another node or to a switch Switches can be connected to other switches A path from one node to another leads through 1 or more switches (this number is sometimes referred to as the number of "hops" ) Data Acquisition Systems, CERN Summerstudent Lecture 2008 30

A Switched Network 2 3 1 4 5 While 2 can send data to 1 and 4, 3 can send at full speed to 5 2 can distribute the share the bandwidth between 1 and 4 as needed Data Acquisition Systems, CERN Summerstudent Lecture 2008 31

Switches Switches are the key to good network performance They must move frames reliably and as fast as possible between nodes They face two problems Finding the right path for a frame Handling congestion (two or more frames want to go to the same destination at the same time) Data Acquisition Systems, CERN Summerstudent Lecture 2008 32

Ethernet Cheap Unreliable but in practice transmission errors are very low Available in many different speeds and physical media We use IP or TCP/IP over Ethernet By far the most widely used local area network technology (even starting ti on the WAN) Data Acquisition Systems, CERN Summerstudent Lecture 2008 33

IP Packets over Ethernet e Ethernet Header IP Header UDP Header Data 0 32 bits Data Acquisition Systems, CERN Summerstudent Lecture 2008 34

Data Acquisition for a Large Experiment

Moving on to Bigger Things The CMS Detector Data Acquisition Systems, CERN Summerstudent Lecture 2008 36

Moving on to Bigger Things 15 million detector channels @ 40 MHz = ~15 * 1,000,000 * 40 * 1,000,000 bytes = ~ 600 TB/sec? Data Acquisition Systems, CERN Summerstudent Lecture 2008 37

Designing a DAQ System for a Large HEP Experiment What defines "large"? The number of channels: for LHC experiments O(10 7 ) channels a (digitized) channel can be between 1 and 14 bits The rate: for LHC experiments everything happens at 40.08 MHz, the LHC bunch crossing frequency (This corresponds to 24.9500998 ns or 25 ns among friends) HEP experiments usually consist of many different sub-detectors: tracking, calorimetry, particle-id, muon-detectors Data Acquisition Systems, CERN Summerstudent Lecture 2008 38

First Questions Can we or do we want to save all the data? How do we select the data Is continuous read-out needed, i.e. an experiment in a collider? Or are there idle periods mixed with periods with many events this is typically the case for fixedtarget experiments How do we make sure that the values from the many different channels refer to the same original event (collision) Data Acquisition Systems, CERN Summerstudent Lecture 2008 39

What Do We Need to Read Out a Detector t (successfully)? A selection mechanism ( trigger ) Electronic readout of the sensors of the detectors ( front-end electronics ) A system to keep all those things in sync ( clock ) A system to collect the selected data ( DAQ ) A Control System to configure, control and monitor the entire DAQ Data Acquisition Systems, CERN Summerstudent Lecture 2008 40

Trigger No (affordable) DAQ system could read out O(10 7 ) channels at 40 MHz 400 TBit/s to read out even assuming binary channels! What s worse: most of these millions of events per second are totally uninteresting: one Higgs event every 0.02 seconds A first levell ti trigger (Level-1, l1 L1) must somehow select the more interesting events and tell us which h ones to deal with any further Black magic happening here Data Acquisition Systems, CERN Summerstudent Lecture 2008 41

Inside the Box: How does a Level-1trigger work? Millions of channels : try to work as much as possible with local information Keeps number of interconnections low Must be fast: look for simple signatures Keep the good ones, kill the bad ones Robust, can be implemented in hardware (fast) Design principle: fast: to keep buffer sizes under control every 25 nanoseconds (ns) a new event: have to decide within a few microseconds (μs): triggerlatency Data Acquisition Systems, CERN Summerstudent Lecture 2008 42

Challenges for the L1 at LHC N (channels) ~ O(10 7 ); 20 interactions every 25 ns need huge number of connections Need to synchronize detector elements to (better than) 25 ns In some cases: detector signal/time of flight > 25 ns integrate more than one bunch crossing's worth of information need to identify bunch crossing... It's On-Line (cannot go back and recover events) need to monitor selection - need very good control over all conditions Data Acquisition Systems, CERN Summerstudent Lecture 2008 43

Know Your Enemy: pp Collisions at 14 TeV at 10 34 cm -2 s -1 σ(pp) = 70 mb --> >7 x 10 8 /s (!) In ATLAS and CMS * 20 min bias events will overlap H ZZ Z μμ H 4muons: the cleanest ( golden ) signature Reconstructed tracks with pt > 25 GeV And this (not the H though ) repeats every 25 ns *) LHCb @2x10 33 cm -2-1 isn t much nicer and in Alice (PbPb) it will be even worse Data Acquisition Systems, CERN Summerstudent Lecture 2008 44

Mother Nature is a Kind Woman After All pp collisions produce mainly hadrons with transverse momentum p t ~1GeV Interesting physics (old and new) has particles (leptons and hadrons) with large p t : p t W eν: M(W)=80 GeV/c 2 ; p t (e) ~ 30-40 GeV H(120 GeV) γγ: p t (γ) ~ 50-60 GeV B μd *+ ν p t (μ) ~ 1.4 GeV p t p Impose high thresholds on the p t of particles Implies distinguishing particle types; possible for electrons, muons and jets ; beyond that, need complex algorithms Conclusion: in the L1 trigger we need to watch out for high transverse momentum electrons, jets or muons Data Acquisition Systems, CERN Summerstudent Lecture 2008 45

How to defeat minimum bias: transverse momentum p t Use prompt p data (calorimetry and muons) to identify: High p t electron, muon, jets, missing E T γ ν e µ MUON System Segment and track finding φ η n CALORIMETERs Cluster finding and energy deposition evaluation p New data every 25 ns Decision latency ~ µs Data Acquisition Systems, CERN Summerstudent Lecture 2008 46

Distributing the L1 Trigger Assuming now that a magic box tells for Gl b l T i 1 each bunch crossing (clock-tick) c yes or no Triggering is not for philosophers perhaps is not an option This decision has to be brought for each crossing to all the detector front-end electronics elements so that they can send of their data or discard it Local level-1 trigger Global Trigger 1 Primitive e, γ, jets, µ Front-End Digitizer Pipeline delay ( 3 µs) Accept/Reject LV-1 2-3 µs latency loop Trigger Primitive Generator Data Acquisition Systems, CERN Summerstudent Lecture 2008 47

Clock Distribution and Synchronisation An event is a snapshot of the values of all detector t front-end electronics elements, which have their value caused by the same collision A common clock signal must be provided to all detector elements Since the c is constant, the detectors are large and the electronics is fast, the detector elements must be carefully time-aligned Common system for all LHC experiments TTC based on radiation-hard optoelectronics 40 MHz Plus: Trigger decision Bunch cross ID Data Acquisition Systems, CERN Summerstudent Lecture 2008 48

Bird s-eye View on (front-end) Electronics clock (TTC) All this explained in great detail by J. Christiansen this week --> focus on the green arrow on beyond Detector Amplifier Filter Shaper Range compression Sampling Digital filter Zero suppression Buffer Feature extraction Buffer Format & Readout to Data Acquisition System Data Acquisition Systems, CERN Summerstudent Lecture 2008 49

FEE & DAQ by electronics engineers FEE = Front End Electronics Example from LHCb Data Acquisition Systems, CERN Summerstudent Lecture 2008 50

Data Acquisition Event-data are now digitized, preprocessed and tagged with a unique, monotonically increasing number The event data are distributed over many read-out boards ( sources ) For the next stage of selection, or even simply to write it to tape we have to get the pieces of the event together: event building Data Acquisition Systems, CERN Summerstudent Lecture 2008 51

Event Building

Event Building To Trigger Algorithms Event Builder 3 Data Acquisition Switch Event Builder 3 Event Builder 3 1Event fragments are 2Event fragments are builder read a3event 4Complete events are 1received from out over detector front-end2read 3assembles fragments by trigger network to an event into a complete event4processed algorithms builder Data Acquisition Systems, CERN Summerstudent Lecture 2008 53

Push-Based Event Building Switch Buffer Event Builder 1 Data Acquisition Switch Event Builder 2 Readout Supervisor Send next event Send to EB1 next event to EB2 1Readout Supervisor 1tells readout boards where events must be sent (round-robin) 2Readout boards do 2not buffer, so switch must 3No feedback from 3Event Builders to Readout system Data Acquisition Systems, CERN Summerstudent Lecture 2008 54

Congestion 1 3 2 2 Bang "Bang" translates into random, uncontrolled packet-loss In Ethernet this is perfectly valid behavior and implemented by very cheap devices Higher Level protocols are supposed to handle the packet loss due to lack of buffering This problem comes from synchronized sources sending to the same destination at the same 2 time Data Acquisition Systems, CERN Summerstudent Lecture 2008 55

Overcoming Congestion: Queuing at the Input 1 3 2 2 2 Two frames destined to the same destination arrive While one is switched through the other is waiting at the input port When the output port is free the queued packet is sent Data Acquisition Systems, CERN Summerstudent Lecture 2008 56

Pull-Based Event Building EB1: EB2: EB3: Data Acquisition Switch 01 1 0 Send next event Send 0 1 to next Send EB1 event next to EB2 event to EB3 Send Send me me an an event! event! E v Event Builder 1 e n t Event Builder Send 2 me B an event! u i l Event Builder 3 Send dme an event! e r 1 1Event Builders notify 1Readout Supervisor of available capacity 2Readout Supervisor 2ensures that data are sent only to nodes with available capacity 3Readout system 3relies on feedback from Event Builders Data Acquisition Systems, CERN Summerstudent Lecture 2008 57

Head of Line Blocking 1 3 2 24 2 The reason for this is the First in First Out (FIFO) structure of the input buffer Queuing Packet to theory node 4 must tells wait us* that t for random traffic even though port to node 4 is free (and infinitely many switch ports) the throughput of the switch will go down to 58.6% that means on 100 MBit/s network the nodes will "see" effectively only ~ 58 MBit/s 4 *) "Input Versus Output Queueing on a Space- Division Packet Switch"; Karol, M. et al. ; IEEE Trans. Comm., 35/12 Data Acquisition Systems, CERN Summerstudent Lecture 2008 58

Output Queuing 1 3 2 24 In practice virtual output queueing is used: at each input there is a queue for n ports O(n 2 ) queues must be managed Assuming the buffers are large enough(!) port such 2. Way a to switch node 4 will is free sustain random traffic at 100% nominal link load Packet to node 2 waits at output to 4 2 Data Acquisition Systems, CERN Summerstudent Lecture 2008 59

AACL ALICE, ATLAS, CMS, LHCb DAQs in 4 slides

ALICE DAQ Rare/All BUSY CTP LTU TTC L0, L1a, L2 L0, L1a, L2 FERO FERO Event 144 DDLs 342 DDLs Fragment 416 D-RORC BUSY LTU TTC FERO FERO DDL H-RORC 10 DDLs 10 D-RORC FEP FEP HLT Farm Load Bal. LDC 194 Detector LDC LDC LDC 10 HLT LDC LDC LDC EDM Sub-event Event File GDC Two stage hardware trigger L0 + L1 High Level Trigger (HLT) on separate farm Event Building Network 2500 MB/s GDC GDC GDC Storage Network 1250 MB/s TDS 50 GDC 25 TDS TDS DS DS 5 DSS PDS Data Acquisition Systems, CERN Summerstudent Lecture 2008 61

ATLAS DAQ ATLAS L1 selects events at 100 khz and defines regions of interest L2 pulls data from the region of interest and processes the data in a farm of processors L2 accepts data at ~ 1 khz Event Filter reads the entire detector (pull), processes the events in a farm and accepts at 100 Hz Data Acquisition Systems, CERN Summerstudent Lecture 2008 62 62

CMS DAQ Congestion is handled by synchronizing the sources to send in discrete time- slots: Barrel Shifting Collision rate 40 MHz Level-1 1Maximum trigger ti rate 100 khz Average event size 1 Mbyte Event Flow Control 10 6 Mssg/s No. of In-Out units 512 Readout network bandwidth 1T Terabit/s Event filter computing power 10 6 SI95 Data production Tbyte/day No. of PC motherboards Thousands Data Acquisition Systems, CERN Summerstudent Lecture 2008 63

LHCb DAQ L0 Trigger L0 trigger LHC clock TFC System 80 MB/s SWITCH C C C C P P P P U U U U MON farm MEP Request Event data Timing and Fast Control Signals Control and Monitoring data Detector VELO ST OT RICH ECal HCal Muon FE Electronics Readout Board 40 GB/s FE Electronics FE Electronics FE Electronics FE Electronics FE Electronics FE Electronics Readout Readout Readout Readout Readout Readout Board Board Board Board Board Board Front-End READOUT NETWORK Event building SWITCH SWITCH SWITCH SWITCH SWITCH SWITCH C C C C C C C C C C C C C C C C C C C C C C C C P P P P P P P P P P P P P P P P P P P P P P P P U U U U U U U U U U U U U U U U U U U U U U U U HLT farm Experim ment Contro ol System (ECS) Average event size 40 kb Average rate into farm 1 MHz Average rate to tape 2 khz Data Acquisition Systems, CERN Summerstudent Lecture 2008 64

LHC Experiments DAQ Level-1 Event Storage khz MByte MByte/s ATLAS 100 1 100 CMS 100 1 100 LHCb 1000 0.04 80 ALICE 1 25 1250 Data Acquisition Systems, CERN Summerstudent Lecture 2008 65

High Level Trigger Complicated Event structure with hadronic jets (ATLAS) or secondary vertices (LHCb) require full detector information Methods and algorithms are the same as for offline reconstruction (Lecture (ecue From raw data daato ophysics ) yscs) Data Acquisition Systems, CERN Summerstudent Lecture 2008 66

On to tape...and the GRID Networks, farms and data flows To regional centers 622 Mbit/s Remote control rooms Controls: 1 Gbit/s Events: 10 Gbit/s Controls: 1 Gbit/s Raw Data: 1000 Gbit/s Data Acquisition Systems, CERN Summerstudent Lecture 2008 67

Further Reading Buses Conferences VME: http://www.vita.com/ PCI http://www.pcisig.com/ Network and Protocols Ethernet Ethernet: The Definitive Guide, O Reilly, C. Spurgeon TCP/IP TCP/IP Illustrated, W. R. Stevens Protocols: RFCs www.ietf.org in particular RFC1925 http://www.ietf.org/rfc/rfc1925.txt The 12 networking truths th is required reading Wikipedia (!!!) and references therein for all computing related stuff this is usually excellent IEEE Realtime ICALEPCS CHEP IEEE NSS-MIC Journals IEEE Transactions on Nuclear Science, in particular the proceedings of the IEEE Realtime conferences IEEE Transactions on Communications Data Acquisition Systems, CERN Summerstudent Lecture 2008 68