HIGH SPEED SIX OPERANDS 16-BITS CARRY SAVE ADDER AWATIF BINTI HASHIM SCHOOL OF MICROELECTRONIC ENGINEERING UNIVERSITI MALAYSIA PERLIS 2007
HIGH SPEED SIX OPERANDS 16-BITS CARRY SAVE ADDER by AWATIF BINTI HASHIM Report submitted in partial fulfillment of the requirements for the degree of Bachelor of Engineering MARCH 2007
ACKNOWLEDGEMENT I am greatly would like to express my gratitude to my supervisor, Madam Norina Idris, for her overall supports, patience, supervised, guidance throughout the project development and for her confidence in me and my work. She did her best to help and relieve concerns. It has been memorable that she encouraged and supported me while I was in deep depression and faced problems in completing this project. I am greatly indebted to the Integrated Circuit Laboratory who contributed Altera UP2 board that being used in the hardware development. Without their support, I would never proceed into hardware part that cost lots. Also for the complete device provided and perfect working environment in laboratory. Thanks for my group under the same supervisor that giving me indebted information needed for completing this project. I appreciate for their supports and will to help me during designing and implement the design into hardware. Last but not least, my special gratitude for my parents for their support during my education and for their understanding and tolerance during this project.
APPROVAL AND DECLARATION SHEET This project report titled High-Speed Six Operands 16-bits Carry Save Adder was prepared and submitted by Awatif Binti Hashim ( Matrix Number: 031030048 ) and has been found satisfactory in terms of scope, quality and presentation as partial fulfillment of the requirement for the Bachelor of Engineering ( Electronic Engineering ) in Universiti Malaysia Perlis ( UniMAP ). Checked and Approved by (MADAM NORINA IDRIS) Project Supervisor School of Microelectronic Engineering Universiti Malaysia Perlis March 2007
Enam Penambahan bagi 16-bit Pembawa Penyimpan Penambah (CSA) Berkelajuan Tinggi ABSTRAK Penambah banyak dijumpai dalam gabungan blok-blok mikroproses dan juga cip digital isyarat proses. Kajian yang lepas menyatakan penyebaran yang lambat dan saiz adalah faktor penting dalam menentukan kualiti sesuatu penambah. Tujuan projek ini dibuat adalah untuk implimentasi 3 tahap/peringkat 6 operasi penambah bagi 16-bit Pembawa Penyimpan Penambah CSA dengan Pembawa Riak Penambah (RCA) pada akhir rekaan litar. Objektif projek ini adalah untuk merekacipta pelaksanaan lebih cepat bagi CSA dengan menggunakan rekaan get-get logik dan implimentasikannya pada litar Altera UP2. Projek ini disimulasi dan hasilnya dapat dilihat dengan jelas menggunakan perisian Quartus II dan litar Altera UP2 untuk mengesahkan senibina rekabentuk. Litar yang berkelajuan tinggi telah direka dengan cara mencari kelambatan yg paling sedikit antara lima jenis litar Full Adder(FA) dan juga dengan cara menambah litar yang mempengaruhi kelajuan. Projek ini telah mencapai kelajuan dari 16.84MHz ke 90.09MHz laju dengan menggunakan peranti EPF10K70RC240-4. Keputusan menyumbangkan rekabentuk CSA yang lebih laju.
ABSTRACT Adders are commonly found in the critical path of many building blocks of microprocessors and digital signal processing chips. The most important for measuring the quality of adder designs in the past were propagation delay, and area. The purpose of the project is to implement a high-speed three levels six operands of 16-bits CSA with RCA at the end of the design. The objective of this project are design faster execution of CSA using gate logic design and implement it to the Altera UP2 board. The project is simulated and clarifies the output using Quartus II software and Altera UP2 board implementation to verify the design architectures. The high-speed circuit was designed by using smallest delay between five different logic gates Full Adder (FA) and by adding pipeline. This project has been achieved from 16.84MHz to the 90.09MHz speed on EPF10K70RC240-4 device. This result contribute CSA is in faster speed.
TABLE OF CONTENTS ACKNOWLEDGEMENT APPROVAL AND DECLARATION SHEET ABSTRAK ABSTRACT TABLE OF CONTENTS LIST OF TABLES LIST OF FIGURES Page i ii iii iv v viii ix CHAPTER 1 INTRODUCTION 1 1.1 Background of Project 1 1.2 Application of CSA 1 CHAPTER 2 LITERATURE REVIEW 3 2.1 Introduction 3 2.2 Multioperand Carry-Save Adder (CSA) 3 2.3 Number Systems 5 2.4 Basic Function of Boolean Algebra in Full Adder (FA) 7 2.5 Multilevel Carry-Save Adder 11 2.6 Ripple Carry Adder 13 2.7 Design Circuit 14 2.8 Delay 2.8.1 CSA 2.8.2 Ripple Carry Adder 16 16 16
2.9 Applications of CSA 2.10 Advantages 2.11 Characteristics 2.11.1 Transistor Sizing 2.11.2 Propagation Delay 2.11.3 CMOS Technology 2.11.4 Pipelining 17 18 18 18 18 19 19 CHAPTER 3 METHODOLOGY 22 3.1 Introduction 22 3.2 Research 22 3.3 Analyze 3.3.1 Software 3.3.2 Hardware 3.3.2.1 Seven segment display 23 23 34 36 CHAPTER 4 RESULTS AND DISCUSSION 38 4.1 Introduction 38 4.2 Result and discussion 38 4.2.1 Output waveform delay 38 4.2.2 Speed 44 4.3 Conclusion 46 CHAPTER 5 CONCLUSION 47 5.1 Summary 47 5.2 Recommendation For Future Project 48 5.3 Commercialize Potential 48 REFERENCES 49
APPENDICES Appendix A Appendix B Appendix C Appendix D 53 54 55 56 65
LIST OF TABLE Tables No. Page 2.1 Truth table of CSA 5 2.2 Truth table of number system 7 2.3 FA truth table 10 2.4a AND gate truth table 10 2.4b Negative-OR gate truth table 10 2.4c NAND gate truth table 10 2.4d XOR gate truth table 10 2.5 The number of level in a CSA tree for k operands 12 2.6 Truth Table of D Flip-Flop 21 3.1 Truth table of 16-bit CSA 27 3.2 Truth table of 7 segment logic 37 4.1 Comparison delay between FA circuits design 39 4.2 The analysis data throughout achieves design 46
LIST OF FIGURE Figures No. 2.1 The 1-bit carry save adder block is the same circuit as a full adder. Page 4 2.2 The 4-bit carry save adder block diagram 4 2.3 The example calculation of CSA 6 2.4 Full adder using XOR, OR and AND gate 8 2.5 Full adder using AND and XOR gate 8 2.6 Full adder using XOR, NAND and negative-or gate logic 9 2.7 Full adder using XOR and NAND gate 9 2.8 Full adder using XOR gate and 2 to 1 Multiplexer 9 2.9 CSA tree 11 2.10 4-bit ripple carry adder circuit diagram 13 2.11 Basic Design of n-bit CSA 14 2.12 6 operands of 16-bit CSA using (3,2) counter 15 2.13 Pipeline applications in 16-bit CSA 20 2.14 Pipelining Timing Diagram 20 3.1 Flow chart of research 23 3.2 16-bit CSA 24 3.3 Six operands of 16-bits CSA 25 3.4 3 level Six operands of 16-bits CSA with RCA 26 3.5 Flow Chart of level 1 analysis stage 29
3.6 Flow Chart of level 2 analysis stage 30 3.7 The non-pipeline 6 operands of 3 level 16-bit CSA with RCA logic design 31 3.8 The modified 6 operands of 3 level 16-bit CSA logic design 32 3.9 The modified 3 level 6 operands of 3 level 16-bit CSA logic design 33 3.10 Altera UP-2 Training Board Block Diagram 35 3.11 Seven segment display pins 36 3.12 Pin connection diagram 36 3.13 Hardware Design Circuit Test 37 4.1 The functional simulation mode waveform of FA 39 4.2 The timing simulation mode waveform of FA 40 4.3 Longest delay of FA circuit design 40 4.4 The functional simulation mode waveform of 16-bit CSA 40 4.5 The timing simulation mode waveform of 16-bit CSA 41 4.6 The longest delay of 16-bit CSA 42 4.7 The functional simulation mode waveform of modified 16-bit CSA 42 4.8 The timing simulation mode waveform of modified 16-bit CSA 43 4.9 The longest delay of modified 16-bit CSA 44 4.10 Speed of non-pipeline 3 level 16-bit CSA with RCA 45 4.11 Speed of modified 3 level of 6 operands 16-bit CSA 45 4.12 Speed of modified 3 level of 6 operands 16-bit CSA with RCA 46 4.13 The Altera UP2 board connections to display the design 46