Embedded System Design

Model Paper 2 Seventh Semester B.E. Degree Examination Embedded System Design Time: 3 hrs. Max. Marks: 100 Note: 1. Answer any FIVE full questions, selecting at least two questions from each part. PART - A 1. a. Explain how embedded system application can be interfaced with the internal world. (08 Marks) Ans: Embedded application on inl inded to work with the physical world, sensing various analog or digital signals while controlling, manipulating or responding to others. Local exchange is extended to include distribute and remote systems. The study of basic transaction management consistency models, idemportant systems, and error management continues the thread of designing safe and reliable systems. Digital Busses Analog inputs Digital Bits Analog inputs Embedded System Control signals Communication Hosting application 1. b. Draw and explain a microprocessor Based embedded system. (12 Marks) Ans: The implementation of a microprocessor based embedded system combines the individual pieces into an integrated whole as shown in fig. A microprocessor based embedded system consist of following. System Bus: The systems bus is actually sub divided into three buses, segregated by the information they carry. Address bus, data bus and control bus. The microprocessor controls the whole system, and ultimately the application, by executing a set of instructions called firmware that is stored in Rom in the memory subsytems. To run the application, when power is first turned on, the microprocessor addresses a predefined location 4-Model Question Paper 2.indd 64 8/30/2013 10:46:43 AM

Embedded System Design M. P. 2 Dec. 12 - and fetches, decodes and executes one instruction after another. As each instruction is completed, the processor fetches the next one. Minimal Requirement for an embedded system Address Date Control Data store ram memory Firmware & Rom memory Other physical device I/O interface Internal World Internal World Address decode & other logic Common Interface Internal World Micro processor Realtime clock and Time Base NM1 Watch dog timer When operating in electrically hash environments such as the engine compartment of an automobile, thus is a high probability that electro magnetic noise may cause the system to behave usatically. To address these kind of problem, we add a timer called watch dog timer. Periodically the microprocessor must reset the timer. If it fails to do so, the timer will reset the microprocessor, which generally solves the problem. 2. a. Draw and explain the block diagram of a digital signal processor. (10 Marks) Ans: The DSP is typically used in conjunction with a general-proper processer to perform specialized tasks such as image speech, audio or video processing. The block diagram of a digital signal processor is as shown below. The task performed by the digital signal processor often requires it to interface with analog world. Real world signals are captured through an analog-to-digital converter, processed and returned through a digitalto analog converter. One of the major strengths of the DSP is its ability to perform basic arithmetic computation, such as multiply, add etc. To support-high-speed arithmetic, the device will often implement a multiply-accomulate (MAC) primitive in which a multiply and add to the accumulator is performed in a single operation which is useful in matrix operations. 4-Model Question Paper 2.indd 65

Dec.12 - M. P. 2 Embedded System Design Address Data Control Instruction Bus Interrupt Control cpu dsp code Register array Instruction Memory Data Memory Timers DMA Control Address Data Control Data Bus ALU Multiplier/ Add Shifter Output Input Signal to outside world Signal from outside world Block diagram for a Digital Signal Processor DSP supports a high speed signal processing, the DSP device is architectured as a Havened rather than the clon-numann machine and in corporate multiple computations units, a large number of registers, and wide high-band width data busses. 2. b. What are the commonly used addressing modes. (10 Marks) Ans: The most common used addressing modes include a) Immediate b) Direct-and Indirect c) Register Direct and Register Indirect d) Indexed e) Program counter Relative a) Immediate: An immediate mode instruction uses one of the operand fields, to hold the value of the operand rather than a reference. b) Direct and Indirect Modes: When using the direct and indirect addressing modes, we an working with operand addresses rather than operand values. In both the cases, the first level of address information is contained in the instruction. The difference between the two modes is that, is the direct mode, the contents of the operand field in the instruction one the address of the derived operand, when as in indirect can, the field contains the address of the operand. c) Registers Direct and Register Indirect: The distinction between the register direct and register indirect modes lies in the content of the referenced register. In the former case, the register contains the value of the operand and in the latter case, the address of the operand. The register indirect mode provides the means to easily implement pointer-type operations that are commonly used in C and C++. d) Indexed Mode: The indexed or displacement mode provides support for accessing content type data structures such as arrays. The effective address is computed as the sum of base address and the contents 4-Model Question Paper 2.indd 66

Embedded System Design M. P. 2 Dec. 12 - of the indexing register. It is important to note here that following the execution of the instruction, neither the base address nor the index values are changed. e) Program counter relative modes: In this mode, the values in the program counter serves on the base address, and the program counter is assigned the value of the computed effective address that is the contents of the program counter are modified as a result of executing the instruction. Finally the offset that is added to the program counter is a signed number. 3. a. Explain the following terms a) Access time b) Block size c) Memory Bandwidth d) Latency e) Block access terms f) Page g) Refresh Period (10 Marks) Ans: a) Access time: A time to access a word in memory. Access time specifies to perform a read or write operation. The time is measured from the point at which the access commences until the operation is complete. For read operation that time will be when the data appears at the output port of the device. For a write operation, that time will be when the data is successfully written into the memory. b) Block size: A block is a logical view placed on a collection of words in memory. When quantities of data as transferred within a system, the units of transfer are called blocks. The block size specifies the number of words in such a collection. Fig. shown below illustrate a memory organisation into blocks. Block 0 0...0 Block 1 Block 2.... Block n-1 F...F c) Memory bandwidth: is a measure of the word transmission rate to and from memory via the memory I/O bus. Consider a memory in which the stored data words are in pattern of alternating 0's and 1's as illustrated in fig. shown below. 0 0 0...0 0 0 1 1 1...1 1 1 0 0 0...0 0 0 1 1 1...1 1 1 when the data is read from memory the pattern in each data line will be square wave. The highest frequency of that square wave is the memory bandwidth. d) Latency: is the amount of time required to access the first of a sequence of words. Latency measures the time necessary to compute the address of that sequence and then locate its firstblock of words in memory. e) Block access time: Block access time gives a measure of the time to access an entire block from the start of read. Block access time will include the time to find the 0 th word of a block and then to transfer of the remaining words. f) Page: Page is a logical view placed on larger collection of words in memory. Pages are generally comprised of blocks, the size of a page can be given in words or in blocks. g) Refresh Period: Specifies the maximum period in which all memory cells must be refreshed to ensure that no data is lost. 4-Model Question Paper 2.indd 67

Dec.12 - M. P. 2 Embedded System Design 3. b. Explain how refresh address in generated. (10 Marks) Ans: The refresh address in generated using a 12-bit binary counter as shown in fig. below. RA0 RA11 refresh address refresh active 12 bit binary counter Refresh address generator The counter should be incriminated following the completion of each row refresh operation. During normal read or write operation, the row addresses to the DRAM are provided by the source executing the operation. During a refresh, they are given by the refresh address counter. Thus the DRAM address lines must provide row, then coloumn addresses during normal operation and refresh row address during the refresh cycle. Selection among the three alternatives is a shown below. A0 enable row address A12 MA0 enable column address RA0 enable refresh address A9 enable row address A21 enable column address RA9 enable refresh address A10 enable row address RA10 enable refresh address MA9 MA10 DRAM A11 enable row address RA11 enable refresh address MA11 4-Model Question Paper 2.indd 68

Embedded System Design M. P. 2 Dec. 12-4. a. Briefly explain capitalization Reuse, requirement tracebality and requirement management. (10 Marks) Ans: Capitalization: is activities that are essential to the contemporary design process. Proper and efficient exploitation of intellectual properties is very important. Intellectual properties are designs, often patented that can be sold to another party to develop and sell as their product. The company Mrps, for example designer computer architectures. It does not actually do any implementation itself the design is its product. Reuse: Any consideration of component reuse is an activity to be performed during the functional and architectural design phases of the project. One of the main purposes of reuse is to help designers shorten the development life cycle. Components reuse is facilitated in two ways. Present and future reuse is supported in the present by identifying a set of external functional or architectural components that can satisfy some parts of desired functionality. Future reuse is supported by identifying components in the system under design that will be reusable in other projects or products. Requirement traceabality: Requirement traceability refers to the ability to follow the life of a requirement in both the forward and reverse direction through the entire design process and the design. Traceability is potentially a one to many relationship between a requirement and the components it relates or traces to. Requirement Management: Requirement Management addresses Requirement modification changes Improvements corrections During the design, such changes are difficult to avoid for many reasons. Therefore a clear procedure that facilitates a way to accommodate such modifications has to be used during the whole design process. 4. b. Write a brief note on waterfall and Rapid prototyping. (10 Marks) Ans: Waterfall Model: The waterfall model represents a cycle- specifically a seven of steps appearing much like a waterfall sequentially one below the next as shown below. Specification Review and Revise Primary Design Review and Revise Specification Review and Revise Primary Design Review and Revise 4-Model Question Paper 2.indd 69

Dec.12 - M. P. 2 Embedded System Design Successive steps are linked in a chain manner and each steps is connected to the previous phase reverse connection provides an essential verification link backwards to ensure that the solution agrees with and follows from the specification. With the waterfall model the recognition of problems can be delayed until later states of development where the cost of repair is higher. Rapid Proto typing: The rapid prototyping model is extended to provide rapid implementation of high level portion of with the software and hardware. The approach allows developers to construct working portion of the hardware and software in incremental stage. Each stage consists of design code and unit test, integration test and delivery. The proto type is useful for both the designer and the customer. For the designer, it enables the early development of major prices of the intended functionality of system. PART - B 5. a. Write a brief note on a) Thread of execution b) Address space c) child process d) multiple thread e) operating system (05 Marks) Ans: a) Thread of execution: The sequential execution of a set of instructions through a task on process is an embedded application is called a thread of execution or thread of control. b) Address space: The set of address delimiting that code and data memory, proprietary to each process is called its address space. That address space will typically not be shared with any other purposes. c) Child Process: A process may execute sponen child processes. When doing so, that parent process may choose to give a subit of its resources to each of the children. The children are separate processes, and each has its own data p address space, data station and stack. The code portion of the address space is shared. d) Multiple threads: A process may execute multiple threads. When doing so, that parent process shares most of its resources with each of the threads. They are not separate processes but separate threads of execution within the same process. Each thread will have its own stack and status information. e) Operation system: An embedded operating system provides an environment with in which the firmware pieces, the tasks that makes up an embedded application are executed. An operating system provides following function schedule task execution dispatch a task to run ensure communication and synchronization among tasks. 5. b. What is reentrant-code? How it is useful? (05 Marks) Ans: Child process and consequently then thread share the same firm ware memory area. As a result, two different thread can be executing the same function at the same time. Functions using only local variables an inherently reentrant is they can be simultaneously called and executed in two or more contexts. Local variables are copied to the stack, and each invocation will get new copies. On the other hand functions that use global variables local to the process, variables passed by references, or shared resources are not reentrant. One must be particularly careful to ensure that all accesses to any common resources are co-ordinated. While designing one must be very careful to ensure that all accesser to any common resources are coordinated when designing application, one must make certain that one thread cannot corrupt the values of the variables in a second. It is good practice to make certain that all functions are reentrant. 4-Model Question Paper 2.indd 70

Embedded System Design M. P. 2 Dec. 12-5. c. Draw and explain TCB? (08 Marks) Ans: In a tasked band approach each process is represented in the operating system by a date structure called task control block. The TCB contain all the important information about the task and the block diagram of TCB is as shown below. Pointer State Process ID Program Counter Register contents Memory limits Open files etc A typical TCB contains following information Pointer Process ID and state Program counter CPU Register Scheduling information Memory management information Scheduling information I/O states information 6. a. Write a C program to implement the design given in data/control flow diagram shown below. (12 Marks) Get 1.0 Increment 2.0 Remote Input Data Buffer Display 2.0 Remote Output Ans: // Building a simple OS kernel-step 1 #include <stdlo.h> // Declare the prototypes for the tasks 4-Model Question Paper 2.indd 71

Dec.12 - M. P. 2 Embedded System Design Void get (void* anumber); void increment (void*anumber); void display (void*anumber); void main (void) { Int 1 = 0; Int data; Int*aPtr = &data; //Input task //computation task // output task //queue index // declare a shared data //point to it void (*queue [3])(void); //declare queue as an array of pointer to // functions taking an arg of type void* queue [0] = get; //enter the tasks into the queue queue [1] = increment; queue[2] = display; while(1) { queue [1] ((void*) aptr); // dispatch each task in turn 1 = (1 + 1) % 3; } return; } void get (void* anumber) // perform Input operation { printf ("Enter a number 0..9"); *(int*) anumber = getchar ( ); get char ( ); // discard cr *(int*) anumber = '0'; // convert to decimal from ascii return; } void increment (void* anumber) //perform computation { int*aptr = (int*) a Number; (*aptr)++; return; } void display (void* anumber) //perform output operation { printf("the result is: %d\n", *(int*) anumber); 4-Model Question Paper 2.indd 72

Embedded System Design M. P. 2 Dec. 12 - return; } 6. b. Write a brief note on context switch. (08 Marks) Ans: If the design supports the ability to preempt or block a scanning task on thread and initiate another, then next to a switch to a new content. A context switch after involves Saving the entering content Switching to the new one Restoring the old one These three steps can consume a significant amount of time. When operating under real time constraints, the time required to affect the switch can be critical to the success or failure of the application. The information that must be saved from an existing content may be as simple as the program counter and stack pointer for the original content. The typical minimum includes The state of the CPU registers including the CPU The value of local variables States information Saving of such information can be accomplished in several different ways. Duplicate Hardware content Task Control Block Stack 7. a. What is Amdahl's law. (04 Marks) Ans: Ttotal T T total component = + Timproved ( Ttotal Tcomponent ) n T = Systemmetric prior to improvement total T improved = System metric after improvement T component = Contribution of the components to be improved to the system metric. n = The amount of improvement 7. b. What is instruction counting. (08 Marks) Ans: Instruction counting requires that the code actually be written. At the end of the day, this is the best method to determine the time loading due to the code execution time. For periodic system: the total task execution time is computed and then devided by time for the individual module. This becomes the time loading for the task. For sporadic systems, the minimum task execution rates are used and the percentages are combined over all the tasks. This gives a total time loading. For example if we have Total time loading is T Ti is cycle time for i th task Ai is execution time for i th task For n tasks n Ai T = Ti i= 1 4-Model Question Paper 2.indd 73

Dec.12 - M. P. 2 Embedded System Design 7. c. Write a brief note on co-routine and interrupt call. (08 Marks) Ans: Co- routine: A co-routine is a special kind of procedure call in which then is a mutual call exchanged between co-operating procedures- that is two procedures sharing time. The mechanics are the same as the simple procedure call, and so is the time budget. The major differences is that a conventional procedure execute until the end unless it leaves under extra ordinary circumstances. Co-routine unit and return through out the body of the procedure. Usually, this is executed under the direction of a third process or procedure. Graphically, the process appears as shown below. Control Procedure Procedure 0 Procedure 1 The control procedure starts the process. Each context switch is determined by array of the following: Control procedure External event - a timing signal Internal event - a data value The process continues until both procedure are complete with each switch, the appropriate information from the current context must be saved. Interrupt call: An interrupt is a special kind of procedure call. Then initiator is some asynchronous initial or external event. Interrupt handler Foreground task ISR As illustrated in fig. above, normal execution proceeds in the foreground task. When the interrupt occurs control is first transferred to the interrupt handler and then the appropriate ISR. Most processors complete the current instruction before initiating the content switch. Thus since it is not generally known which instruction is bring executed when the interrupt occurs, the longest is selected. Such a choice gives an upper bound. 8. a. If a system is implemented as MI = 15 mega bytes, M R = 100 kilobytes, M S = 150 kilobytes, Pi = 55%, P R = 33% and P S = 10% calculate memory loading. (05 Marks) Ans: Memory loading is given by 4-Model Question Paper 2.indd 74

Embedded System Design M. P. 2 Dec. 12 - MT = M i.pi + MR PR + M S.PS 15 0.1 0.15 MT = 0.55 + 0.33 + 0.1 15.25 15.25 15.25 M = 54% T 8. b. What is SMART? (05 Marks) Ans: SMART stands for smart memory allocation for Real time. It is a scheme that may be used to address the precemption problem, when each task is given its own portion of cache. Cache can be decompound into restricted portion and a common portion. A critical task is assigned a restricted portion on start-up. All cache accesses are restricted to through partitions and to the common area. The task retains execlusive rights to the restricted area until it terminates or is aborted. Such restriction includes preemption by other tasks. The method for assigning partitions remains an open problem still. 8. c. What is hardware accelerator? (05 Marks) Ans: Hardware accelerator is a technique that is used to gain significant performance increase with respect to a software implementation is to move some of the functionality to hardware. Such a collection of components is called hardware accelerator. The accelerater is often attached to the cpu bus. The accelerater does not generally execute instruction. Its interface appears as I/O. It is designed to perform a specific function and is generally implemented as an ASK, FPGA or CPLD. Hardware accelerators are used when there are functions whose operations do not map all into the cpu. Few examples are as below Bit and bit field operations Differing precession of arithmetic calculations Very high speed arithmetic 8. d. What are the ruler Big O Arithmetic hand in. (05 Marks) Ans: Big O arithmetic is hand on following rules order common function from smallest to longest 1, log (N), N, N log(n), N 2, N 3,...2 N, 3 N Ignore constant multipliers 300 N + SN 4 + 6.2 N = 0 (N + N 4 + 2 N ) Ignore every thing except the higher order times N + N 4 + 2 N = 0(2 N ) 4-Model Question Paper 2.indd 75