Circuit Pack Descriptions

NT7E65DJ 323-1111-102 SONET Transmission Products S/DMS TransportNode OC-3/OC-12 NE TBM Circuit Pack Descriptions Standard Rel 14 February 2001 What s inside... Circuit pack descriptions

Copyright 1992 2001 Nortel Networks, All Rights Reserved The information contained herein is the property of Nortel Networks and is strictly confidential. Except as expressly authorized in writing by Nortel Networks, the holder shall keep all information contained herein confidential, shall disclose it only to its employees with a need to know, and shall protect it, in whole or in part, from disclosure and dissemination to third parties with the same degree of care it uses to protect its own confidential information, but with no less than reasonable care. Except as expressly authorized in writing by Nortel Networks, the holder is granted no rights to use the information contained herein. Nortel Networks and S/DMS TransportNode are trademarks of Nortel Networks. VT100 is a trademark of Digital Equipment Corporation. UNIX is a trademark of X/Open Company Ltd. Printed in Canada

iii Contents What s inside... About this document vii Circuit pack descriptions 1-1 DS1 input circuit pack (NT4K32) 1-2 Functional description 1-2 Physical appearance of the DS1 input circuit pack 1-2 DS1 output circuit pack (NT4K33) 1-3 Functional description 1-4 Physical appearance of the DS1 output circuit pack 1-4 Equipping rules for the DS1 input and output circuit packs 1-5 DS1 VT mapper circuit pack (NT7E04) 1-6 From DS1 interface to OC-12 or OC-3 optical interface 1-7 From OC-12 or OC-3 optical interface to DS1 interface 1-7 Control bus interface 1-7 Point-of-use power supply (PUPS) 1-7 Alarm LED definitions 1-7 Provisioning options for the DS1 VT synchronous mapper 1-8 Physical appearance of the DS1 VT synchronous mapper 1-9 Equipping rules for the OC-12 or OC-3 shelf 1-10 Associated I/O circuit packs 1-11 BNC I/O circuit pack (NT4K30) 1-11 Functional description 1-11 Physical appearance of the BNC I/O circuit pack 1-13 Equipping rules 1-13 DS3 STS mapper circuit pack (NT7E08) 1-17 From BNC I/O circuit packs to OC-12 or OC-3 optical interface 1-17 From OC-12 or OC-3 optical interface to BNC I/O circuit pack 1-17 Unframed DS3 clear channel 1-17 Control bus interface (CBus) 1-18 Point-of-use power supply (PUPS) 1-18 Alarm LED definitions 1-18 Physical appearance of the DS3 STS mapper 1-20 Equipping rules for the OC-12 or OC-3 shelf 1-21 DS3 STS mapper circuit pack (NT7E08BA) 1-22 STS-1 electrical interface circuit pack (NT7E09) 1-22 From the BNC I/O circuit packs to the OC-12 or OC-3 optical interface 1-22 From the OC-12 or OC-3 optical interface to the BNC I/O circuit packs 1-22 Control bus interface 1-23 Circuit Pack Descriptions 323-1111-102 Rel 14 Standard Feb 2001

iv Contents Point-of-use power supply (PUPS) 1-23 Alarm LED definitions 1-23 Equipping rules for the OC-12 or OC-3 shelf 1-24 Physical appearance of the STS-1 interface 1-26 Protection switcher circuit pack (NT4K60) 1-27 Functional description 1-27 Bus connections 1-29 Physical appearance of the protection switcher circuit pack 1-30 Equipping rules for the OC-12 or OC-3 shelf 1-31 External synchronization interface carrier (NT7E19) 1-31 Functional description 1-31 External synchronization interface (ESI) unit (NT7E27) 1-33 Functional description 1-34 Physical appearance of the ESI equipment 1-36 Equipping rules for the OC-3 or OC-12 shelf 1-37 Maintenance interface controller circuit pack (NT4K53) 1-37 Functional description 1-38 Bus connections 1-43 Equipping rules for the OC-12 or OC-3 shelf 1-43 Physical appearance of the maintenance interface circuit pack 1-44 OC-12 optical interface circuit pack (NT7E02) 1-45 OC-12 interfaces with changeable optical connectors 1-47 Terminal, linear ADM, and ring ADM applications 1-50 Regenerator application 1-50 Control bus interface (CBus) 1-51 Point-of-use power supply (PUPS) 1-52 Equipping rules for the OC-12 shelf 1-52 Alarm LED definitions 1-53 Ring loopback circuit pack (NT7E35) 1-55 Control bus interface (CBus) 1-55 Point-of-use power supply (PUPS) 1-57 Equipping rules for the OC-12 shelf 1-57 Overhead bridge circuit pack (NT7E36) 1-59 Equipping rules for the OC-12 shelf 1-59 OC-3 optical interface circuit pack (NT7E01) 1-61 NT7E01GA and NT7E01GB optical interface circuit packs 1-61 Transmit direction 1-61 Receive direction 1-62 Control bus interface (CBus) 1-62 Point-of-use power supply (PUPS) 1-62 Equipping rules for the OC-3 or OC-12 shelf 1-62 Alarm LED definitions 1-63 STS-12 electrical interface (NT7E33) 1-66 Control Bus (CBus) interface 1-67 Point-of-use power supply (PUPS) 1-67 Equipping rules for the OC-12 shelf 1-67 Alarm LED definitions 1-67 OC-12 VTM circuit pack (NT7E05) 1-70 VTM ring ADM application 1-73 Bus interface 1-74 Transport Control Subsystem 1-74 S/DMS TransportNode OC-3/OC-12 NE TBM Vol 1 323-1111-102 Rel 14 Standard Feb 2001

Contents v Point-of-use power supply (PUPS) 1-74 Equipping rules for the OC-12 shelf 1-74 Alarm LED definitions 1-74 Operations controller (NT7E24) 1-76 Solid state OPC (NT7E24EA or NT7E24FA) 1-76 Centralized data management 1-76 Software management 1-76 OPC user interface 1-76 Point-of-use power supply (PUPS) 1-76 Alarm LED definitions 1-77 Interfaces supported by the OPC 1-82 Equipping rules for the OC-12 or OC-3 shelf 1-83 Processor circuit pack (NT4K52) 1-84 Functional description 1-85 Bus connections 1-87 Point-of-use power supply (PUPS) 1-87 Physical appearance of the processor circuit pack 1-88 Equipping rules for the OC-12 or OC-3 shelf 1-89 Power termination circuit pack (NT4K58) 1-89 Equipping rules for the OC-12 or OC-3 shelf 1-89 Side interconnect left circuit pack (NT4K50BA) 1-90 Circuit Pack Descriptions 323-1111-102 Rel 14 Standard Feb 2001

vi Contents S/DMS TransportNode OC-3/OC-12 NE TBM Vol 1 323-1111-102 Rel 14 Standard Feb 2001

About this document vii This document provides a brief description of each circuit pack, a functional block diagram, and an illustration of the faceplate. The document also provides equipping rules. Audience This document is for the following members of the operating company: planners provisioners network administrators transmission standards engineers maintenance personnel References in this document This document refers to the following documents: System Description, 323-1111-100 Software Description, 323-1111-101 System Applications Description, 323-1111-150 Ordering Information, 323-1111-151 User Interfaces Description, 323-1111-301 Circuit Pack Descriptions 323-1111-102 Rel 14 Standard Feb 2001

viii About this document S/DMS TransportNode OC-3/OC-12 NE TBM Vol 1 323-1111-102 Rel 14 Standard Feb 2001

1-1 Circuit pack descriptions 1- This chapter describes all OC-12 and OC-3 network element (NE) circuit packs. See Table 1-1 for a list of all circuit packs described in this chapter. Table 1-1 OC-3/OC-12 network element circuit packs and modules PEC Circuit pack or module Page NT4K30 BNC I/O circuit pack (NT4K30) 1-11 NT4K32 DS1 input circuit pack (NT4K32) 1-2 NT4K33 DS1 output circuit pack (NT4K33) 1-3 NT4K50 Side interconnect left circuit pack (NT4K50BA) 1-90 NT4K52 Processor circuit pack (NT4K52) 1-84 NT4K53 Maintenance interface controller circuit pack (NT4K53) 1-37 NT4K58 Power termination circuit pack (NT4K58) 1-89 NT4K60 Protection switcher circuit pack (NT4K60) 1-27 NT7E01 OC-3 optical interface circuit pack (NT7E01) 1-61 NT7E02 OC-12 optical interface circuit pack (NT7E02) 1-45 NT7E04 DS1 VT mapper circuit pack (NT7E04) 1-6 NT7E05 OC-12 VTM circuit pack (NT7E05) 1-70 NT7E08 DS3 STS mapper circuit pack (NT7E08) 1-17 NT7E09 STS-1 electrical interface circuit pack (NT7E09) 1-22 NT7E19 External synchronization interface carrier (NT7E19) 1-31 NT7E24 Operations controller (NT7E24) 1-76 continued Circuit Pack Descriptions 323-1111-102 Rel 14 Standard Feb 2001

1-2 Circuit pack descriptions Table 1-1 (continued) OC-3/OC-12 network element circuit packs and modules PEC Circuit pack or module Page NT7E27 External synchronization interface (ESI) unit (NT7E27) 1-33 NT7E33 STS-12 electrical interface (NT7E33) 1-66 NT7E35 Ring loopback circuit pack (NT7E35) 1-59 NT7E36 Overhead bridge circuit pack (NT7E36) 1-59 end The following information is provided for each circuit pack: circuit pack function supported by a block diagram faceplate layout illustration with LED definitions equipping rules (if applicable) DS1 input circuit pack (NT4K32) Install the DS1 input circuit pack in the upper level of the OC-12 or OC-3 shelf. Each working DS1 virtual tributary (VT) synchronous mapper in the lower level of the shelf must have one DS1 input circuit pack and one DS1 output circuit pack in the upper level. Each DS1 input circuit pack handles 14 DS1 channels of input (all DS1 input to a single DS1 VT synchronous mapper). Input DS1 signals enter the S/DMS TransportNode, travel to the DS1 input circuit pack, and onto the associated DS1 VT synchronous mapper. Functional description Figure 1-1 shows a block diagram of the DS1 input circuit pack. The circuit pack filters electromagnetic interference (EMI) from the incoming DS1 signals. The signals pass through a splitter, and travel to the associated working DS1 VT synchronous mapper, then towards the DS1 protection bus in the shelf backplane. In normal operation, the signals do not reach the DS1 protection bus because an on-card relay is open. When a protection-switching request occurs for the associated working DS1 VT synchronous mapper, the relay closes, and the DS1 signals travel to the protection bus. (The DS1 protection bus routes the DS1 signals toward the protection DS1 VT synchronous mapper.) Physical appearance of the DS1 input circuit pack The DS1 input circuit pack is 5.7 cm (2.25 in.) high by 25.8 cm (10.15 in.) deep by 2.0 cm (0.8 in.) wide. Figure 1-2 shows the front view of the DS1 input circuit pack. This circuit pack has a D connector at the front. S/DMS TransportNode OC-3/OC-12 NE TBM Vol 1 323-1111-102 Rel 14 Standard Feb 2001

Circuit pack descriptions 1-3 Figure 1-1 Block diagram of the DS1 input circuit pack DSX-1 twisted pair line EMI filter 6 db splitter To Working DS1/VT synchronous mapper To Protection DS1/VT synchronous mapper FW-1923 Relay contact is normally open. Figure 1-2 Front view of the DS1 input circuit pack FW-1927 44-pin D connector Fastening screw DS1 output circuit pack (NT4K33) Install the DS1 output circuit pack in the upper level of the TBM shelf. Each working DS1 VT synchronous mapper in the lower level of the shelf must have one DS1 output circuit pack and one DS1 input circuit pack in the upper level. Each DS1 output circuit pack handles 14 DS1 channels of output (all DS1 output from a single DS1 VT synchronous mapper circuit pack). Output DS1 signals travel from the DS1 VT synchronous mapper to the associated DS1 output circuit pack, then out of the S/DMS TransportNode. Circuit Pack Descriptions 323-1111-102 Rel 14 Standard Feb 2001

1-4 Circuit pack descriptions Functional description Figure 1-3 shows a block diagram of the DS1 output circuit pack. The circuit pack receives DS1s from the associated working DS1 VT synchronous mapper (under normal circumstances) or the DS1 protection bus in the shelf backplane. When a protection-switching request occurs for the associated working mapper, the on-card relays break the connection to the associated working mapper and close the connection to the protection bus. The DS1 output circuit pack performs EMI filtering on the outgoing DS1s. Figure 1-3 Block diagram of the DS1 output circuit pack Relay contact is normally closed FW-1931 From Working DS1/VT synchronous mapper From Protection DS1/VT synchronous mapper EMI filter DSX-1 twisted pair line Relay contact is normally open. Physical appearance of the DS1 output circuit pack The DS1 output circuit pack is 5.7 cm (2.25 in.) high by 25.8 cm (10.15 in.) deep by 2.0 cm (0.8 in.) wide. Figure 1-4 shows the front view of the DS1 output circuit pack. This circuit pack has a D connector at the front. Figure 1-4 Front view of the DS1 output circuit pack FW-1927 44-pin D connector Fastening screw S/DMS TransportNode OC-3/OC-12 NE TBM Vol 1 323-1111-102 Rel 14 Standard Feb 2001

Circuit pack descriptions 1-5 Equipping rules for the DS1 input and output circuit packs Figure 1-5 shows the slots in which DS1 input and DS1 output circuit packs can be installed in an OC-12 or OC-3 shelf. Each upper-level slot that accommodates DS1 input and output circuit packs is associated with a specific lower-level slot that accommodates a DS1 VT synchronous mapper. Note: Cover unequipped in/out circuit pack positions with blank I/O faceplates (NT4K5830). Fill unequipped shelf slot positions with filler circuit packs (NT7E39). Figure 1-5 DS1 input and output circuit packs installed in the OC-12 or OC-3 shelf FW-1926 (Vol 1) Associated Mapper position odd even odd even odd even odd even odd OC-12 or OC-3 ADM even odd even odd OC-3 30 32 34 36 38 40 42 44 46 48 50 52 54 55 DS1 In DS1 In DS1 Out DS1 Out DS1 In DS1 In DS1 Out DS1 Out DS1 In DS1 In DS1 Out DS1 Out DS1 In DS1 In DS1 Out DS1 Out DS1 In DS1 In DS1 Out DS1 Out DS1 In DS1 In DS1 Out DS1 Out 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 DS1/VT Mpr (NT7E04) DS1/VT Mpr (NT7E04) DS1/VT Mpr (NT7E04) DS1/VT Mpr (NT7E04) IN OUT IN OUT DS1/VT Mpr (NT7E04) DS1/VT Mpr (NT7E04) odd even odd even DS1/VT Mpr (NT7E04) DS1/VT Mpr (NT7E04) DS1/VT Mpr (NT7E04) DS1/VT Mpr (NT7E04) odd DS1/VT Mpr (NT7E04) DS1/VT Mpr (NT7E04) even odd even odd even even odd even odd even odd even odd even odd even odd even OC-12 OC-3 Note: An OC-12 can handle up to 168 DS1s (12 DS1/VT Mappers). An OC-3 Terminal can handle up to 84 DS1s (6 DS1/VT Mappers). An OC-3 ADM can handle up to 168 DS1s (12 DS1/VT Mappers). Circuit Pack Descriptions 323-1111-102 Rel 14 Standard Feb 2001

1-6 Circuit pack descriptions Table 1-2 shows the association of slots in the OC-12 or OC-3 shelf. Table 1-2 Association of slots in the OC-12 or OC-3 shelf DS1 protection group name DS1 VT synchronous mapper DS1 input circuit pack DS1 output circuit pack OC-12 and OC-3 ADM OC-3 Term G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 P 1 2 3 4 11 12 13 14 15 16 17 18 19 30 31 34 35 38 39 42 43 46 47 50 51 Not applicable 32 33 36 37 40 41 44 45 48 49 52 53 Not applicable X X X X X X X X X X X X X X X X X X X X DS1 VT mapper circuit pack (NT7E04) The DS1 VT mapper circuit pack provides interface circuitry between the DS1 input and output circuit packs, and the backplane STS bus (see Figure 1-6). The DS1 VT mapper circuit pack generates a half-full virtual tributary (VT) organized STS-1 signal from up to 14 DS1 signals. The DS1 signals are mapped as VT1.5 signals according to the floating DS1 asynchronous mapping provided by the SONET standard. Each circuit pack processes 14 DS1 transmit and receive signals independently. The STS-1 signals are transmitted and received by way of the backplane. The two half-full STS-1 signals from adjacent DS1 mappers (odd and even slots) are merged on the backplane interface of the OC-3/OC-12 circuit pack to form a full STS-1 signal on the optical path. You can perform loopbacks for link maintenance and fault detection purposes. Software controls the line build-out (LBO) range selection and can select for a range of 0 m to 200 m (0 feet to 655 feet). The following line codings are accepted: AMI, B8ZS, or AMIZCS. S/DMS TransportNode OC-3/OC-12 NE TBM Vol 1 323-1111-102 Rel 14 Standard Feb 2001

Circuit pack descriptions 1-7 From DS1 interface to OC-12 or OC-3 optical interface The DSI VT processor regenerates the 14 DS1 signals received from the DS1 input circuit pack, and performs DS1 clock recovery using digital phase lock loops. The system uses the recovered clock to time-regenerate each DS1 line data. Each DS1 is bit-stuffed into a SONET VT along with VT path overhead. The VTs are byte-interleaved into a VT group that is sent to a VT/STS processor where each VT group is byte-interleaved into an STS-1 format. The STS path overhead is then added. The half-full STS-1 signal travels to the OC-12 or OC-3 optical interface circuit pack where it merges with the half-full STS-1 signal from the adjacent DS1 mapper. From OC-12 or OC-3 optical interface to DS1 interface The STS-1 signal coming from the OC-12 or OC-3 optical interface circuit pack travels to the VT/STS processor. The VT/STS processor extracts the STS path overhead, and demultiplexes the STS-1 payload into VT groups. The VT groups then travel to the DS1 VT. The DS1 VT processor extracts The DS1 signals and terminates VT path overhead. A programmable LBO circuit then regenerates the DS1 signals. Control bus interface The control bus interface (CBus) circuit that communicates with the processor through the control bus provides control and status monitoring for the DS1 VT mapper circuit pack. The CBus interface circuit also controls the Unit Fail LED (red) and the Active LED (green) located on the faceplate of the circuit pack. Point-of-use power supply (PUPS) The DS1 VT mapper circuit pack is equipped with its own point-of-use power supply (PUPS) that converts the -48 V dc office supply to the specific regulated direct-current voltage levels required by the local circuitry. The PUPS are fused individually. Alarm LED definitions Table 1-3 lists the names of the DS1 VT mapper circuit pack LEDs, the possible cause for LED activation, and how the LEDs are controlled (hardware or software). Table 1-3 DS1 VT mapper circuit pack LEDs LED name Possible cause Controlled by Unit fail Alarm points circuit pack fail receive STS bus parity error Software Active Active unit Software Circuit Pack Descriptions 323-1111-102 Rel 14 Standard Feb 2001

1-8 Circuit pack descriptions Figure 1-6 Block diagram of the DS1 VT mapper circuit pack FW-1965 VT Overhead Insertion / Removal STS Overhead Insertion / Removal DS1 1-14 (To/From DS1 Input/Output cards) DS1/VT Processor VT/STS Processor STS-1 (To/From OC-3 or OC-12 Optical Interface) CBus -48 V dc PUPS +5 V dc -4.5 V dc CBus Interface Active Unit Fail Legend: CBus = Control Bus PUPS = Point-of-Use Power Supply VT = Virtual Tributary STS = Synchronous Transport Signal To/From Application Processor card Provisioning options for the DS1 VT synchronous mapper The DS1 VT synchronous mapper can accept DS1 signals with the following frame formats: superframe (SF) extended superframe (ESF) null The DS1 VT synchronous mapper can also accept SLC-96 DS1 signals as long as the DS1 facilities are provisioned with the following parameters: AMI line carding null framing format zeros alarm encoding asynchronous synchronization S/DMS TransportNode OC-3/OC-12 NE TBM Vol 1 323-1111-102 Rel 14 Standard Feb 2001

Circuit pack descriptions 1-9 Physical appearance of the DS1 VT synchronous mapper The DS1 VT synchronous mapper is 27.7 cm (10.9 in.) high by 25.7 cm (10.1 in.) deep. It is a single-width circuit pack, 2.0 cm (0.8 in.) wide. Figure 1-7 shows the front view of the DS1 VT synchronous mapper. Figure 1-7 DS1 VT mapper circuit pack faceplate layout FW-0127 DS1 VT Mapper Active Fail Active LED (Green) Indicates the unit is processing DS1s. The circuit pack should not be removed while this LED is lit. The LED is software controlled. Fail LED (Red) Indicates a circuit pack failure. The LED is software controlled. Circuit Pack Descriptions 323-1111-102 Rel 14 Standard Feb 2001

1-10 Circuit pack descriptions Equipping rules for the OC-12 or OC-3 shelf CAUTION Risk of traffic loss Deprovision unused DS3 ports before installing a DS1 VT mapper. If you do not deprovision unused DS3 ports, the DS1 traffic is not carried through the DS1 VT mapper even if the DS1 VT mapper is provisioned correctly. If you insert mappers into slots other than those specified in the equipping rules, or configure a DS1/DS3-mix system contrary to the prescribed configurations, you can cause hits on traffic, or incorrect provisioning of the system. If you equip a protection switcher circuit pack in slot 2, you cannot use slot 3 to provide DS1 service. Remove DS1 I/O circuit packs in slots 30 through 32 for any mix configuration. If you do not remove these circuit packs, protection traffic and the currently bridged DS3 or STS-1 traffic is affected. Do not insert DS1 input and output circuit packs into slots other than those specified in the equipping rules. CAUTION Risk of preventing software downloads Seat DS1 I/O circuit packs in place correctly with screws tightened. Improperly seated I/O circuit packs can prevent software downloads. In an OC-12 shelf and an OC-3 ADM shelf, install up to twelve working DS1 VT synchronous mappers in slots 1 (G1) to 4 (G4), and 11 (G5) to 18 (G12). In an OC-3 terminal shelf, install up to six working DS1 VT synchronous mappers in slots 13 (G7) to 18 (G12). Install a protection DS1 VT synchronous mapper only in slot 19. The protection arrangement is revertive 1:N, where N 12 for the OC-12, and N 6 for the OC-3. A pair of DS1 VT working mappers supplies the 28 VT1.5 signals (2 multiplied by 14 VT1.5 signals) required to fill the bandwidth of one STS-1. Install the working mappers in pairs of slots. In each pair of slots (for example, 17/18, 15/16, 13/14), the mapper in the odd-numbered slot serves the first set of 14 VT1.5 signals (1 to 14), and the even-numbered slot serves the second set of 14 VT1.5 signals (15 to 28). S/DMS TransportNode OC-3/OC-12 NE TBM Vol 1 323-1111-102 Rel 14 Standard Feb 2001

Circuit pack descriptions 1-11 In an OC-12 mixed system, DS1 VT mappers and DS3 STS mappers share the same slots. Thus the quantity of DS1 VT mappers to be installed depends on the quantity of DS3 STS mappers being installed. In an OC-3 mixed system, install DS1 VT mappers after DS3 STS mappers. Once you install DS3 STS mappers, deprovision unused DS3 ports before inserting a DS1 VT mapper. Associated I/O circuit packs Each DS1 VT synchronous mapper in the lower level of the shelf requires two circuit packs in associated slots in the upper level of the shelf. Table 1-2 shows the association of lower-level slots and upper-level slots in the TBM shelf. If a mapper in the lower level of the TBM shelf is a working unit, the associated circuit packs in the upper level must be a DS1 input circuit pack and a DS1 output circuit pack. BNC I/O circuit pack (NT4K30) Install the BNC I/O circuit pack (formerly referred to as the DS3 I/O or the DS3 BNC I/O circuit pack) in the upper level of the TBM shelf. Each BNC I/O circuit pack handles both directions of one DS3 or STS-1 line: one DS3 or STS-1 coming into the S/DMS TransportNode, and one DS3 or STS-1 going out. An input DS3 signal enters the S/DMS TransportNode, makes its way to the BNC I/O circuit pack, and onto the associated DS3 STS mapper. An input STS-1 signal enters the S/DMS TransportNode, makes its way to the BNC I/O circuit pack, and onto the associated STS-1 electrical interface circuit pack. An output DS3 or STS-1 signal travels from the DS3 STS mapper or STS-1 interface (respectively) to the associated BNC I/O circuit pack, and out of the S/DMS TransportNode. Functional description Each BNC I/O circuit pack has a splitter that sends the DS3 or STS-1 signal to both the associated working DS3 STS mapper circuit pack or STS-1 electrical interface circuit pack (respectively) and to the protection switcher circuit pack. (In normal operation, the signal sent to the protection switcher circuit pack terminates in that circuit pack.) Each BNC I/O circuit pack can receive DS3 signals either from the associated working DS3 STS mapper, or from the protection mapper (by way of the protection switcher circuit pack). Each BNC I/O circuit pack can also receive STS-1 signals from either the associated working STS-1 interface, or from the protection interface (by way of the protection switcher circuit pack). The BNC I/O circuit pack supports framed DS3 and STS-1 signals. Figure 1-8 illustrates these connections. Note: The BNC I/O circuit pack also supports unframed (clear channel) DS3 signals. Circuit Pack Descriptions 323-1111-102 Rel 14 Standard Feb 2001

1-12 Circuit pack descriptions In normal operation, an incoming DS3 or STS-1 signal passes through a splitter in the BNC I/O circuit pack. The signal then travels to both the associated DS3 STS mapper or STS-1 interface and the protection switcher circuit pack. The signal that goes to the protection switcher terminates on that circuit pack. The BNC I/O circuit pack receives a DS3 or STS-1 signal from the associated DS3 STS mapper or STS-1 interface. The BNC I/O circuit pack does not receive any signal from the protection switcher circuit pack. If a protection-switching request occurs for the working DS3 STS mapper or STS-1 interface, the relays on the protection switcher circuit pack close. Incoming DS3 or STS-1 traffic travels to the associated DS3 protection mapper or STS-1 protection interface. The protection mapper or interface is synchronized to the incoming DS3 or STS-1 signals. The relays on the three associated BNC I/O circuit packs interrupt the traffic that comes from the working mapper or the working interface. Then, the relays accept the traffic that comes from the protection mapper or the protection interface by way of the protection switcher circuit pack. Note: When a shelf is equipped with both DS3 mappers and STS-1 interfaces, install only one protection switcher circuit pack. The two services share the protection switcher circuit pack. Figure 1-8 Block diagram of the BNC I/O circuit pack FW-1918 (R8) DS3 or STS-1 from DS3 or STS-1 termination panel DS3 or STS-1 to DS3 or STS-1 termination panel To Working DS3 STS Mapper or STS-1 interface To Protection switcher From Working DS3 STS Mapper or STS-1 interface From Protection switcher Note: Heavy lines show signal flow in normal operation. Legend: = Open relay = Closed relay = Resistive termination S/DMS TransportNode OC-3/OC-12 NE TBM Vol 1 323-1111-102 Rel 14 Standard Feb 2001

Circuit pack descriptions 1-13 Physical appearance of the BNC I/O circuit pack The BNC I/O circuit pack is 5.7 cm (2.25 in.) high by 25.8 cm (10.15 in.) deep by 2.0 cm (0.8 in.) wide. Figure 1-9 shows the front view of the BNC I/O circuit pack. This circuit pack has two BNC-type connectors on the front. Figure 1-9 BNC I/O circuit pack FW-1919 In Out Fastening screw Equipping rules CAUTION Risk of preventing software downloads Seat BNC I/O circuit packs in place correctly with screws tightened. Improperly seated I/O circuit packs can prevent software downloads. Install I/O circuit packs individually or in sets of three. Each set of three circuit packs can handle all the input and output for a DS3 STS mapper circuit pack or an STS-1 electrical interface circuit pack (both directions of three DS3 or STS-1 signals). Equipping rules for the OC-12 shelf In the OC-12 shelf, install up to 12 BNC I/O circuit packs (the shelf can handle up to 12 DS3 or STS-1 signals). Install BNC I/O circuit packs in sets of three in slots 38, 39, and 40; in slots 42, 43, and 44; in slots 46, 47, and 48; and in slots 50, 51, and 52 (see Figure 1-10). Each set of three I/O circuit packs is associated with a DS3 STS mapper or STS-1 interface. Circuit Pack Descriptions 323-1111-102 Rel 14 Standard Feb 2001

1-14 Circuit pack descriptions Figure 1-10 BNC I/O circuit packs installed in the OC-12 shelf FW-3039 BNC I/O card (NT4K30) or Blank I/O faceplate (NT4K5830) (Note) 30 32 34 36 38 40 42 44 46 48 50 52 54 55 Blank I/O Blank I/O Blank I/O Blank I/O Blank I/O Blank I/O Blank I/O Blank I/O BNC I/O BNC I/O BNC I/O Blank I/O BNC I/O BNC I/O BNC I/O Blank I/O BNC I/O BNC I/O BNC I/O Blank I/O BNC I/O BNC I/O BNC I/O Blank I/O Pwr Pwr 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 SIL DS3 Mpr (Prot) (NT7E08) Protection Switcher (NT4K60) STS-1 I/F (Prot) (NT7E09) Operations Controller (OPC) (NT7E24) IN OUT OC-12 G1 IN OUT OC-12 G2 DS3 Mpr or STS-1 I/F DS3 Mpr or STS-1 I/F DS3 Mpr or STS-1 I/F DS3 Mpr or STS-1 I/F MIC (NT4K53) Processor Card (NT4K52) ESI ESI Optical Interfaces (NT7E02) Legend: DS3 Mpr = DS3 to Synchronous Transport Signal Mapper (NT7E08) ESI = External Synchronization Interface MIC = Maintenance Interface Card OC-12 = OC-12 Interface Pwr = Power Termination Card SIL = Side Interconnect Left Card STS-1 I/F = STS-1 Tributary Interface Card (NT7E09) ESI Carrier (NT7E19) equipped with 2 ESI units (NT7E27) Note: Unused In/Out card positions must be equipped with blank I/O faceplates (NT4K5830). S/DMS TransportNode OC-3/OC-12 NE TBM Vol 1 323-1111-102 Rel 14 Standard Feb 2001

Circuit pack descriptions 1-15 Table 1-4 shows the set of three I/O circuit packs as associated with a DS3 STS mapper or STS-1 interface. Table 1-4 Association of BNC I/O circuit packs with DS3 STS mappers or STS-1 interfaces in the OC-12 shelf DS3 or STS-1 protection group name DS3 STS mapper or STS-1 interface slots BNC I/O circuit pack slots Port 1 Port 2 Port 3 G1 11 38 39 40 G2 13 42 43 44 G3 15 46 47 48 G4 17 50 51 52 Equipping rules for the OC-3 shelf In the OC-3 terminal shelf, install up to three BNC I/O circuit packs (the OC-3 signal can handle up to three DS3 or STS-1 signals). In the OC-3 add-drop multiplexer (ADM) shelf, install up to six BNC I/O circuit packs (the ADM shelf can handle up to three DS3 or STS-1 signals from each direction because no STS-1 signals are passed through). Install the circuit packs in sets of three in slots 38, 39, 40, and 42, 43, 44 (see Figure 1-11). Each set of three BNC I/O circuit packs is associated with a DS3 STS mapper or STS-1 interface (see Table 1-5 and Figure 1-11). Table 1-5 Association of BNC I/O circuit packs with DS3 STS mappers or STS-1 interfaces in the OC-3 shelf DS3 or STS-1 protection group name DS3 STS mapper or STS-1 interface slots BNC I/O circuit pack slots OC-3 shelf Port 1 Port 2 Port 3 G1 11 38 39 40 X G2 13 42 43 44 X Circuit Pack Descriptions 323-1111-102 Rel 14 Standard Feb 2001

1-16 Circuit pack descriptions Figure 1-11 BNC I/O circuit packs installed in the OC-3 shelf (terminal application) FW-3040 BNC I/O card (NT4K30) 30 32 34 36 38 40 42 44 46 48 50 52 54 55 Blank I/O Blank I/O Blank I/O Blank I/O Blank I/O Blank I/O Blank I/O Blank I/O BNC I/O BNC I/O BNC I/O Blank I/O Blank I/O Blank I/O Blank I/O Blank I/O Blank I/O Blank I/O Blank I/O Blank I/O Blank I/O Blank I/O Blank I/O Blank I/O Pwr Pwr 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 SIL DS3 Mpr (Prot) (NT7E08) Protection Switcher (NT4K60) STS-1 I/F (Prot) (NT7E09) Operations Controller (OPC) (NT7E24) IN OUT OC-3 G1 IN OUT OC-3 G2 DS3 Mpr or STS-1 I/F MIC (NT4K53) Processor Card (NT4K52) ESI ESI or Optical Interfaces (NT7E01) Legend: DS3 Mpr = DS3 to Synchronous Transport Signal Mapper (NT7E08) ESI = External Synchronization Interface MIC = Maintenace Interface Card OC-3 = OC-3 Interface Pwr = Power Termination Card SIL = Side Interconnect Left Card STS-1 I/F = STS-1 Tributary Interface Card (NT7E09) ESI Carrier (NT7E19) equipped with 2 ESI units (NT7E27) Note: Unused In/Out card positions must be equipped with blank I/O faceplates (NT4K5830). S/DMS TransportNode OC-3/OC-12 NE TBM Vol 1 323-1111-102 Rel 14 Standard Feb 2001

Circuit pack descriptions 1-17 DS3 STS mapper circuit pack (NT7E08) The DS3 STS mapper circuit pack provides interface circuitry between BNC I/O circuit packs and the backplane STS bus (see Figure 1-12). The DS3 STS mapper circuit pack generates an STS-1 signal (non-vt organized) from a DS3 signal (framed or unframed). Each circuit pack processes up to three DS3 transmit and receive signals independently. STS-1 signals are transmitted and received by way of the backplane STS buses. Loopbacks can be performed for link maintenance and fault detection purposes. The line build-out (LBO) range selection is under software control and can be selected for long or short range (the length depends on the type of cable used). From BNC I/O circuit packs to OC-12 or OC-3 optical interface Three BNC I/O circuit packs process three received DS3 signals, performing line equalization, clock recovery, and data regeneration. Regenerated DS3 signals travel to the DS3/STS processor which performs DS3 performance monitoring. Then, the DS3/STS processor bit stuffs each DS3 into a SONET STS-1 format and adds the STS path overhead. The three STS-1 signals coming out of the DS3 STS mapper circuit pack then travel to the OC-12 or OC-3 optical interface circuit pack. From OC-12 or OC-3 optical interface to BNC I/O circuit pack Three BNC I/O circuit packs process three STS-1 signals received from the OC-12 or OC-3 optical interface circuit pack. The circuit packs retime the STS-1 signals, extract the DS3 signal from each STS-1, then terminate the STS path overhead. The outgoing DS3 clock rate depends on the average (after pointer smoothing) DS3 data rate contained in the STS-1 SPE. The circuit packs frame outgoing DS3 signals, and monitor the DS3 parity prior to being B3ZS-encoded. DS3 signals then travel through a line driver circuit. A programmable LBO circuit generates the line signal. Unframed DS3 clear channel The DS3 STS mapper circuit pack has the built-in capability to carry unframed DS3 clear channel signals. The circuit pack processes the unframed signal in the same way it processes a standard DS3, except that it does not insert an alarm indication signal (AIS) upon detection of an unframed DS3 signal. Processor software does not process status messages provided by the mapper (LOF, parity error). The DS3 STS mapper circuit pack provides path performance monitoring counts. The counts are invalid but are displayed by the processor in the DS3 Facility screens. The circuit pack does not detect an unframed all-ones (111...), thus no AIS is inserted under this condition. Circuit Pack Descriptions 323-1111-102 Rel 14 Standard Feb 2001

1-18 Circuit pack descriptions Control bus interface (CBus) The control bus interface (CBus) circuit that communicates with the Proc circuit pack through the control bus provides control and status monitoring for the DS3 STS mapper circuit pack. The CBus interface circuit also controls the Unit Fail LED (red), the Active LED (green), and the three DS3 LOS (loss of signal) LEDs (yellow) located on the faceplate of the circuit pack. Point-of-use power supply (PUPS) The DS3 STS mapper circuit pack is equipped with its own PUPS that converts the -48 V dc office supply to the specific regulated direct-current voltage levels required by the local circuitry. Alarm LED definitions Table 1-6 lists the names of the DS3 STS mapper circuit pack LEDs, the possible cause for LED activation, and how the LEDS are controlled (hardware or software). Table 1-6 DS3 STS mapper circuit pack LEDs LED name Possible cause Controlled by Unit Fail Alarm points component fail receive STS bus parity error Software Active Active unit Software LOS1 DS3 No. 1 loss of signal Hardware LOS2 DS3 No. 2 loss of signal Hardware LOS3 DS3 No. 3 loss of signal Hardware On a DS3/STS-1 mix shelf, the DS3 STS mapper and STS-1 interface protection circuit packs share the same protection switcher. The protection switcher is bridged to only one of the protection circuit packs at a time. This bridge alternates every 60 minutes. The LOS LEDs on the protection circuit pack are disabled whenever the circuit pack is not bridged. When bridged, the LOS LEDs mirror the LOS LEDs on the working circuit pack. As a result, when the alternating bridge feature is activated and if the unused channels are not put out of service, the LOS LEDs on the protection circuit packs change state every 60 minutes. S/DMS TransportNode OC-3/OC-12 NE TBM Vol 1 323-1111-102 Rel 14 Standard Feb 2001

Circuit pack descriptions 1-19 Figure 1-12 Block diagram of the DS3 STS mapper circuit pack Path Overhead insertion/removal FW-1970 (TBM) DS3 1-3 (To/from DS3 BNC I/O cards) Data Regenerator Line Driver DS3/ STS Processor 3 STS-1s (To/from OC-3 or OC-12 optical interfaces) CBus Unit Fail Active LOS 3 LOS 2 LOS 1 CBus Interface To/from Processor card Legend: CBus = Control Bus PUPS = Point-of-Use Power Supply STS = Synchronous Transport Signal -48 V dc PUPS +5 V dc -4.5 V dc +12 V dc -12 V dc Circuit Pack Descriptions 323-1111-102 Rel 14 Standard Feb 2001

1-20 Circuit pack descriptions Physical appearance of the DS3 STS mapper The DS3 STS mapper is 27.7 cm (10.9 in.) high by 26.7 cm (10.1 in.) deep. It is a single-width circuit pack, 2.0 cm (0.8 in.) wide. Figure 1-13 shows the front view of a DS3 STS mapper. Figure 1-13 Front view of a DS3 STS mapper FW-0129.1 LOS 1 LOS 2 LOS 3 Active Fail LOS LEDs (yellow) Indicates a failure or a loss of an incoming DS3 signal on ports 1, 2, or 3. The LEDs are hardware or software controlled. (Note: If both optical cards are removed, LOS LEDs may light on the Protection Mapper.) Active LED (green) Indicates that the unit is processing DS3s. The Mapper should not be removed while this LED is lit. The LED is software controlled. Fail LED (red) Indicates a circuit pack failure or the detection of a backplane parity error. The LED is software controlled. S/DMS TransportNode OC-3/OC-12 NE TBM Vol 1 323-1111-102 Rel 14 Standard Feb 2001

Circuit pack descriptions 1-21 Equipping rules for the OC-12 or OC-3 shelf CAUTION Risk of traffic loss Deprovision unused DS3 ports before installing a DS1 VT mapper. If you do not deprovision unused DS3 ports, the DS1 traffic is not carried through the DS1 VT mapper even if the DS1 VT mapper is provisioned correctly. If you insert mappers into slots other than those specified in the equipping rules, or configure a DS1/DS3-mix system contrary to the prescribed configurations, you can cause hits on traffic, or incorrect provisioning of the system. If you equip a protection switcher circuit pack in slot 2, you cannot use slot 3 to provide DS1 service. Remove DS1 I/O circuit packs in slots 30 through 32 for any mix configuration. If you do not remove these circuit packs, protection traffic and the currently bridged DS3 or STS-1 traffic is affected. Do not insert DS1 input and output circuit packs into slots other than those specified in the equipping rules. CAUTION Risk of preventing software downloads Seat DS1 I/O circuit packs in place correctly with screws tightened. Improperly seated I/O circuit packs can prevent software downloads. In an OC-12 shelf, install up to 4 working DS3 STS mappers in slots 11 (G1), 13 (G2), 15 (G3), and 17 (G4). In an OC-3 terminal shelf, install only one working DS3 STS mapper (slot 11, G1). In an OC-3 ADM shelf, install up to two working DS3 STS mappers (slots 11, G1 and 13, G2). Install one protection DS3 STS mapper in slot 1 of both the OC-12 and OC-3 shelf. Install a protection switcher circuit pack in slot 2. The protection arrangement is revertive 1:N where N 4 for the OC-12, N 2 for the OC-3 ADM, and N=1 for the OC-3. Do not install a working DS3 STS mapper in an even-numbered slot. Circuit Pack Descriptions 323-1111-102 Rel 14 Standard Feb 2001

1-22 Circuit pack descriptions You can mix DS3 tributaries with DS1, STS-1, and OC-3 tributaries on the same shelf. When mixing DS3 and STS-1 services, equip slots 11, 13, 15, and 17 with either DS3 mapper or STS-1 interface circuit packs (all combinations are supported). When a shelf is equipped with both DS3 mappers and STS-1 interface circuit packs, the circuit packs share the protection switcher circuit pack (in slot 2). Note: Install OC-3 tributaries only in an OC-12 shelf. In an OC-12 mixed system, the DS1 VT mappers and DS3 STS mappers share the same slots. Thus the quantity of DS1 VT mappers to be installed depends on the quantity of DS3 STS mappers being installed. In an OC-3 mixed system, install the DS3 STS mapper before the DS1 VT mappers. Once you install the DS3 STS mappers, deprovision the unused DS3 ports before inserting a DS1 VT mapper. DS3 STS mapper circuit pack (NT7E08BA) Combined with OC-12 Release 14 software, the NT7E08BA circuit pack provides C-bit transparency, providing the ability to evolve to data oriented transmissions and allow C-bit based performance monitoring. STS-1 electrical interface circuit pack (NT7E09) The STS-1 electrical interface circuit pack provides interface circuitry between the BNC I/O circuit packs and the OC-3 or OC-12 optical interface circuit packs (Figure 1-14). Each STS-1 electrical interface circuit pack processes up to three STS-1 transmit and receive signals independently. The STS-1 signals are transmitted and received by way of the backplane STS buses. You can perform loopbacks for link maintenance and fault detection purposes. Software controls the line build-out (LBO) range selection, and can select for long or short range (the length depends on the type of cable used). From the BNC I/O circuit packs to the OC-12 or OC-3 optical interface Three BNC I/O circuit packs process three received STS-1 signals. The circuit packs perform line equalization, clock recovery, and data regeneration. Regenerated STS-1 signals then travel to the STS-1 processor. The STS-1 processor performs B3ZS decoding, STS-1 framing, and performance monitoring. The STS-1 processor then bulk maps each STS-1, and adds the STS path overhead. Three STS-1 signals coming out of the STS-1 interface circuit pack then travel to the OC-3 or OC-12 optical interface circuit pack. From the OC-12 or OC-3 optical interface to the BNC I/O circuit packs Three BNC I/O circuit packs process three STS-1 signals received from the OC-3 or OC-12 optical interface circuit pack. The circuit packs retime these STS-1 signals, and remove the STS path overhead. Then the circuit packs S/DMS TransportNode OC-3/OC-12 NE TBM Vol 1 323-1111-102 Rel 14 Standard Feb 2001

Circuit pack descriptions 1-23 frame and scramble outgoing STS-1 signals are framed, and monitor the signal parity prior to being B3ZS encoded. STS-1 signals then travel through a line-driver circuit, and a programmable LBO circuit generates the line signal. Control bus interface The control bus interface (CBus) circuit that communicates with the processor circuit pack through the control bus provides control and status monitoring for the STS-1 interface circuit pack. The CBus interface circuit also controls the Fail LED (red) located on the faceplate of the circuit pack. Point-of-use power supply (PUPS) The STS-1 interface circuit pack is equipped with its own PUPS that converts the -48 V dc office supply to the specific regulated direct-current voltage levels required by the local circuitry. Alarm LED definitions Table 1-7 lists the names of the STS-1 interface circuit pack LEDs, the possible cause for LED activation, and how LEDs are controlled (hardware, software, or firmware). Table 1-7 STS-1 interface circuit pack LEDs LED name Possible cause Controlled by Fail Alarm points component fail receive STS bus parity error Software Active Active unit Firmware LOS1 STS-1 No. 1 loss of signal Hardware/Firmware LOS2 STS-1 No. 2 loss of signal Hardware/Firmware LOS3 STS-1 No. 3 loss of signal Hardware/Firmware On a DS3/STS-1 mix shelf, the DS3 STS mapper, and STS-1 interface protection circuit packs share the same protection switcher. The protection switcher is bridged to only one of the protection circuit packs at a time. This bridge alternates every 60 minutes. The LOS LEDs on the protection circuit pack are disabled whenever the circuit pack is not bridged. When bridged, the LOS LEDs mirror the LOS LEDs on the working circuit pack. As a result, when the alternating bridge feature is activated and if the unused channels are not put out of service, the LOS LEDs on the protection circuit packs change state every 60 minutes. Circuit Pack Descriptions 323-1111-102 Rel 14 Standard Feb 2001

1-24 Circuit pack descriptions Equipping rules for the OC-12 or OC-3 shelf The equipping rules for the working STS-1 interface circuit packs are identical to the equipping rules for the working DS3 STS mappers. In an OC-12 shelf, install up to four working STS-1 interfaces in slots 11 (G1), 13 (G2), 15 (G3), and 17 (G4). In an OC-3 terminal shelf, install one working STS-1 interface in slot 11 (G1). In an OC-3 ADM shelf, install up to two working STS-1 interfaces (slots 11, G1, and 13, G2). Install one protection STS-1 interface in slot 3 of both the OC-12 and OC-3 shelf. Install a protection switcher circuit pack in slot 2. The protection arrangement is revertive 1:N where N 4 for the OC-12, N 2 for the OC-3 ADM, and N=1 for the OC-3. You can mix the STS-1 tributaries with DS1, DS3, and OC-3 tributaries on the same shelf. When mixing DS3 and STS-1 services, equip slots 11, 13, 15, and 17 with either DS3 mapper or STS-1 interface circuit packs (all combinations are supported). When a shelf is equipped with both DS3 mappers and STS-1 interface circuit packs, the services share the protection switcher circuit pack (in slot 2). Note: Install OC-3 tributaries only in an OC-12 shelf. See System Description, 323-1111-100, for more information on the shelf configurations. S/DMS TransportNode OC-3/OC-12 NE TBM Vol 1 323-1111-102 Rel 14 Standard Feb 2001

Circuit pack descriptions 1-25 Figure 1-14 Block diagram of the STS-1 electrical interface circuit pack FW-0086(TBMR8) Line and Section Overhead Insertion/Removal STS-1 1-3 (to/from BNC I/O cards) Data Regenerator Line Driver and LBO STS-1 Processor To optical interfaces (3 STS-1s) From optical interfaces (3 STS-1s) CBus Microcontroller CBus Interface To/from Processor card Unit Fail Active LOS 3 LOS 2 LOS 1 Legend: CBus = Control Bus PUPS = Point-of-Use Power Supply STS = Synchronous Transport Signal -48 V dc PUPS +5 V dc -4.5 V dc +12 V dc -12 V dc FW-0086 (TBM R8) Circuit Pack Descriptions 323-1111-102 Rel 14 Standard Feb 2001

1-26 Circuit pack descriptions Physical appearance of the STS-1 interface The STS-1 interface circuit pack is 27.7 cm (10.9 in.) high by 26.7 cm (10.1 in.) deep. It is a single-width circuit pack, 2.0 cm (0.8 in.) wide. Figure 1-15 shows the front view of a STS-1 interface. Figure 1-15 Front view of the STS-1 interface FW-0129.2 LOS 1 LOS 2 LOS 3 Active Fail LOS LEDs (yellow) Indicates a failure or a loss of an incoming STS-1 signal on ports 1, 2, or 3. The LEDs are hardware or software controlled. (Note: If both optical cards are removed, LOS LEDs may light on the protection STS-1 interface.) Active LED (green) Indicates the unit is processing STS-1s. The interface should not be removed while this LED is lit. The LED is software controlled. Fail LED (red) Indicates a circuit pack failure or the detection of a backplane parity error. The LED is software controlled. S/DMS TransportNode OC-3/OC-12 NE TBM Vol 1 323-1111-102 Rel 14 Standard Feb 2001

Circuit pack descriptions 1-27 Protection switcher circuit pack (NT4K60) Install the protection switcher circuit pack in the lower level of the shelf. Install this circuit pack if protection switching is provided for the working DS3 STS mappers or STS-1 interfaces. If protection is provided, install the protection switcher in slot 2. If a fault occurs in a working DS3 STS mapper, the protection switcher routes the traffic away from the faulty mapper to a protection mapper. If a fault occurs in a working STS-1 interface, the protection switcher routes the traffic away from the faulty interface to a protection interface. The protection switcher reroutes the traffic by switching the connections to the BNC I/O circuit packs. Functional description All working DS3 STS mappers or STS-1 interfaces are normally connected to BNC I/O circuit packs. Each mapper or interface that can process both directions (receive and transmit) of up to three DS3 or STS-1 signals is connected to a set of three BNC I/O circuit packs. Each mapper or interface that can process both directions of only one DS3 or STS-1 signal is connected to a single BNC I/O circuit pack. Each BNC I/O circuit pack is connected to the protection switcher as well as to the associated working mapper or interface. In normal operation, the signals that the protection switcher receives from the BNC I/O circuit packs are terminated. When a protection-switching request occurs for one of the working DS3 STS mappers or STS-1 interfaces, the protection switcher connects the three BNC I/O circuit packs to a protection DS3 STS mapper or a protection STS-1 interface (respectively). The protection arrangements are revertive (1:N). When the fault clears the protection switcher reconnects the three BNC I/O circuit packs to the working DS3 STS mapper or STS-1 interface. Note: When a shelf is equipped with both DS3 STS mapper and STS-1 interface circuit packs, the two services share the protection switcher circuit pack (in slot 2). As a result of this sharing, both service types are 1:N protected but only one service type can be protected at one time. Circuit Pack Descriptions 323-1111-102 Rel 14 Standard Feb 2001

1-28 Circuit pack descriptions Figure 1-16 shows the connections to the protection switcher. Each direction has separate connections and relays. Figure 1-16 Connections to the protection switcher circuit pack FW-1946(R8) For traffic flowing from the BNC I/O circuit packs toward the DS3/STS mappers or STS-1 interfaces: Connections to the 12 DS3 or STS-1 signals serving the four BNC I/O circuit packs Relays Connection to the DS3/STS protection mapper in slot 1 or the STS-1 protection interface in slot 3 For traffic flowing from the DS3/STS mappers or STS-1 interfaces toward the BNC I/O circuit packs: Connection to the DS3/STS protection mapper in slot 1 or the STS-1 protection interface in slot 3 Relays Connections from the 12 DS3 or STS-1 signals serving the four BNC I/O circuit packs S/DMS TransportNode OC-3/OC-12 NE TBM Vol 1 323-1111-102 Rel 14 Standard Feb 2001

Circuit pack descriptions 1-29 Figure 1-17 shows a functional block diagram of the 1:N protection switcher. Figure 1-17 Block diagram of the 1:N protection switcher circuit pack FW-1947(R8) 1:N Protection switcher From BNC I/O circuit pack (3 DS3s or STS-1s In) To BNC I/O circuit pack (3 DS3s or STS-1s Out) Legend: = Normally Open = Normally Closed = Resistive Termination To DS3 mapper or STS-1 interface circuit pack used for protection From DS3 mapper or STS-1 interface circuit pack used for protection Bus connections CBus The protection switch is connected to the CBus in the TBM shelf. Circuit Pack Descriptions 323-1111-102 Rel 14 Standard Feb 2001