APPLICATION NOTE GPIO ports configuration in ST30 devices INTRODUCTION The General Purpose IO (GPIO) Ports of ST30 devices are programmable by software in several modes:, Output, Alternate Function,, Output pushpull, Bidirectional weak push-pull and High impedance. It is possible to manage Analog input as well. This document describes best practice for GPIO ports configuration. Rev 2 September 2013 1/18 www.st.com 1
Contents 1 Introduction.................................................. 4 1.1 Functional description........................................... 4 1.2 Port configuration.............................................. 5 1.2.1 configuration.............................................. 5 1.2.2 Bidirectional configuration........................................ 6 1.2.3 Output configuration............................................ 6 1.2.4 Alternate Function configuration................................... 7 1.2.5 Analog input configuration........................................ 7 1.3 Port configuration procedure...................................... 8 1.3.1 Recommended configuration sequence............................. 8 1.3.2 From Alternate push-pull......................................... 9 1.3.3 From Alternate Function open drain................................ 9 1.3.4 From Output push-pull.......................................... 10 1.3.5 From........................................ 11 1.3.6 From /Output............................................. 12 1.3.7 From................................................... 13 1.3.8 From............................................. 14 1.4 Registers description.......................................... 15 1.4.1 Port Configuration Register 0 (PC0)............................... 15 1.4.2 Port Configuration Register 1 (PC1)............................... 16 1.4.3 Port Configuration Register 2 (PC2)............................... 16 2 Revision history.............................................. 17 2/18
List of tables Table 1. Port configuration summary................................................. 5 3/18
1 Introduction AN2261 1 Introduction The ST30 micro controller has up to seven 16-bit General Purpose I/O Ports. These ports are programmable by software in several modes:, Output, Alternate Function, Output open drain, Output push-pull, Bidirectional weak push-pull and High impedance. It is possible to manage Analog input as well. Main features of the GPIO ports are listed hereafter: /Output Alternate Function TTL Output push-pull Output weak push-pull Full software programmability 1.1 Functional description Figure 1 shows the basic structure of a General Purpose IO Port bit. A writing access to the IO Data register always loads the written data in the Output Latch. Any read access to the data register returns the content of the Latch. Depending upon the pin configuration the Latch either captures the physical signal level of the IO pin or holds the value of the Output Latch. Figure 1. Basic structure of an I/O port bit Alternate Function (IN) I/O PORT REGISTER INPUT LATCH OUTPUT LATCH TTL Alternate Function (OUT) Push-Pull Tristate Open Drain Weak Push-Pull I/O PIN The General Purpose IO Port has three configuration registers (PC0, PC1 and PC2) and one IO Data register (PD). 4/18
1 Introduction All the allowed port configurations, set by programming of the configuration registers are summarized in Table 1, where the index (n) is a generic IO bit. Table 1. Port configuration summary Register Analog Reserved Output Output Open Drain Output Push Pull Alternate Function Open Drain Alternate Function Push Pull PC0(n) 0 1 0 1 0 1 0 1 PC1(n) 0 0 1 1 0 0 1 1 PC2(n) 0 0 0 0 1 1 1 1 The number of available IO bits depends upon the package, the number of Alternate Function lines is directly related to the number of implemented peripherals. Please, refer to the datasheet for details. The configuration of the GPIO port at Reset depends from each specific device. Please, refer to the device s datasheet for default values. 1.2 Port configuration This paragraph illustrates in details the characteristic and functionality of each port mode. 1.2.1 configuration When the IO Port is programmed as : The Output Buffer is forced tristate The data present on the IO pin is sampled into the Latch every clock cycle A reading access to the Data register gets the value in the Latch. Figure 2 shows the Configuration of the IO Port bit. Figure 2. configuration Alternate Function (IN) I/O PORT DATA REGISTER INPUT LATCH OUTPUT LATCH TTL Tristate I/O PIN Alternate Function (OUT) 5/18
1 Introduction AN2261 1.2.2 Bidirectional configuration When the IO Port is programmed as Bidirectional: The Output Buffer is turned on in weak push-pull configuration The data in the Output Latch drives the IO pin A reading access to the IO Data register gets the Latch value. Figure 3 shows the Bidirectional Configuration of the IO Port. Figure 3. Bidirectional configuration Alternate Function (IN) I/O PORT DATA REGISTER INPUT LATCH OUTPUT LATCH Weak Push-Pull I/O PIN Alternate Function (OUT) 1.2.3 Output configuration When the IO Port is programmed as Output: The Output Buffer is turned on in open drain or push-pull configuration The data in the Output Latch drives the IO pin A reading access to the IO Data register gets the Output Latch value. Figure 4 shows the Output configuration of the IO Port bit. Figure 4. Output configuration Alternate Function (IN) I/O PORT DATA REGISTER INPUT LATCH OUTPUT LATCH Open Drain Push-Pull I/O PIN Alternate Function (OUT) 6/18
1 Introduction 1.2.4 Alternate Function configuration When the IO Port is programmed as Alternate Function: The Output Buffer is turned on in open drain or push-pull configuration The Output Buffer is driven by the signal coming from the peripheral (alternate function out) The data present on the IO pin is sampled into the Latch every clock cycle A reading access to the Data register gets the value in the Latch. Note: This pin configuration is Alternate Function Output. An alternate function input like UART_RX or capture must be always configured as.the reason for this is that an input signal can be distributed to all resources simultaneously, while an output signal must multiplexed among several sources (Output Latch, peripheral block, etc.) to avoid signal level conflicts. Figure 5 shows the Alternate Function configuration of the IO Port bit. Figure 5. Alternate Function configuration Alternate Function (IN) I/O PORT DATA REGISTER INPUT LATCH OUTPUT LATCH Open Drain Push-Pull I/O PIN Alternate Function (OUT) 1.2.5 Analog input configuration When the IO Port is programmed as Analog input configuration: The Output Buffer is forced tristate The Buffer is disabled (the Alternate Function is forced to a constant value) The can be input to an Analog peripheral. A reading access to the IO Data register gets the Output Latch value. 7/18
1 Introduction AN2261 Figure 6 shows the Analog input configuration of the IO Port bit. Figure 6. Analog input configuration I/O PORT DATA REGISTER INPUT LATCH OUTPUT LATCH Tristate I/O PIN Alternate Function (OUT) 1.3 Port configuration procedure In order to configure the port up to three (read-modify-) write accesses could be needed to change the actual pin configuration to the targeted one. Since these accesses can only be performed sequentially, intermediate configurations could result. To avoid undesired intermediate configurations and possible glitches, the following sequences are recommended. 1.3.1 Recommended configuration sequence It appears that the safest sequence for writing the Port Configuration registers in most situations is: PC2 - PC1 - PC0 The exceptions to this would be in the following transitions: 1. /Output to 2. /Output to Output push-pull 3. /Output to Alternate Function open drain 4. to 5. to Alternate Function open drain In all of these cases the safest sequence for writing the PC registers is: PC0 - PC1 - PC2 Note: It is possible to have a level change on a pin when transitioning between open drain and pushpull output modes. The resulting output level may be determined by the state of the GPIO Output, Alternate Function Output and/or external pull-up/down (if any). The user needs to be aware of the state of an output when changing the pin configuration. 8/18
1 Introduction 1.3.2 From Alternate push-pull If the port is set to Alternate Push pull, use the following sequences to change mode. Alternate push-pull to /Output IN Alternate push-pull to /Output IN Alternate push-pull to /Output /Output Alternate push-pull to Output push-pull Alternate push-pull to Output Push pull Output push-pull Alternate push-pull to Alternate Function open drain Alternate Function open drain 1.3.3 From Alternate Function open drain If the port is set to Alternate Function open drain, use the following sequences to change mode. Alternate Function Open-Drain to Reserved 9/18
1 Introduction AN2261 Alternate Function Open-Drain to Reserved IN Alternate Function Open-Drain to /Output Reserved /Output Alternate Function Open-Drain to Alternate Function Open-Drain to Output push-pull Output push-pull Alternate Function Open-Drain to Alternate Function push-pull Alternate Function push-pull 1.3.4 From Output push-pull If the port is set to Output Push pull, use the following sequences to change mode. Output push-pull to Output push-pull to Output push-pull to Output /Output 10/18
1 Introduction Output push-pull to Output push-pull to Alternate Function open drain Alternate Function push-pull Alternate Function open drain Output push-pull to Alternate Function push-pull Alternate Function push-pull 1.3.5 From If the port is set to Output Open-Drain, use the following sequences to change mode. to to IN to /Output Reserved /Output to Output push-pull Output push-pull to Alternate Function open drain Alternate Function open drain 11/18
1 Introduction AN2261 to Alternate Function push-pull Alternate Function open drain Alternate Function push-pull 1.3.6 From /Output If the port is set to /Output, use the following sequences to change mode. /Output to /Output to Output to Alternate Function push-pull (1) Output Push pull (2) 1. Glitch possible if alternate function is a test function 2. Glitch possible if OUTPUT = 1 with no external pull-up Alternatively, the following sequence can be used: Reserved /Output to Output push-pull Alternate Function push-pull (1) Output push-pull 1. Glitch possible if alternate function is a test function Alternatively, the following sequence can be used: Output push-pull 12/18
1 Introduction /Output to Alternate Function open drain Alternate Function push-pull (1) Alternate Function open drain 1. Glitch possible if alternate function is a test function, and If OUTPUT = 1 with no external pull-up Alternatively, the following sequence can be used:, 1.3.7 From Reserved Alternate Function open drain /Output to Alternate Function push-pull Alternate Function push-pull If the port is set to, use the following sequences to change mode. to to /Output /Output to OUTOPP (1) 1. Glitch possible if OUTPUT = 1 with no external pull-up Alternatively, the following sequence can be used: 13/18
1 Introduction AN2261 to Output push-pull 1.3.8 From Output push-pull to Alternate Function open drain Output push-pull (1) Alternate Function push-pull (2) (3) 1. Glitch possible if OUTPUT differs from ALT OUTPUT value 2. Glitch possible if OUTPUT = 1 with no external pull-up 3. Glitch possible is alternate function is a test function Alternatively, the following sequence can be used: Reserved Alternate Function open drain to Alternate Function push-pull Output push-pull Alternate Function push-pull If the port is set to, use the following sequences to change mode. to to /Output Reserved /Output to 14/18
1 Introduction to Output push-pull Output push-pull to Alternate Function open drain Alternate Function open drain to Alternate Function push-pull Alternate Function open drain Alternate Function push-pull 1.4 Registers description For the base address of the Port configuration register, please, refer to the device s User Manual. Note: GPIO Port registers can not be accessed by byte. 1.4.1 Port Configuration Register 0 (PC0) Address Offset: 00h Reset value: Refer to the device Architecture Overview section of the device s datasheet. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C015 C014 C013 C012 C011 C010 C09 C08 C07 C06 C05 C04 C03 C02 C01 C00 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bit 15:0 C0[15:0]: Port Configuration bits. See Table 1 to configure the IO Port. 15/18
1 Introduction AN2261 1.4.2 Port Configuration Register 1 (PC1) Address Offset: 04h Reset value: Refer to the device Architecture Overview section of the device s datasheet. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C115 C114 C113 C112 C111 C110 C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bit 15:0 C1[15:0]: Port Configuration bits. See Table 1 to configure the IO Port. 1.4.3 Port Configuration Register 2 (PC2) Address Offset: 08h Reset value: Refer to the device Architecture Overview section of the device s datasheet. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C215 C214 C213 C212 C211 C210 C29 C28 C27 C26 C25 C24 C23 C22 C21 C20 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bit 15:0 C2[15:0]: Port Configuration bits. See Table 1 to configure the IO Port. 16/18
2 Revision history 2 Revision history Date Revision Changes 08-Nov-2005 1 Initial release. 25-Sep-2013 2 Updated disclaimer. 17/18
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