Patrick B. Billings. NMSG/NPD Applications Engineering

Patrick B. Billings NMSG/NPD Applications Engineering June 2012 Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis, mobilegt, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SafeAssure, the SafeAssure logo, SMAROS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. 2012 Freescale Semiconductor, Inc..

Session Objectives etsec Overview Initialization / Re-Configuration Considerations Media Independent Interface (MII) Management Unused Pin Termination Recommendations Design Considerations Troubleshooting Tips Conclusion 2

Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis, mobilegt, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SafeAssure, the SafeAssure logo, SMAROS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. 2012 Freescale Semiconductor, Inc..

After completing this session you will understand: The caveats of no PHY with the Media Independent Interface (MII) in Half-Duplex Mode The expectations of no PHY with the Reduced Gigabit MII (RGMII) interface The expectations of no PHY with the Serial GMII (SGMII) interface The basic principles to apply to any chosen interface The best steps for an Ethernet driver The common topics for troubleshooting 4

Media Layers Host Layers 7: Application end use (FTP, SMTP, ) 6: Presentation encryption & decryption 5: Session interhost communication 4: Transport reliability and flow control 3: Network / Internet logical addressing 2: Data Link (MAC) physical addressing 1: Physical (PHY) transmission/reception of bits OSI Model Layers Media Access Control (MAC) Ethernet Type II Frame L2 header L3 header (IPv4/IPv6) L4 header (TCP/UDP) Preamble SFD DA SA EthType Payload CRC32 IFG 7 bytes 1 byte 6 bytes 6 bytes 2 bytes 46 1500 bytes 4 bytes 12 bytes 6

etsec etsec etsec etsec OCeaN e500 L2 Cache LBC Security Engine ECM AXI2Cu AXI2Cu DDR PCI-X TIP: If the HIC or AXI2Cu Gasket are hung, an etsec reset can not recover the etsec for proper operation. Must perform a hard reset of the device. TIP: Tx PAUSE Frames come from another logic block. Don t originate from DDR. HIC HIC gmac0 gmac1 gmac0 gmac1 wrp_0 wrp_1 TIP: MAC reset logic does not reset TBI PHY. RapidIO DMA PCI Express 7

INTERFACE SPEED (Mbps) MII (3.3v) 100 Full / Half (Media Independent Interface) 1 10 Full / Half RMII (3.3v) 100 (Reduced MII) 2 10 DUPLEX ECNTRL INTERFACE BITS MACCFG2 Full / Half Full / Half all zeroes all zeroes R100M=1; RMM=1 RMM=1 I/F Mode=0b01; FD=1 / 0 I/F Mode=0b01; FD=1 / 0 I/F Mode=0b01; FD=1 / 0 I/F Mode=0b01; FD=1 / 0 GMII (3.3v) 1000 Full GMMIM=1 I/F Mode=0b10; FD=1 (Gigabit MII) 3 RGMII (2.5v) 1000 (Reduced GMII) 2 100 10 SGMII (2.5v) 1000 (Serial GMII) 2 100 10 Full Full / Half Full / Half Full Full / Half Full / Half RPM=1 RPM=1; R100M=1 RPM=1 TBIM=1; SGMIIM=1 TBIM=1; SGMIIM=1;R100M=1 TBIM=1; SGMIIM=1 1 100Mbps is chosen by 25MHz clock source. 10Mbps is chosen by 2.5Mhz clock source. 2 Half Duplex -10/100 is supported on this interface via encoding methods because there are no physical COL and CRS signals. 3 10/100 supported via fallback mode to MII by setting MACCFG2[I/F Mode]=0b01. MACCFG2[FD] selects between FD and HD. I/F Mode=0b10; FD=1 I/F Mode=0b01; FD=1 / 0 I/F Mode=0b01; FD=1 / 0 I/F Mode=0b10; FD=1 I/F Mode=0b01; FD=1 / 0 I/F Mode=0b01; FD=1 / 0 TIP: MAC level loopback testing may be problematic for 10-bit interfaces. This includes TBI and SGMII. Also, MAC loopback is only for full-duplex mode and a TX clock is only used. 8

INTERFACE SPEED (Mbps) DUPLE X ECNTRL INTERFACE BITS MACCFG2 TBI (3.3v) (Ten Bit Interface) 1000 Full TBIM=1 I/F Mode=0b10; FD=1 RTBI (2.5v) (Reduced TBI) 1000 Full TBIM=1; RPM=1 I/F Mode=0b10; FD=1 FIFO (3.3v/2.5v) GMII Style (FIFOCFG[SIGM]=0b00) 1 Platform Clk/4.2 8-bit Full 16-bit Full FIFM=1; RPM=1 FIFM=1 - - FIFO (3.3v/2.5v) Encoded (FIFOCFG[SIGM]=0b01) 1 Platform Clk/3.2 8-bit Full 16-bit Full FIFM=1; RPM=1 FIFM=1 - - 1 FIFO mode bypasses most MAC configuration registers. See FIFOCFG and RCTRL for options. TIP: Interface Selection does not change onthe-fly. Different MAC devices will support various other interfaces (i.e., QSGMII, XAUI, XFI, HiGig, HiGig+, Interlaken). 9

RX FEATURE Wake-On-LAN (Magic Packet OR Filer Rule) Receive Short Frames Exact Match MAC Addresses (15 available) Lossless Flow Control (RxBDs) Custom L2 Header (Layer 2 Offset) 1588 Timestamping Little Endian Descriptor Mode Snooping /Stashing RxBD and/or Rx Buffer Accesses Packet Alignment Padding Event Notifications via Maskable /Selectable Interrupts Control Frame Accept (Capture in Memory) MIB Statistics (auto zeroing option) Rx Interrupt Coalescing Broadcast Frame Reject Promiscuous Mode Length Check (Layer 2) Automatic VLAN TAG Extraction Parsing & Filing (single or multi queue) Extended Group Address Hashing (256 -> 512) IP Header Checksum (Layer 3) TCP/UDP Header Checksum (Layer 4) Preamble Accept ( Capture in Memory) Huge Frame Reception TX FEATURE TxBD modes (POLL or WAIT) Custom L2 Header 1588 Timestamping Little Endian Descriptor Mode Snoop TxBD and/or Tx Buffer Accesses Transmit On Demand for TxBD Ring 0 Event Notifications via Maskable /Selectable Interrupts MIB statistics (auto zeroing option) Automatic VLAN TAG Insertion Tx Interrupt Coalescing IP Header Checksum (Layer 3) TCP/UDP Header Checksum (Layer 4) PADDDING and CRC APPENDING options Interpacket Gap Options Hafl-Duplex Options Transmit Half-Duplex Flow Control Transmit & Receive Pause Frames Transmit Ring Scheduling ( Single polled, priority & modified weighted roundrobin modes) Custom Preamble Huge Frame Transmission Internal Loopback Main Config Registers: RCTRL TCTRL MACCFG1 MACCFG2 TXIC RXIC ECNTRL EDIS DMACTRL MRBLR MAXFRM FIFOCFG TIP: Do not change config bits on-the-fly 10

TIP: etsec has min operating frequency of 133MHz for gigabit modes. Ensure proper ratio via SCCR on 83xx platforms. 13

INTERFACE TX Clock RX Clock Reference Clock MII (Media Independent Interface) Source: External (i.e., PHY) Speed: 2.5/25Mhz etsec Pin: INPUT TSECn_TX_CLK Source: External (i.e., PHY) Speed: 2.5/25MHz etsec Pin: INPUT TSECn_RX_CLK - RMII (Reduced MII) Source: External (i.e., PHY) Speed: 5/50Mhz etsec Pin: INPUT TSECn_TX_CLK TSECn_TX_CLK is the only clock used - GMII (Gigabit MII) 1 Source: etsec Speed: 125Mhz etsec Pin: OUTPUT TSECn_GTX_CLK Source: External (i.e., PHY) Speed: 125MHz etsec Pin: INPUT TSECn_RX_CLK Source: External (i.e., OSC) Speed: 125MHz etsec Pin: INPUT - EC_GTX_CLK125 RGMII (Reduced GMII) 2 Source: etsec Speed 1 : 2.5/25/125Mhz etsec Pin: OUTPUT TSECn_GTX_CLK Source: External (i.e., PHY) Speed: 2.5/25/125MHz etsec Pin: INPUT TSECn_RX_CLK Source: External (i.e., OSC) Speed: 125MHz etsec Pin: INPUT - EC_GTX_CLK125 SGMII recovered recovered On Chip SerDes:100MHz or 125MHz SerDes differential pins: INPUT (Serial GMII) SD_REF_CLK_B; SD_REF_CLK 1 For GMII interface 10/100 Mbps Fallback Mode support, TX Clock is TSECn_TX_CLK. 2 For RGMII 10/100 Mbps support, internal dividers provide 2.5MHz (divide by 50) and 25MHz (divide by 5). 15

INTERFACE TX Clock RX Clock Reference Clock TBI (Ten Bit Interface) Source: etsec Speed: 125Mhz etsec Pin: OUTPUT TSECn_GTX_CLK Source: External Speed 1 : 62.5MHz (x2) etsec Pins: TSECn_TX_CLK (RX_CLK1); TSECn_RX_CLK (RX_CLK0) Source: External (i.e., OSC) Speed: 125MHz etsec Pin: INPUT - EC_GTX_CLK125 RTBI (Reduced TBI) Source: etsec Speed: 125Mhz etsec Pin: OUTPUT TSECn_GTX_CLK Source: External (i.e., PHY) Speed: 125MHz etsec Pin: INPUT TSECn_RX_CLK Source: External (i.e., OSC) Speed: 125MHz etsec Pin: INPUT - EC_GTX_CLK125 FIFO GMII Style & Encoded Packet Source: etsec Speed: 155Mhz etsec Pin: OUTPUT Source: ASIC Speed: 155MHz etsec Pin: INPUT TSECn_TX_CLK, 155MHz etsec Pin: INPUT 1 Two out of phase 62.5MHz clocks. TIP: A stable clock is needed to allow read/write access to MAC registers TIP: Don t leave unused input pins floating TIP: Sync d bits in MACCFG1 indicate clock is good across clock domains 16

INTERFACE SPEED (Mbps) DUPLEX MII (Media Independent Interface) 10 / 100 Full / Half RMII (Reduced MII) 1 10 / 100 Full / Half SMII (Serial MII) 1 10 / 100 Full / Half GMII (Gigabit MII) 2 10 / 100 / 1000 Full RGMII (Reduced GMII) 1 10 / 100 / 1000 Full / Half SGMII (Serial GMII) 1 10 / 100 / 1000 Full / Half TBI (Ten Bit Interface) 1000 Full RTBI (Reduced TBI) 1000 Full FIFO (8/16-bit) GMII Style (Platform Clk/4.2) Encoded (Platform Clk/3.2) Full Controllers CPM-FCC (8280,8560), QE-UEC (8360), FEC (880), TSEC (8560), etsec (8572), dtsec (P4080), 10GEC (P4080), VeTSEC (P1020), memac (T4240) (Some controllers support different interfaces. Must refer to each products specific documentation.) 1 Half Duplex -10/100 is supported on this interface via encoding methods because there are no physical COL and CRS signals. 2 10/100 supported via fallback mode to MII 17

checksum Transmit TCP and UDP checksums of frames up to 9.6 kb at DMA rates IPv4 header checksum and IPv6 header skip Receive TOE at Gigabit Ethernet or 2.5 Gbps FIFO rates Frame parser peels encapsulated VLAN, MPLS, PPPoE, LLC, IPv4, IPv6, IP over IP, TCP and UDP headers Optional word re-alignment of IP header data payload DMA Add 2kB Rx FIFO: Data + TOE status 8/16-bit FIFO Interface 10 kb Tx FIFO: Data w/headers Layers 2 4 Rx Frame Parser fields to QoS filer CkSm 10/100/1000 Ethernet MAC data checksum TCP/IP Offload Engine Add CkSm Tx checksumming @64 bits per cycle 18

extracted header fields Receive Inbound frame parsed and headers extracted Filer table searched to locate RxBD ring to DMA Frame rejection supported in rule set 256-entry filing table field value TCP port # queue #3 priority select queue # Transmit Stack queues frames on 1 of 8 TxBD rings WRR scheduler allocates MAC bandwidth according to 8-bit queue weights Priority-based queuing supported 8 TxBD Queues Frame Parser L2 to L4 10/100/1000 Ethernet MAC Rx FIFO data address BD cache DMA Weighted round-robin scheduler (1 with priority override) 10/100/1000 Ethernet MAC 19

etsec uses 8-byte prepended Frame Control Block (FCB): Driver is responsible for populating and reading FCBs, stack never sees FCB directly Since driver is responsible for allocating and freeing buffers, room for FCBs can be easily set aside by driver code Driver adjusts data pointer to skip FCB when passing the pointer to stack Ethernet Device drivers use conventional descriptor rings 8-byte Tx FCB: Checksum offl. parameters FCB Ethernet frame for Transmission TCP/IP stack Device Driver etsec 8-byte Rx FCB: Checksum offl. status FCB Received Ethernet frame 20

VLAN control word is valid Layer 3 header is an IP header IP header is IP version 6. Valid only if IP=1 Layer 4 header is a TCP or UDP header UDP protocol at Layer 4 if UDP=1 Calculate IP Header Checksum Calculate TCP or UDP Header Checksum Disable calculation of TCP or UDP pseudo-header checksum (instead use PHCS) for overall TCP/UDP checksum 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Offset +0 VLN IP IP6 TUP UDP CIP CTU NPH Offset +2 L4OS L3OS Offset +4 Offset +6 VLCTL Layer 4 Header Offset 802.1Q VLAN Control Word if VLN=1 Layer 3 Header Offset 21

VLAN tag recognized, see control word IP header found, see Next Header protocol ID IPv6 header type TCP or UDP header found IPv4 header checksum checked TCP/UDP checksum checked IPv4 header checksum error TCP/UDP checksum error Parse error Packet matched a General Purpose Interrupt file rule 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Offset +0 VLN IP IP6 TUP CIP CTU EIP ETU PERR GPF Offset +2 RQ PRO Offset +4 Offset +6 VLCTL Receive Queue Index 802.1Q VLAN Control Word if VLN=1 Next Header Protocol 22

DDR Transceivers are called Medium Attachment Units (MAUs) in IEEE 802.3 Medium: Coaxial cable, twisted pair, optical fiber AUI: MII, RMII, GMII, etc. Interrupt Link Partner PHY (Layer 1) PHY (Layer 1) etsec based device (Layer 2,3,4) Advertise (reg 4) Advertise (reg 4) CPU ECM/MCM DDR CTRL DMA Partner Ability (reg 5) Partner Ability (reg 5) MAC etsec Data and Buffer Descriptors AUI- Attachment Unit Interface DMA Direct Memory Access MDC MDIO 23

etsec Memory Mapped Registers TxBD Table Base (TBASEn) RxBD Table Base (RBASEn) Memory TxBD Ring Buffer RxBD Ring Buffer TxBD Status/Control Data Length Buffer Pointer RxBD Status/Control Data Length Buffer Pointer TIP: BD rings must be contiguous. Minimum of 9 BDs per ring for etsec because of pre-fetch mechanism. 25

Control (written by SW) R:Ready, SW sets, etsec clears after use PAD:Padding, Auto pad length to min 64bytes and append CRC W:Wrap, End-of-ring indicator I:Interrupt, Set Tx event bits in IEVENT (IMASK allows interrupts to the core) L: Last, Last BD in frame indicator TC:Transmit, CRC Allow per frame CRC appendage if MACCFG2 not configured to append CRC for every framet PRE:Custom Preamble, if MACCFG2[PreAm_TxEN]=1 HFE:Huge Frame Enable, per frame non-truncation for packets greater than MAXFRM CF:Control Frame, send control frames even in pause state TOE:TCP/IP Off-Load, etsec expects TxFCB to precede the Tx frame Status (written by etsec) DEF:Defer, frame was deferred LC:Late Collision, frame experienced a collision outside of collision window RL:Retry Limit, frame exceeded collision retry limit RC:Retry Count, number of retries experienced for this frame UN:Under-run, Tx FIFO starvation indicator TIP: For multiple BD Tx frames, set R bit in 1 st BD last TIP: If etsec fetches TxBD with length=0, controller may hang 26

Control (written by SW) E:Empty, SW sets, etsec clears after use RO1:RSVD, SW general purpose use W:Wrap, End-of-ring indicator I:Interrupt, Set Rx event bits in IEVENT (IMASK allows interrupts to the core) TIP: MRBLR determines how many RxBDs etsec uses for a frame Status (written by etsec) L:Last, last BD in received frame F:First, first BD in received frame M:Miss, frame accepted but did not match any address (promiscuous mode) BC:Broadcast, frame has a broadcast address MC:Multicast, frame has a multicast address LG:Large, frame exceeded MAXFRM, truncated if huge frame enable not set in MACCFG2 NO:Non-octet, frame not a non-fractional multiple of eight SH:Short Frame, frame less than 64 bytes CR:CRC Error, valid frame with CRC error OV:Over-run, frame caused Rx FIFO capacity to be exceeded TR:Truncation, frame was truncated 27

DDR etsec1 BD Rings 0 thru 7 Tx BD Ring #0 IEVENT RSTAT etsec1 TSTAT Rx Error etsec1 core0 PIC etsec2 BD Rings 0 thru 7 Tx BD Ring #0 IEVENT RSTAT etsec2 TSTAT Rx Error etsec2 core1 28

The documentation will have an update with the following steps: 1. Set MIIMCOM=0x0000_0000 (Write Cycle) 2. Set MIIMADD=0x0000_nn11 (TBICON, where nn=tbipa) 3. Set MIIMCON=0x0000_8000 (TBICON[Soft_Reset]=1) 4. Poll MIIMIND=0x0000_0000 (Write Cycle complete) 5. Wait 3-10 Tx interface clocks (interface clk is set at 125MHz) 6. Set MIIMCON=0x0000_8020 (TBICON[Clock Select]=1 for SerDes clock source) 7. Poll MIIMIND=0x0000_0000 (Write Cycle complete) 8. Wait 3-10 Tx interface clocks 9. Initialize MACCFG2 10. Wait 3-10 Tx interface clocks 11. Set MACCFG1=0x8000_0000 (Soft Reset=1) 12. Wait 3-10 Tx interface clocks 13. Set MACCFG1=0x0000_0000 (Soft Reset=0) 14. Wait 3-10 Tx interface clocks 15. Set MIIMCON=0x0000_0020 (TBICON[Soft_Reset]=0) 16. Poll MIIMIND=0x0000_0000 (Write Cycle complete) 17. Wait 3-10 Tx interface clocks 18. Continue with remaining controller init/soft reset/reconfigure steps A SerDes reset here if desired while MAC and TBI are held in reset 29

TSEC 1 MAC TSEC 1 TBI GMII, TBI MDC/MDIO TSEC 2 MAC TSEC 2 TBI GMII, TBI MDC/MDIO CPM-FEC MII MDC/MDIO PHY 1 PHY 2 PHY X TIP: For TBI and SGMII operation with same MDC/MDIO signals, TBIPA must have a unique PHY address from external PHYs 31

TIP: It is best to consult device specific design checklist or bring-up guide 33

External 125 MHz clock source is needed etsec outputs TX 125 MHz clock MII Fallback enables TSECn_TX_CLK, CRS, and COL Collision Detect (TSECn_COL) TIP: MACCFG2[I/F Mode] affects the logic path for the clocking. 0b10 = 1Gbps 0b01 = 10/100Mbps 35

External 125 MHz clock source is needed etsec outputs TX 125 MHz clock etsec has internal dividers to support 100 Mbps and 10 Mbps Half-Duplex is encoded (No COL and CRS signals used) TX and RX have different timings for the data (needed delay provided by trace or PHY) 36

SerDes block is used (differential signaling) 100MHz or 125Mhz Clk_P Clk_N Lane n Ten Bit Interface (TBI) signals are routed to the SerDes block 10/100/1000 Mbps supported with rate adaptation logic for SGMII SerDes TXD_P TXD_N Fixed 1.25Gbaud RXD_P RXD_N PHY Link Partner 1000Base-X is only 1 Gbps Internal TBI PHY is used to establish the link (Speed fixed at 1000Mbps) TBI TBI PHY etsec MDC MDIO SGMII or 1000Base-X Advertisement registers may have two formats: 1000Base-X or SGMII. Software determines which is used. TIP: Reception of valid symbols set TBI SR[Link Status] 37

SerDes block is used (differential signaling) 100MHz or 125Mhz Clk_P Clk_N Lane n Ten Bit Interface (TBI) interface signals are routed to the SerDes block 10/100/1000 Mbps supported with rate adaptation logic for SGMII 1000Base-X is only 1 Gbps Internal TBI PHY is used to establish the link (Speed fixed at 1000Mbps) SerDes TBI TBI PHY etsec TXD_P TXD_N Fixed 1.25Gbaud RXD_P RXD_N MDC X MDIO SWITCH (MAC) SGMII or 1000Base-X Link Partner Link Partner Link Partner Lose MII management because no slave device. Configuration and status info can be placed in system memory for access Two Masters 38

COL and CRS are active Clock speed 2.5 MHz or 25 MHz Collisions are normal and a back-off algorithm is used PHY manages the detection of collisions PHY manages the detection of the carrier Should be no reception when transmitting (No MAC loopback for Half-Duplex Mode) 39

Typically, when the PHY detects a collision event, it asserts the COL signal to the MPC8548. The MPC8548 then employs a back-off algorithm to determine the number of time slots to wait before retransmitting. One time slot equals 512 bits. The MAC-calculated back-off time is a multiple of 1 time slot and a generated random value. MPC8548 processor employs the IEEE standard 802.3 back-off algorithm. Random is based on hardware from an 11-bit linear feedback shift register (LFSR). The LFSR starts with a seed value based on the polynomial function implemented. For each Tx clock, the logic generates a pseudorandom number for use in the back-off time calculation. To add to the randomness, bit 2 of the 32-bit CRC from the etsec is XORed with bit 2 of the LFSR. MPC8548 is used only as an example 40

COL and CRS are active Clock speed 2.5 MHz or 25 MHz Collisions are normal and a backoff algorithm is used Who manages the detection of collisions? Who manages the detection of the carrier? Should be no reception when transmitting (No MAC loopback for Half-Duplex Mode) What are we connected to? A bus Point-to-point device Backplane traces A connector? 41

Carrier Sense and Collision Detect must be provided. By default, if more than 15 collision events are detected before a successful transmission, the MPC8548 processor reports excessive collisions and no longer attempts to transmit the data. Software must take steps to re-enable the etsec transmitter. Because the values from the LFSR are deterministic, MAC-to-MAC connections can become synchronized relative to Tx clocks and generate identical backoff times, causing the devices in the system to re-transmit at the same time. This can lead to an excessive collision event. The logic that controls the assertion of the COL signal must ensure it only asserts after the preamble, SFD, DA, SA, and Type fields of an Ethernet frame (22 bytes into the frame). Since each Tx clock sends a nibble of data over the MII, this equates to 44 Tx clocks. The devices should exhibit a soft reset at different points in time while the Tx clock is running. The logic that drives the Rx_DV signal must not assert it to an MPC8548 processor that is concurrently transmitting. 42

Ensure signal integrity monotonic clock edges meet rise/fall time and other timing requirements matched I/O levels Point-to-Point connections Bus connections if there is an arbiter for CRS and COL 43

Ensure both IEVENT[GRSC] & IEVENT[GTSC] are set before clearing Rx_EN & Tx_EN Wait long enough for the IEVENT to happen before calling it a hang BAD: while (!(gfar_read(&priv->regs->ievent) & (IEVENT_GRSC IEVENT_GTSC))) cpu_relax(); FIXED: while ((gfar_read(&priv->regs->ievent) & (IEVENT_GRSC IEVENT_GTSC))!= (IEVENT_GRSC IEVENT_GTSC)) cpu_relax(); Include the msync instruction to avoid out-of-order execution (memory barrier) tx_bd->status = (PQUICC_BDSTAT_TX_RDY PQUICC_BDSTAT_TX_LAST PQUICC_BDSTAT_TX_TC PQUICC_BDSTAT_TX_INT); asm volatile ("msync"); regs->tstat = TSEC_TSTAT_THLT; 2 There is the potential the etsec can start fetching a TxBD before it is prepared. Danger holds true for Rx side as well. Ensure minimum of 3 TX Interface clocks worth of settling time for etsec resets. Max 10 Tx clocks should suffice. Non-compliance could lead to latent fails 1200ns for 10Mbps (2.5Mhz); 120ns for 100Mbps (25Mhz); 24ns for 1000Mbps (125Mhz) 1 44

FREQ Greater than +/- 300 PPM Monotonic Edges GOOD GTX_CLK / TX_CLK BAD BAD RX_CLK Rise/Fall Meets Spec Really Duty Cycle Agnostic Edge Sensitive Logic 46

When both Rx &TX are used, a frequency requirement of +/- 300ppm between Rx and TX clock sources must be met. For example At 125MHz and 300ppm this allows for an error of 37.5 KHz (125*300) between the clocks. To ensure we have margin let s assume we go with 125MHz and 200ppm (tighter accuracy). This allows for an error of 25KHz between the clocks (125*200) Oscillator 1 25 MHz +/- 25 ppm => +/- 625 Hz error from the oscillator. GTX clock would have error magnified by PHY PLL (x5) giving +/-3125 Hz error Oscillator 2 25 MHz +/- 25 ppm => +/- 625 Hz error from the oscillator. RX_CLK2 would have error magnified by PHY PLL (x5) giving +/-3125 Hz error Worst case frequency error of the two clocks would be 3125+3125=6250 Hz worth of error. This scenario would meet the ppm requirement. 47

Don t change MAC configuration bits on-the-fly, only in graceful stop state (GTSC/GRSC set) or with controller disabled (TxEN/RxEN cleared). Clock Integrity Meets +/- 300 PPM requirement Meets rise/fall time spec Has monotonic edges Verify POR settings Verify power rails Verify speed and duplex settings in MACCFG2 and ECNTRL Check latest errata Minimum frequency of operation for etsec is 133MHz for Gigabit modes MPC85xx etsec operates at CCB/2 MPC83xx etsec operates at CSB, CSB/2, or CSB/3 (check SCCR register) 48

Don t change FIFO threshold registers from their default values Include TBI PHY reset in initialization steps Check latest advisories 49

Spec Min max tskew T -0.5ns 0.5ns tskew R 1ns 2.6ns 50

Spec Min max tskew T -0.5ns 0.5ns tskew R 1ns 2.6ns 51

Many physical interface options (AUIs) are available for an Ethernet solution. 25 options including speed and duplex. Freescale designs to an interface specification, so in most cases proper operation is achieved if the interface signal requirements are met. (timings, IO levels, etc.) Input Output Buffer Information Specification (IBIS) modeling can help determine signal degradation to/from our device across the interconnect. For SGMII, differential signaling should not be a problem for traces less than 12 inches. Bad clocking could result in CRC errors. Use a troubleshooting checklist. Facebook.com/Freescale Tag yourself in photos and upload your own! Tweeting? Please use hashtag #FTF2012 Session materials will be posted @ www.freescale.com/ftf Look for announcements in the FTF Group on LinkedIn or follow Freescale on Twitter 53

Terminate unused pins Check any software advisories that may impact the driver code Consult device documentation to understand what interfaces and features are supported Facebook.com/Freescale Tag yourself in photos and upload your own! Tweeting? Please use hashtag #FTF2012 Session materials will be posted @ www.freescale.com/ftf Look for announcements in the FTF Group on LinkedIn or follow Freescale on Twitter 54