CPE 323 CPE 323 Introduction to Embedded Computer Systems: Introduction Instructor: Dr Aleksandar Milenkovic Lecture Notes Syllabus textbook & other references grading policy important dates course outline Prerequisites memory organization decoding combinatorial and sequential logic important for system architecture Microcomputer Lab (EB 106) Introduction sessions Lab instructor CPE/EE 421/521 Microcomputers 2 CPE 323 LAB Session on-line LAB manual Access cards Accounts Lab Assistant: Joel Wilder Lab sessions #1 - Mon: 5:30 7:00pm #2 - Tues: 5:30-7:00pm Backup - Tues: 7:00 8:30pm Sign-up sheet - if needed CPE/EE 421/521 Microcomputers 3 Outline Embedded systems: structure and organization Applications Technology Trends Historical perspective CPE/EE 421/521 Microcomputers 4 Alex Milenkovich 1
Embedded Computer Systems A Microcontroller-Based System Stand alone system based on a microprocessor An embedded system dedicated to a specific application control system/monitoring system optimization for a single function (system resources, extension, ) block diagram inputs processing outputs Number of microprocessors in our environment? CPE/EE 421/521 Microcomputers 5 LCD Keypad Adj. Vol. Regul. LEDs Thermistor Switches RS232 RS232 controller Analog I/O 2-axes joystick µc CPE/EE 421/521 Microcomputers 6 Wireless Body Area Network Data Flow ECG & tilt sensor PPG & movement sensor Wireless gateway & temperature/ humidity sensor ZigBee or custom wireless Emergency Server t, states A/D µp system D/A Input Processing Output Body Area Network GPRS Internet Temperature sensor control signals Movement sensors Personal Server Medical Server (Mayo Clinic) µp 78 º Physician s Server INPUT PROCESSING OUTPUT CPE/EE 421/521 Microcomputers 7 CPE/EE 421/521 Microcomputers 8 Alex Milenkovich 2
Microcomputer Block Diagram CPE/EE 421/521 Microcomputers 9 Microprocessor System Architecture System Architecture Single Board Computers (SBC) block diagram (modules, cards) System bus Multibus, VME, ISA, PCI, Multiple masters CPU Clock and CPU Control Circuits 1 MHz - 1 GHz power-up and reset circuits Address Decoder Address and Data Bus Buffers Bus Arbitration Control management CPE/EE 421/521 Microcomputers 10 Microprocessor System Architecture Microprocessor System Architecture Module Virtual memory / Physical memory ROM, RAM, video memory static/dynamic Peripheral Module serial interface RS232 (CRT, mouse), USB, Firewire (IEEE 1394) parallel interface printer interface timer time/frequency measurement PC architecture CPU PCI ISA CPE/EE 421/521 Microcomputers 11 CPE/EE 421/521 Microcomputers 12 Alex Milenkovich 3
Von Neumann Architecture Von Neumann Architecture Processing Elements sequential execution Read/Write linear array of fixed size cells Data and instruction store I/O unit Address/Data/Control bus 0 1 2 3 N Wbits log 2 N Von Neumann Architecture Read/Write I/O (peripherals) address control data PE (Processing Element) Control Unit ALU CPE/EE 421/521 Microcomputers 13 CPE/EE 421/521 Microcomputers 14 Von Neumann vs. Harvard Block Diagram of a Personal Computer Von Neumann Architecture Read/Write address data PE (Processing Element) Harvard Architecture Program Data data address address data PE (Processing Element) CPE/EE 421/521 Microcomputers 15 CPE/EE 421/521 Microcomputers 16 Alex Milenkovich 4
A Typical Small Embedded System Digital Thermometer A Microcontroller-Based System Todd D. Morton Embedded Microcontrollers Copyright 2001 by Prentice-Hall Inc. Todd D. Morton Embedded Microcontrollers Copyright 2001 by Prentice-Hall Inc. CPE/EE 421/521 Microcomputers 17 CPE/EE 421/521 Microcomputers 18 Computing History Eniac, 1946 (first stored-program computer) Occupied 50x30 feet room, weighted 30 tonnes, contained 18000 electronic valves, consumed 25KW of electrical power; capable to perform 100K calc. per second PlayStation Portable (PSP) Approx. 170 mm (L) x 74 mm (W) x 23 mm (D) Weight: Approx. 260 g (including battery) CPU: PSP CPU (clock frequency 1~333MHz) Main : 32MB Embedded DRAM: 4MB Profile: PSP Game, UMD Audio, UMD Video CPE/EE 421/521 Microcomputers 19 Understanding computers. User perspective Applications: What do we do with them? Price: How much do they cost? To purchase and to operate Convenience: How difficult is to use them? Designer perspective Size: How large are they? (UP) Speed: How many operations? (UP) Power: What is energy consumed? (UP) Complexity: How complex are they to build? CPE/EE 421/521 Microcomputers 20 Alex Milenkovich 5
Engineering Computers Market Implementation Complexity Evaluate Existing Systems for Bottlenecks Benchmarks Technology Trends Implement Next Simulate New Generation System Designs and Organizations Applications Intel: First 30+ Years Intel 4004 November 15, 1971 4-bit ALU, 108 KHz, 2,300 transistors, 10-micron technology Intel Pentium 4 August 27, 2001 32-bit architecture, 1.4 GHz (now 3.08), 42M transistors (now 55+M), 0.18-micron technology (now 0.09) Workloads CPE/EE 421/521 Microcomputers 21 CPE/EE 421/521 Microcomputers 22 Technology Directions: SIA Roadmap Year 1999 2002 2005 2008 2011 2014 Feature size (nm) 180 130 100 70 50 35 Logic trans/cm 2 6.2M 18M 39M 84M 180M 390M Cost/trans (mc) 1.735.580.255.110.049.022 #pads/chip 1867 2553 3492 4776 6532 8935 Clock (MHz) 1250 2100 3500 6000 10000 16900 Chip size (mm 2 ) 340 430 520 620 750 900 Wiring levels 6-7 7 7-8 8-9 9 10 Power supply (V) 1.8 1.5 1.2 0.9 0.6 0.5 High-perf pow (W) 90 130 160 170 175 183 CPE/EE 421/521 Microcomputers 23 Trends & Challenges Processor/memory discrepancy hierarchy On-chip/off-chip memory Microprocessor execution Fetch > Decode > Execute System on a chip - Microcontroller Cost, smaller PCB, reliability, power. Applications Evolution Microprocessor Microprocessor-on-a-chip System-on-a-chip Distributed-system-on-a-chip CPE/EE 421/521 Microcomputers 24 Alex Milenkovich 6
More on Challenges Performance Trends Scalability billions of small devices performance Availability hardware changes system upgrade failures code enhancements Fault tolerance Year Proc. MIPS 1969 4004 0.06 1970 s 808x 0.64 1982 286 1 1985 386 5 1989 486 20 1993 Pentium 100 1996 P II 250 1999 P III 500 2000 P 4 1500 286 386 486 Pentium P II P III P 4 1600 1400 1200 1000 800 600 400 200 0 CPE/EE 421/521 Microcomputers 25 CPE/EE 421/521 Microcomputers 26 Performance Trends Clock Frequency Growth Rate 1,000 P4 Performance 100 10 1 Mainframes Supercomputers Minicomputers Microprocessors Clock rate (MHz) 100 10 1 R10000 Pentium100 i8086 i80286 i80386 i8080 i8008 i4004 0.1 1965 1970 1975 1980 1985 1990 1995 0.1 1970 1975 1980 1985 1990 30% per year 1995 2000 2005 CPE/EE 421/521 Microcomputers 27 CPE/EE 421/521 Microcomputers 28 Alex Milenkovich 7
Transistor Count Growth Rate Transistors 100,000,000 10,000,000 1,000,000 100,000 Moore s Law i80286 R10000 Pentium i80386 R2000 R3000 P4 i8086 10,000 i8008 i8080 i4004 1,000 1970 1980 1990 2000 1975 1985 1995 2005 CPE/EE 421/521 Microcomputers 29 General Technology Trends Microprocessor performance increases 50%-100% per year Transistor count doubles every 3 years DRAM size quadruples every 3 years Huge investment per generation is carried by huge commodity market 180 160 140 120 100 80 60 40 20 0 Sun 4 260 Integer FP MIPS M/120 MIPS M2000 IBM RS6000 540 HP 9000 750 DEC Alpha 1987 1988 1989 1990 1991 1992 CPE/EE 421/521 Microcomputers 30 Storage Divergence between memory capacity and speed more pronounced Capacity increased by 1000x from 1980-95, speed only 2x Gigabit DRAM by c. 2000, but gap with processor speed much greater Larger memories are slower, while processors get faster Need to transfer more data in parallel Need deeper cache hierarchies How to organize caches? Speed Size Registers ns ~KB Cache 10ns ~MB Main memory 100ns ~100MB Hard disk 10ms ~10GB Archive >100ms ~TB CPE/EE 421/521 Microcomputers 31 Instruction Sets Software costs growing faster than hardware costs (1970s) Machine language v.s. HLL Support for high-level languages Gap between high level languages and computer hardware - semantic gap CISC - Complex Instruction Set Architecture Variety of instructions and addressing modes DEC VAX HLLCA - High Level Language Computer Architecture CPE/EE 421/521 Microcomputers 32 Alex Milenkovich 8
RISC Architectures Resolve problems using simpler architecture "The case for the reduced instruction set computers" Patterson & Ditzel [1980] Stanford MIPS (Hennessy, 1981) Commercial processors: MIPS R2000 (1986), IBM RS6000, SPARC, PowerPC, etc. Good design methodology Efficient pipelining and compiler-assisted scheduling of pipeline Make the Common Case Fast favor the frequent case CPE/EE 421/521 Microcomputers 33 Program Execution Time For all instructions in the instruction set T = ni CPIi T i cycle processor cycle time [s] cycles per instruction instruction count CPE/EE 421/521 Microcomputers 34 80x86 Instruction Mix for SPECint92 Programs [PatHen96] Instruction Frequency (%) load 22 cond. branch 20 compare 16 store 12 add 8 and 6 sub 5 mov reg-reg 4 or 1 xor, not, etc. 1 uncond. branch 1 call 1 return, jmp indirect 1 shift 1 42% 70% CPE/EE 421/521 Microcomputers 35 Mem Instruction Execution A=B+C result = op1 OPERATION op2 A+=C ID OF EX ST PC 1000 1000 When f = 5MHz ( 70s) T cycle = 200ns T mem = 200ns When f = 1000MHz ( 90s) T cycle = 1ns T mem = 50ns 100ns 100ns 1ns ADD R1, M(1000) 3 100ns = 300ns 2 1ns = 2ns 1ns 302ns CPE/EE 421/521 Microcomputers 36 t Alex Milenkovich 9
Pipeline INSTR #1 ID OF EX ST time #2 ID OF EX ST #2 ID OF EX #4 ID OF #5 program #1 if( ) #2 #3 #4 ID CPI = 1 #100 CPE/EE 421/521 Microcomputers 37 Alex Milenkovich 10