CPE/EE 42 Microcomputers Instructor: Dr Aleksandar Milenkovic Lecture Notes S0 *Material used is in part developed by Dr. D. Raskovic and Dr. E. Jovanov CPE/EE 42/52 Microcomputers CPE/EE 42 Microcomputers Syllabus textbook & other references grading policy important dates course outline Prerequisites memory organization decoding combinatorial and sequential logic important for system architecture Microcomputer Lab (EB 06) Introduction sessions Lab instructor Class# CPE/EE 42/52 Microcomputers 2 CPE/EE 42 Microcomputers LAB Session on-line LAB manual Access cards Accounts Lab Assistant: Joel Wilder Lab sessions Lab session #: Monday 6:00 8:00 PM Lab session #2: Monday 8:00 0:00 PM Sign-up sheet - if needed CPE/EE 42/52 Microcomputers 3 Alex Milenkovich
Microcomputer Stand alone system based on a microprocessor An embedded system dedicated to a specific application control system/monitoring system optimization for a single function (system resources, extension, ) block diagram inputs processing outputs Number of microprocessors in our environment? CPE/EE 42/52 Microcomputers 4 System Block Diagram t, states A/D µp system D/A Input Processing Output Temperature sensor control signals µp 78 º INPUT PROCESSING OUTPUT CPE/EE 42/52 Microcomputers 5 CPE/EE 42/52 Microcomputers 6 Alex Milenkovich 2
Microprocessor System Architecture System Architecture Single Board Computers (SBC) block diagram (modules, cards) System bus Multibus, VME, ISA, PCI, Multiple masters CPU Clock and CPU Control Circuits MHz - GHz power-up and reset circuits Address Decoder Address and Data Bus Buffers Bus Arbitration Control management CPE/EE 42/52 Microcomputers 7 Microprocessor System Architecture #2 Module Virtual memory / Physical memory ROM, RAM, video memory static/dynamic Peripheral Module serial interface RS232 (CRT, mouse), USB, Firewire (IEEE 394) parallel interface printer interface timer time/frequency measurement CPE/EE 42/52 Microcomputers 8 Microprocessor System Architecture #3 PC architecture CPU PCI ISA CPE/EE 42/52 Microcomputers 9 Alex Milenkovich 3
Block Diagram of a personal computer CPE/EE 42/52 Microcomputers 0 Todd D. Morton Embedded Microcontrollers Copyright 200 by Prentice-Hall Inc. A Typical Small Embedded System Digital Thermometer CPE/EE 42/52 Microcomputers Todd D. Morton Embedded Microcontrollers Copyright 200 by Prentice-Hall Inc. A Microcontroller-Based System CPE/EE 42/52 Microcomputers 2 Alex Milenkovich 4
LCD Adj. Vol. Regul. RS232 RS232 controller Analog I/O 2-axes joystick LEDs Switches Keypad Thermistor A Microcontroller-Based System µc CPE/EE 42/52 Microcomputers 3 Wireless Body Area Network ECG & tilt sensor PPG & movement sensor Wireless gateway & temperature/ humidity sensor Body Area Network Movement sensors ZigBee or custom wireless Personal Server GPRS Internet Emergency Server Medical Server (Mayo Clinic) Physician s Server CPE/EE 42/52 Microcomputers 4 Conventional Computer Architecture 0 2 3 Wbits Von Neumann Architecture Read/Write PE (Processing Element) Control Unit control data ALU N I/O (peripherals) log 2 N CPE/EE 42/52 Microcomputers 5 Alex Milenkovich 5
Microprocessors - History Implementations size (room, cabinet, desktop, handheld, ) speed (doubling 8-20 months) power consumption Von Neumann Architecture Processing Elements sequential execution Read/Write linear array of fixed size cells Data and instruction store I/O unit Address/Data/Control bus CPE/EE 42/52 Microcomputers 6 Intel: First 30+ Years Intel 4004 November 5, 97 4-bit ALU, 08 KHz, 2,300 transistors, 0-micron technology Intel Pentium 4 August 27, 200 32-bit architecture,.4 GHz (now 3.08), 42M transistors (now 55+M), 0.8-micron technology (now 0.09) CPE/EE 42/52 Microcomputers 7 Technology Directions: SIA Roadmap Year 999 2002 2005 2008 20 204 Feature size (nm) 80 30 00 70 50 35 Logic trans/cm 2 6.2M 8M 39M 84M 80M 390M Cost/trans (mc).735.580.255.0.049.022 #pads/chip 867 2553 3492 4776 6532 8935 Clock (MHz) 250 200 3500 6000 0000 6900 Chip size (mm 2 ) 340 430 520 620 750 900 Wiring levels 6-7 7 7-8 8-9 9 0 Power supply (V).8.5.2 0.9 0.6 0.5 High-perf pow (W) 90 30 60 70 75 83 CPE/EE 42/52 Microcomputers 8 Alex Milenkovich 6
History #2 Von Neumann Architecture Read/Write data PE (Processing Element) Harvard Architecture Program Data data data PE (Processing Element) CPE/EE 42/52 Microcomputers 9 History #3 Processor/memory discrepancy hierarchy On-chip/off-chip memory Microprocessor execution Fetch > Decode > Execute System on a chip - Microcontroller Cost, smaller PCB, reliability, power. Applications Evolution Microprocessor Microprocessor-on-a-chip System-on-a-chip Distributed-system-on-a-chip CPE/EE 42/52 Microcomputers 20 History #4 Challenges scalability billions of small devices performance availability hardware changes system upgrade failures code enhancements fault tolerance CPE/EE 42/52 Microcomputers 2 Alex Milenkovich 7
History #5 Year Processor MIPS 969 4004 0.06 970 s 808x 0.64 982 286 985 386 5 989 486 20 993 Pentium 00 996 P II 250 999 P III 500 2000 P 4 500 600 400 200 000 800 600 400 200 286 386 486 Pentium P II P III P 4 0 CPE/EE 42/52 Microcomputers 22 00 Technology Trends Supercomputers 0 Performance Mainframes Minicomputers Microprocessors 0. 965 970 975 980 985 990 995 The natural building block for multiprocessors is now also about the fastest! CPE/EE 42/52 Microcomputers 23 Clock Frequency Growth Rate,000 P4 Clock rate (MHz) 00 0 R0000 Pentium00 i8086 i80286 i80386 i8080 i8008 i4004 0. 970 975 980 985 990 995 2000 2005 30% per year CPE/EE 42/52 Microcomputers 24 Alex Milenkovich 8
Transistors Transistor Count Growth Rate 00,000,000 0,000,000,000,000 00,000 i80286 R0000 Pentium i80386 R2000 R3000 P4 i8086 0,000 i8008 i8080 i4004,000 970 980 990 2000 975 985 995 2005 00 million transistors on chip by early 2000 s A.D. Transistor count grows much faster than clock rate 40% per year, order of magnitude more contribution in 2 decades CPE/EE 42/52 Microcomputers 25 General Technology Trends Microprocessor performance increases 50%-00% per year Transistor count doubles every 3 years DRAM size quadruples every 3 years Huge investment per generation is carried by huge commodity market 80 60 40 20 00 80 60 40 20 0 Sun 4 260 Integer FP MIPS M/20 MIPS M2000 IBM RS6000 540 HP 9000 750 DEC Alpha 987 988 989 990 99 992 CPE/EE 42/52 Microcomputers 26 Conventional Computer Architecture 0 2 3 Wbits Von Neumann Architecture Read/Write PE (Processing Element) Control Unit control data ALU N I/O (peripherals) log 2 N CPE/EE 42/52 Microcomputers 27 Alex Milenkovich 9
Storage Divergence between memory capacity and speed more pronounced Capacity increased by 000x from 980-95, speed only 2x Gigabit DRAM by c. 2000, but gap with processor speed much greater Larger memories are slower, while processors get faster Need to transfer more data in parallel Need deeper cache hierarchies How to organize caches? Speed Size Registers ns ~KB Cache 0ns ~MB Main memory 00ns ~00MB Hard disk 0ms ~0GB Archive >00ms ~TB CPE/EE 42/52 Microcomputers 28 Instruction Sets Software costs growing faster than hardware costs (970s) Machine language v.s. HLL Support for high-level languages Gap between high level languages and computer hardware - semantic gap CISC - Complex Instruction Set Architecture Variety of instructions and ing modes DEC VAX HLLCA - High Level Language Computer Architecture CPE/EE 42/52 Microcomputers 29 RISC Architectures Resolve problems using simpler architecture "The case for the reduced instruction set computers" Patterson & Ditzel [980] Stanford MIPS (Hennessy, 98) Commercial processors: MIPS R2000 (986), IBM RS6000, SPARC, PowerPC, etc. Good design methodology Efficient pipelining and compiler-assisted scheduling of pipeline Make the Common Case Fast favor the frequent case CPE/EE 42/52 Microcomputers 30 Alex Milenkovich 0
Program execution time: For all instructions in the instruction set RISC Methodology T = ni CPIi T i cycle processor cycle time [s] cycles per instruction instruction count CPE/EE 42/52 Microcomputers 3 80x86 Instruction Mix for SPECint92 Programs [PatHen96] Instruction Frequency (%) load 22 cond. branch 20 compare 6 store 2 add 8 and 6 sub 5 mov reg-reg 4 or xor, not, etc. uncond. branch call return, jmp indirect shift 42% 70% CPE/EE 42/52 Microcomputers 32 Instruction Execution A=B+C A+=C result = op OPERATION op2 ADD R, M(000) IF ID OF EX ST IF Mem PC 000 000 t When f = 5MHz ( 70s) T cycle = 200ns T mem = 200ns When f = 000MHz ( 90s) T cycle = ns T mem = 50ns 00ns 00ns ns ns 3 00ns = 300ns 2 ns = 2ns 302ns CPE/EE 42/52 Microcomputers 33 Alex Milenkovich
INSTR # IF ID Pipeline OF EX ST IF time #2 IF ID OF EX ST #2 IF ID OF EX #4 IF ID OF #5 IF ID program # CPI = if( ) #2 #3 #4 #00 CPE/EE 42/52 Microcomputers 34 0 WBytes System System memory Word Byte 2 3 log 2 N log 2 W N Example: 2 banks, 32 KW each, 4-byte words 0 2 28 KB (32K*4B) 28 KB Bank A3 Select A7 A6 Word A2 A A0 Byte log 2 B= log 2 32K=5 log 2 4=2 CPE/EE 42/52 Microcomputers 35 Alex Milenkovich 2