TKT-3500 Microcontroller systems

TKT-3500 Microcontroller systems Lec 2 PIC18LF8722 Microcontroller s core Teemu Laukkarinen Department of Computer Systems Tampere University of Technology Fall 2011 Copyright Tampere University of Technology Department of Computer Systems

Copyright notice Original slides by Erno Salminen Some figures by Robert Reese, from supplementary CD of the course book from PIC18F8722 Family Data Sheet, Microchip Technology Inc. Thanks to Juha Onkila, Teemu Laukkarinen Copyright Tampere University of Technology Department of Computer Systems

Last week Microcontrollers integrate many units into same chip processor, memories, timers, IO devices, AD converters... Often used in embedded systems that sense environment and control other devices Modest performance, cheap price, high volume Programmability allows fast development and upgrading Brief introduction to exercise platform TUTWSN node with PIC + multiple sensors Copyright Tampere University of Technology Department of Computer Systems

Reminder: PIC18LF8722 8 bit RISC microcontroller with Harvard architecture High End 8-bit microcontroller Accumulator Assembly programming complicated 128 kb program memory, 4 kb SRAM, 1kB EEPROM Operating voltage: 2.0 5.5 V Max. Power dissipation 1 W Min. Power dissipation (@1 Mhz): 3 mw Image: www.futurlec.com Compare: Normal red led 2V and max 20 ma Copyright Tampere University of Technology Department of Computer Systems

Reminder: PIC18LF8722 (2) Plenty of peripherals SPI, I2C, USART 16 channel 10-bit AD-converter 5 timers and capture/compare/pwm module HW 8-bit multiplier Watchdog, Brown-out Max. Frequency: 40 Mhz Many power management modes Clock sources on platform: Low frequency external clock Internal clock Copyright Tampere University of Technology Department of Computer Systems

80-pin TQFP package Many pins have multiple functions For example 8 Vdd or Vss (GND) pins (for logic and I/O) AVdd and Avss (for analog modules) 20 Address and data pins for external memory 4 Ext. Interrupt pins 2 Prim. oscillator pins Most of above usable also as GPIO pins up to 70 GPIO-pins Copyright Tampere University of Technology Department of Computer Systems

control PIC Microarchitecture Defines the internal structure: mem mem data path control data path internal memories peripherals peripherals input/output ports Their type, count, widths, connections I/O ports #7/44 Copyright Tampere University of Technology Department of Computer Systems

PIC18 Data path Data path to/from data mem instruction register (IR) #8/44 Copyright Tampere University of Technology Department of Computer Systems Image: www.microchip.com to/from peripherals

PIC18 data path W = work register, i.e. accumulator Basic case: operands come from W and data memory and result goes W Result often overwrites one of the operands 8-bit operands instruction register (IR) Data path to/from data mem #9/44 Copyright Tampere University of Technology Department of Computer Systems to/from peripherals

Configuration bits The configuration bits select various device configurations Oscillators, bus and mem modes, code protection They are either programmed (read as 0 ) left unprogrammed (read as 1 ) These bits are mapped starting at program memory location 300000h configuration memory space (300000h-3FFFFFh) is beyond the user program memory space can only be accessed using table reads and table writes Copyright Tampere University of Technology Department of Computer Systems

Configuration bits (2) Programming the Configuration registers is done in a manner similar to programming the Flash memory. 12 configuration and 2 device ID registers Configured properties oscillator and clock brown-out and power-up watchdog CPU and bus modes master clear, timer+ccp miscellaneous code protection code protection write protection write protection table read protection table read protection device id (read-only) Copyright Tampere University of Technology Department of Computer Systems

Configuration bits (3) PIC:n konfiguraatiobittejä voi asettaa C - koodissa #pragma config KONFFATTAVAN_BITIN_NIMI = arvo esim. #pragma config WDT = ON #pragma config WDTPS=128 asettavat WatchDogTimerin päälle 1:128 jakajalla. Copyright Tampere University of Technology Department of Computer Systems

Operand storage No general purpose registers in PIC18 Data SRAM used instead Different scheme from many CPUs Data memory accesses are banked because 16-bit instruction can hold only a small address (8b) Hence, each bank contains 2 8 =256 bytes Hence, 4 KB RAM has 16 banks (0 to 15) 4 bits are needed for 16 banks One byte of a bank is called file register, f #13/44 Copyright Tampere University of Technology Department of Computer Systems

Banked access: Bank selection File register, f is a SRAM location corresponds to a general-purpose register of other CPU architectures SRAM contains SFRs (Special Function Registers) and GPRs (General purpose Registers) Banking only for data memory A special register defines which bank is used. Three choices 1. BSR = bank selection register 2. FSR = file selection reg (for pointers) 3. Access bank = fast access to ctrl registers and temporary / often used user data: 00-5F In Bank 0 and, 60-FF in Bank 15 (aka. SFRs) These registers are updated with move instructions #14/44 Copyright Tampere University of Technology Department of Computer Systems

Banked data memory access Op.code defines how to form the SRAM address: a) BSR + 8-bit address b) whole 12 bit address in FSRx c) Access bank + 8 bit address 8-bit address comes from IR (instr. reg.) table latch data bus ROM latch instruction register (IR) #15/44 Copyright Tampere University of Technology Department of Computer Systems

Banked memory access (2) Address is simply concatenated from two parts BSR is one example of special function register (SFR) In contrast to general purpose register, i.e. file register #16/44 Copyright Tampere University of Technology Department of Computer Systems

In-Direct accessing Means that a pointer is used to access data Addr not defined in the instruction Instruction defines the register that contains the address pointer registers FSR0, FSR1 and FSR2 These are also special function registers In many CPUs, any register can be used for in-direct accesses Increment/decrement instructions can be used #17/44 Copyright Tampere University of Technology Department of Computer Systems

Special function registers, memory map #18/44 Copyright Tampere University of Technology Department of Computer Systems

Special function register Special Function Registers (SFR) are addressed like normal data memory locations but have specified functionality tied to hardware subsystems in the processor They control and report the state of microcontroller and it s peripherals Status regs/bits cannot be written In PIC18LF8722, there are 160 SFRs, located in Bank15 #19/44 Copyright Tampere University of Technology Department of Computer Systems

Special function register (2) Purposes: Program counter Interrupts Stack Memory-related: BSR, FSR0/1/2, EEPROM Digital-IO settings/status for ports A,B,C,D Status of arithmetic operations Peripherals: Timers, Serial IO, PWM.. Typically referred to by their name (BSR, W0, T3CON, STATUS, etc) with macros (Assembly or C) instead of address #20/44 Copyright Tampere University of Technology Department of Computer Systems

SFR example: Arithmetic op status STATUS Address 0xFD8 in bank15 5 bits are used [4] Negative [3] Overflow [2] Zero [1] Carry from 4th bit [0] Carry from MSbit #21/44 Copyright Tampere University of Technology Department of Computer Systems

SFR example2: Timer 0 control T0CON Address 0xFD5 of bank15 8 bits used: [7] ON/OFF [6] 8b/16b [5] Clk src [4] pos/neg edge [3:0] Clk scaling #22/44 Copyright Tampere University of Technology Department of Computer Systems

Access bank Register Access Bank selects 96 lowest bytes of Bank0 and all 160 SFRs Fast access to SFR without modifying BSR Whole memory could be reached via BSR Assembly instruction s operand is either BANKED = uses BSR, for regular data ACCESS = uses access bank, for SFR #23/44 Copyright Tampere University of Technology Department of Computer Systems

Data memory map in PIC18 a) general-purpose regs (GPR, aka. file registers) for variables b) special function regs (SFR) for control/status Addressable contents with access bank 0x59 0x60 #24/44 Copyright Tampere University of Technology Department of Computer Systems

PIC18 Program memory map 21b address bus Space 0x0 0x1FFFF 131 072 locations 128 K locations K = 2 10 = 1024 Reset and interrupt vectors contain addresses of special functions The return addresses of function calls reside special stack regs program counter #25/44 Copyright Tampere University of Technology Department of Computer Systems

variables (data) code rst vector Address space vs. memories Address width defines the address space i.e. how many addresses the CPU can access 8b 2 8 =256 addresses 32b 2 32 = 4G addresses It is mapped to memory banks Each physical mem component implements part of the addr space Note that addr width may be different from data width #26/44 Copyright Tampere University of Technology Department of Computer Systems Address space 0x0 The data width of a mem location is casedependent (8b, 16b, 32b...) Mapping Physical memory banks separate memories single memory Option A (blue) Option B (red) Option C...

External memory interface For cases where 128 Kbytes of program memory is inadequate for an application Allows the controller s internal program counter to address a memory space of up to 2 Mbytes ( 21-bit addresses, 2 21 2M Larger level of data access than most 8-bit devices E.g. offers the possibility to 1. Operate entirely from external memory 2. Use combinations of on-chip and external memory, up to the 2-Mbyte limit 3. Use external Flash memory for reprogrammable application code or large data tables 4. Use external RAM devices for storing large amounts of variable data #27/44 Copyright Tampere University of Technology Department of Computer Systems

Program memory configurations #28/44 Copyright Tampere University of Technology Department of Computer Systems

PIC machine language and assembly #29/44 Copyright Tampere University of Technology Department of Computer Systems

Instruction Cycle PIC18 is pipelined so that 1. fetch takes one instruction cycle, while the 2. decode and execute take another instruction cycle. each instruction effectively executes in one cycle. Changes to PC (e.g., GOTO), require two cycles to complete #30/44 Copyright Tampere University of Technology Department of Computer Systems

Instruction Cycle (2) Consists of four Q cycles: Q1-Q4 A fetch cycle begins with incrementing PC in Q1 In the execution cycle, Q1: the fetched instruction is latched into the Instruction Register (IR) Q2,Q3,Q4: This instruction is then decoded and executed Data memory is read during Q2 and written during Q4 #31/44 Copyright Tampere University of Technology Department of Computer Systems

Storage of instructions Program memory is addressed in bytes Instructions are stored as 2 bytes or 4 bytes in prog. memory The Least Significant Byte of an instruction word is always stored at an even address (LSb = 0) PC increments in steps of 2 Branch instructions take two program words absolute program memory address embedded into the instruction (CALL, GOTO) relative address (BNZ) #32/44 Copyright Tampere University of Technology Department of Computer Systems

PIC18 Assembly 16 bit program word in most cases Some instructions need two words 75 standard (PIC18) +8 extended instructions but they cannot be used on this course due to limitations of student version compiler 5 types of operations 1. Byte-oriented 31 instr. 2. Bit-oriented 5 instr. 3. Literal (immediate data) operations 10 instr. 4. Control operations - 23 instr. 5. (Mem read/write 8 instr.) #33/44 Copyright Tampere University of Technology Department of Computer Systems

Assembly 1- Byte-oriented operations Typically 3 operands ADDWF f,d,a Add-W-to-F, f=file register, d=destination (WREG or f) ADDWF 0x20, 0, 0 adds (implicit) WREG to contents of RAM location 0x20 (f) Result stored into register W (d=0, d=1 vise versa) and Access bank (a=0, a=1 for BSR) is used Probably most used instruction type Accumulator machine lots of traffic between WREG and SRAM #34/44 Copyright Tampere University of Technology Department of Computer Systems

Assembly 2 - Bit-oriented operations Three operands, b= bit in file register BCF f,b,a Bit-Clear-in-Filereg, f=file register, b=index of affected bit, a=accessed memory bank BCF 0x20, 7, 0 clears bit 7 in file register 0x20 cleared. Access bank is used #35/44 Copyright Tampere University of Technology Department of Computer Systems

Assembly 3 - Literal operations Typically 1 operand; the literal (or immediate data aka. data stored to the instruction code) ADDLW k Add-Literal-to-W, literal k=8,12 or 20 bit value ADDLW 12 adds WREG and number 12 together. Value is stored to WREG. Operand k (in this example 12) has to be between 0 and 256 #36/44 Copyright Tampere University of Technology Department of Computer Systems

Assembly 4 - Control operations Typically 1 operand BNZ n Brach-if-Zot-Zero, n=relative address BNZ 200 moves execution to program memory address 200 if the zero bit in status register is zero #37/44 Copyright Tampere University of Technology Department of Computer Systems

Assembly 5 Read/write operations Typically no operands TBLRD TBLWT TBLRD reads from program memory location into SFR called table latch (TABLAT) Often used for static strings, which are stored to the program memory and need to be written to SFRs (for example USART TX) The Flash program memory and data EEPROM are readable, writable and erasable during normal operation #38/44 Copyright Tampere University of Technology Department of Computer Systems

General instruction formats 1a. 1b. 4. 2. 3. #39/44 Copyright Tampere University of Technology Department of Computer Systems

Conclusions PIC is somewhat un-orthodox CPU architecture, e.g. Accumulator Use of SRAM as registers Special registers for in-direct addressing Several Special function registers Some of these issues can be neglected with high-level languages However, they are necessary to understand some forthcoming examples Most examples will be generalized and not PIC-specific #40/44 Copyright Tampere University of Technology Department of Computer Systems

Compare to AVR #41/44 Copyright Tampere University of Technology Department of Computer Systems

Compare PIC18 with ATMEGA128 #42/44 8-bit Harvard architecture with RISC instruction set, Program word 16 bits, max. 16 MIPS 128 kb PM, 4kB SRAM and EEPROM 32 General purpose registers 133 Instructions 53 GPIO-lines 4 Timers with compare/pwm SPI, i2c, 2*USART 8 channel 10 bit ADC JTAG Interface Copyright Tampere University of Technology Department of Computer Systems

Simplified AVR block diagram AVR may stand for a) Advanced Virtual RISC b) Alf and Vegard's RISC c) something completely different Image:www.atmel.com #43/44 Copyright Tampere University of Technology Department of Computer Systems

ASM comparison Add constants 2 and 3, store result in Access Bank s file register 20 (or register number 20) PIC AVR #44/44 Copyright Tampere University of Technology Department of Computer Systems