CS 471 Operating Systems Yue Cheng George Mason University Fall 2017
Review: Segmentation 2
Virtual Memory Accesses o Approaches: Static Relocation Dynamic Relocation Base Base-and-Bounds Segmentation 3
Virtual Memory Accesses o Approaches: Static Relocation: requires rewrite for the same code Dynamic Relocation Base: add a base to virtual address to get physical address Base-and-Bounds: checks physical address is in range Segmentation: many base+bounds pairs 4
Virtual Memory Accesses o Approaches: Static Relocation: requires rewrite for the same code Dynamic Relocation Base: add a base to virtual address to get physical address Base-and-Bounds: checks physical address is in range Segmentation: many base+bounds pairs 5
Segmentation Example o Assume a 10-bit virtual address space With the high 2-bit indicating the segment o Assume 0 => code+data 1 => heap 2 => stack 6
Segmentation Example 0x000 Virtual 0x100 0x200 0x300 7
Segmentation Example 0x000 Virtual Code 0x100 Heap 0x200 0x300 Stack 8
Segmentation Example 0x000 Virtual Code 0x100 Heap 0x200 0x300 Stack base bounds code?? heap?? stack?? 9
Segmentation Example 0x000 Virtual Code 0x100 Heap 0x200 0x300 Stack base bounds code? 0x40 heap? 0xC0 stack? 0x80 10
Segmentation Example 0x000 Virtual Code Physical Heap 0x000 0x100 Code 0x400 Heap Stack 0x800 0x200 0x300 Stack base bounds code 0x400 0x40 heap 0 0xC0 stack 0x800 0x80 11
Segmentation Example 0x000 Virtual Code Physical Heap 0x000 0x100 Code 0x400 Heap Stack 0x800 0x200 0x300 Stack base bounds code 0x400 0x40 heap 0 0xC0 stack 0x800 0x80 12
Segmentation Example 0x000 Virtual Code Physical Heap 0x000 0x100 Code 0x400 Heap Stack 0x800 0x200 0x300 Stack base bounds code 0x400 0x40 heap 0 0xC0 stack 0x800 0x80 Most segments: phys = virt_offset + base 13
Segmentation Example 0x000 Virtual Code Physical Heap 0x000 0x100 Code 0x400 0x180 Heap Stack 0x800 0x200 0x300 Stack base bounds code 0x400 0x40 heap 0 0xC0 stack 0x800 0x80 Most segments: phys = virt_offset + base 14
Segmentation Example 0x000 Virtual Code Physical Heap 0x000 0x100 Code 0x400 0x180 Heap Stack 0x800 0x200 0x300 Stack base bounds code 0x400 0x40 heap 0 0xC0 stack 0x800 0x80 Most segments: phys = 0x80 + base 15
Segmentation Example 0x000 Virtual Code Physical Heap 0x000 0x100 Code 0x400 0x180 Heap Stack 0x800 0x200 0x300 Stack base bounds code 0x400 0x40 heap 0 0xC0 stack 0x800 0x80 Most segments: phys = 0x80 + base 16
Segmentation Example 0x000 Virtual Code Physical Heap 0x000 0x100 Code 0x400 0x180 Heap Stack 0x800 0x200 0x300 Stack base bounds code 0x400 0x40 heap 0 0xC0 stack 0x800 0x80 Most segments: phys = 0x80 + 0 17
Segmentation Example 0x000 Virtual Code Physical Heap 0x000 0x100 Code 0x400 0x180 Heap Stack 0x800 0x200 0x300 Stack base bounds code 0x400 0x40 heap 0 0xC0 stack 0x800 0x80 Most segments: phys = 0x80 + 0 = 0x80 18
Segmentation Example 0x000 Virtual Code Physical Heap 0x000 0x100 Code 0x400 Heap Stack 0x800 0x200 0x300 Stack base bounds code 0x400 0x40 heap 0 0xC0 stack 0x800 0x80 What if heap needs to grow? 19
Segmentation Example 0x000 Virtual Code Physical Heap 0x000 0x100 Code Heap Stack 0x800 0x200 Copy 0x300 Stack base bounds code 0x400 0x40 heap 0 0xC0 stack 0x800 0x80 What if heap needs to grow? 20
Segmentation Example 0x000 Virtual Code Physical Heap 0x000 0x100 Heap Stack 0x800 0x200 Code 0x300 Stack base bounds code 0x400 0x40 heap 0 0xC0 stack 0x800 0x80 What if heap needs to grow? 21
Segmentation Example 0x000 Virtual Code Physical Heap 0x000 0x100 Heap Stack 0x800 0x200 Code 0xC00 0x300 Stack base bounds code 0xC00 0x40 heap 0 0xC0 stack 0x800 0x80 What if heap needs to grow? 22
Segmentation Example 0x000 Virtual Code Physical 0x000 Heap 0x100 Heap Stack 0x800 0x200 Code 0xC00 0x300 Stack base bounds code 0xC00 0x40 heap 0 0x100 stack 0x800 0x80 What if heap needs to grow? 23
Segmentation Example 0x000 Virtual Code Physical 0x000 Heap 0x100 Heap Stack 0x800 0x200 Code 0xC00 0x300 Stack base bounds code 0xC00 0x40 heap 0 0x100 stack 0x800 0x80 dilemma: must (a) waste space or (b) waste time 24
Issues: External Fragmentation o As processes are loaded and removed from the main memory, the free memory is broken into small pieces Hole: block of available memory; holes of various size are scattered throughout memory o A new allocation request may have to be denied When there is no contiguous free memory with requested size The total free memory space may be much larger than the requested size! Hole Hole Hole 25
Memory Compaction o Reduce external fragmentation by copy+compaction Shuffle memory contents to place all free memory together in one large block Compaction is possible only if relocation is dynamic, and is done at execution time Must be careful about pending I/O before initiating compaction Problems Too much perf overhead 26
Paging 27
Paging o Motivation: Segmentation is too coarse-grained Either waste space (external fragmentation) or copy memory often (compaction) o We need a finer-grained alternative! 28
Paging Scheme o A memory management scheme that allows the physical address space of a process to be noncontiguous o Divide physical memory into fixed-sized blocks called frames o Divide logical memory into blocks of same size called pages o Flexible mapping: Any page can go to any free frame o Scalability: To run a program of size n pages, need to find n free frames and load program Grow memory segments wherever we please! 29
A Simple Example page 0 page 1 page 2 An 8-frame physical memory (128B) page 3 Program s Virt Addr Space Each page is of 16B 30
A Simple Example page 0 page 1 page 2 An 8-frame physical memory (128B) page 3 Program s Virt Addr Space Each page is of 16B Virtual page # Physical frame # 31
Addressing Basics o For segmentation High bits => segment # Low bits => offset VPN offset o For paging High bits => page # Low bits => offset VA4 VA3 VA2 VA1 VA0 Q: How many offset bits do we need? A: log(page_size) 32
Address Examples Page size Low bits (offset) 16 Bytes 33
Address Examples Page size Low bits (offset) 16 Bytes 4 34
Address Examples Page size Low bits (offset) 16 Bytes 4 2 KB 35
Address Examples Page size Low bits (offset) 16 Bytes 4 2 KB 11 36
Address Examples Page size Low bits (offset) 16 Bytes 4 2 KB 11 4 MB 37
Address Examples Page size Low bits (offset) 16 Bytes 4 2 KB 11 4 MB 22 38
Address Examples Page size Low bits (offset) 16 Bytes 4 2 KB 11 4 MB 22 256 Bytes 39
Address Examples Page size Low bits (offset) 16 Bytes 4 2 KB 11 4 MB 22 256 Bytes 8 40
Address Examples Page size Low bits (offset) 16 Bytes 4 2 KB 11 4 MB 22 256 Bytes 8 16 KB 41
Address Examples Page size Low bits (offset) 16 Bytes 4 2 KB 11 4 MB 22 256 Bytes 8 16 KB 14 42
Address Examples Page size Low bits (offset) Virt Addr Bits High bits (vpn) 16 Bytes 4 10 2 KB 11 20 4 MB 22 32 256 Bytes 8 16 16 KB 14 64 43
Address Examples Page size Low bits (offset) Virt Addr Bits High bits (vpn) 16 Bytes 4 10 6 2 KB 11 20 4 MB 22 32 256 Bytes 8 16 16 KB 14 64 44
Address Examples Page size Low bits (offset) Virt Addr Bits High bits (vpn) 16 Bytes 4 10 6 2 KB 11 20 9 4 MB 22 32 256 Bytes 8 16 16 KB 14 64 45
Address Examples Page size Low bits (offset) Virt Addr Bits High bits (vpn) 16 Bytes 4 10 6 2 KB 11 20 9 4 MB 22 32 10 256 Bytes 8 16 16 KB 14 64 46
Address Examples Page size Low bits (offset) Virt Addr Bits High bits (vpn) 16 Bytes 4 10 6 2 KB 11 20 9 4 MB 22 32 10 256 Bytes 8 16 8 16 KB 14 64 47
Address Examples Page size Low bits (offset) Virt Addr Bits High bits (vpn) 16 Bytes 4 10 6 2 KB 11 20 9 4 MB 22 32 10 256 Bytes 8 16 8 16 KB 14 64 50 48
Address Examples Page size Low bits (offset) Virt Addr Bits High bits (vpn) Virt pages 16 Bytes 4 10 6 2 KB 11 20 9 4 MB 22 32 10 256 Bytes 8 16 8 16 KB 14 64 50 49
Address Examples Page size Low bits (offset) Virt Addr Bits High bits (vpn) Virt pages 16 Bytes 4 10 6 64 2 KB 11 20 9 512 4 MB 22 32 10 1K 256 Bytes 8 16 8 256 16 KB 14 64 50 2 50 50
Address Examples Page size Low bits (offset) Virt Addr Bits High bits (vpn) Virt pages 16 Bytes 4 10 6 64 2 KB 11 20 9 512 4 MB 22 32 10 1K 256 Bytes 8 16 8 256 16 KB 14 64 50 2 50 Note: high bits for physical frames may be different! 51
Question: An x86_64 Linux OS with 4KB page size. How many pages can we have assuming the maximum memory limit? 52
Virtual => Physical Addr Mapping o We need a general mapping mechanism o What data structure is good? Big array VPN offset 0 1 0 0 1 0 1 Addr mapper 0 1 0 1 0 1 PFN offset 53
Virtual => Physical Addr Mapping o We need a general mapping mechanism o What data structure is good? Big array (aka linear page table) VPN offset 0 1 0 0 1 0 1 Addr mapper 0 1 0 1 0 1 PFN offset 54
Mapping Example P1 P2 Virtual mem Phys mem 55
Mapping Example P1 P2 Virtual mem Phys mem 56
Mapping Example P1 P2 Virtual mem Phys mem 57
Mapping Example P1 P2 Virtual mem Phys mem 58
Mapping Example P1 P2 Virtual mem Phys mem 0 1 2 3 4 5 6 7 P1 P2 0 2 0 5 Page tables 1 2 7 0 1 2 1 3 3 4 3 6 59
Page Table o A per-process data structure used to keep track of virtual page to physical frame mapping o Major role: store address translation 60
Address Translation Scheme o Observe: The simple limit/relocation register pair mechanism is no longer sufficient o m-bit virtual address generated by CPU is divided into: Virtual Page number (p) used as an index into a page table which contains base address of each page in physical memory Page offset (d) combined with base address to define the physical memory address that is sent to the memory unit 61
Address Translation Architecture f logical address physical address f0000 0000 CPU p d f d f1111 1111 p f page table physical memory 62
Free Frames Before allocation After allocation 63
Free Frames Before allocation After allocation 64
More on Page Table o The page table data structure is kept in main memory o Each page table entry (PTE) holds <physical translation + other info> o Page-table base register (PTBR) points to the page table E.g., CR3 on x86 o Page-table length register (PTLR), if it exists, indicates the size of the page table 65
Page Table Entry (PTE) o The simplest form of a page table is a linear page table Array data structure OS indexes the array by virtual page number (VPN) To find the desired physical frame number (PFN) An 32-bit x86 page table entry (PTE) Important page status info 66
Paging Problems o Page tables are too slow (today) o Page tables are too big (next lecture) 67
Address Translation Steps o Hardware: for each memory reference 1. Extract VPN (virt page num) from VA (virt addr) 2. Calculate addr of PTE (page table entry) 3. Fetch PTE 4. Extract PFN (phys page frame num) 5. Build PA (phys addr) 6. Fetch PA to register o Q: Which steps are expensive?? 68
Address Translation Steps cheap cheap expensive cheap cheap expensive o Hardware: for each memory reference 1. Extract VPN (virt page num) from VA (virt addr) 2. Calculate addr of PTE (page table entry) 3. Fetch PTE 4. Extract PFN (phys page frame num) 5. Build PA (phys addr) 6. Fetch PA to register o Q: Which steps are expensive?? 69
Address Translation Steps cheap cheap expensive cheap cheap expensive o Hardware: for each memory reference 1. Extract VPN (virt page num) from VA (virt addr) 2. Calculate addr of PTE (page table entry) 3. Fetch PTE 4. Extract PFN (phys page frame num) 5. Build PA (phys addr) 6. Fetch PA to register o Q: Which expensive steps can we avoid?? 70
Array Iterator o A simple code snippet in array.c int sum = 0; for (i=0; i<n; i++) { sum += a[i]; } o Compile it using gcc o Dump the assembly code objdump (Linux) or otool (Mac) 71
Trace the Memory Accesses Virt load 0x3000 load 0x3004 load 0x3008 load 0x300C 72
Trace the Memory Accesses Virt load 0x3000 load 0x3004 load 0x3008 load 0x300C Phys load 0x100C load 0x7000 load 0x100C load 0x7004 load 0x100C load 0x7008 load 0x100C load 0x700C 73
Trace the Memory Accesses Virt load 0x3000 load 0x3004 load 0x3008 load 0x300C Phys load 0x100C load 0x7000 load 0x100C load 0x7004 load 0x100C load 0x7008 load 0x100C load 0x700C 1 st mem access: Fetch PTE 74
Trace the Memory Accesses Virt load 0x3000 load 0x3004 load 0x3008 load 0x300C Phys load 0x100C load 0x7000 load 0x100C load 0x7004 load 0x100C load 0x7008 load 0x100C load 0x700C Map VPN to PFN: 3 -> 7 75
Trace the Memory Accesses Virt load 0x3000 load 0x3004 load 0x3008 load 0x300C Phys load 0x100C load 0x7000 load 0x100C load 0x7004 load 0x100C load 0x7008 load 0x100C load 0x700C 2 nd mem access: access a[i] 76
Trace the Memory Accesses Virt load 0x3000 load 0x3004 load 0x3008 load 0x300C Phys load 0x100C load 0x7000 load 0x100C load 0x7004 load 0x100C load 0x7008 load 0x100C load 0x700C Note: 1. Each virt mem access -> two phys mem accesses 2. Repeated memory accesses! 77