AN562 PCI EXPRESS 3.1 JITTER REQUIREMENTS 1. Introduction PCI Express () is a serial point-to-point interconnect standard developed by the Peripheral Component Interconnect Special Interest Group (PCI-SIG). Although originally targeted at desktop personal computers, has been broadly adopted in many applications including blade servers, storage, embedded computing and communication networks because of its widespread use, low cost, and high data throughput. A key difference between and earlier buses (e.g., PCI/PCI-X) is is based on point-to-point serial links rather than a shared parallel bus architecture. Serial transmission was chosen over traditional parallel transmission because it eliminates the problems associated with timing skew across multiple wires and variable transmission distances. Serial transmission sends both the clock and data on the same wire allowing for scalable transmission rates and reduced complexity and cost. A typical serial architecture is illustrated in Figure 1. CPU CPU Clock PCI/PCI-X Add-In Cards to PCI/PCI-X Bridge Refclk Link Refclk Refclk Root Complex Switch Link Link Memory Endpoint 100 MHz ±300ppm Buffer Refclks Link Legacy Endpoint Link Endpoint Refclk Refclk Refclk Figure 1. Architecture Components The root complex provides a central control point in the tree topology. It manages connectivity for a port, a CPU and associated memory, and other bridging functions. A switch connects multiples endpoints to the root complex. Endpoints are peripheral I/O devices that communicate to the CPU through the switch and/or the root complex. reference clocks (Refclk) provide a stable timing reference for the serial data transmission between two devices. Rev. 0.2 11/15 Copyright 2015 by Silicon Laboratories AN562
AN562 2. PCI Express Link A link is made up of one or more lanes which consists of a transmit and receive differential pair. Support for x1, x2, x4, x8, x12, x16, x32 lanes per link enables a scalable bandwidth to meet the needs of a wide variety of applications. With the introduction of 1.0 in 2003, a lane rate of 2.5 Gbps was defined, which resulted in a data throughput of 500 MBps per lane using 8B/10B encoding (2.5 Gbps 10 bits/byte x 2 directions). In 2007, 2.0 doubled the data throughput by increasing the lane rate to 5.0 Gbps. 3.0 released in 2010 once again doubled the data throughput by increasing the lane rate to 8 Gbps and changing to a more efficient scrambling and encoding scheme (128B/130B). Figure 2 illustrates the flexible data throughput of the link for the three standards. Number of Lanes per Link x1 x2 x4 x8 x12 x16 x32 1.1 500 MBps 1 GBps 2 GBps 4 GBps 6 GBps 8 GBps 16 GBps 2.1 1 GBps 2 GBps 4 GBps 8 GBps 12 GBps 16 GBps 32 GBps 3.1 2 GBps 4 GBps 8 GBps 16 GBps 24 GBps 32 GBps 64 GBps Total Data Throughput per Link Figure 2. Link and Effective Data Throughput 2 Rev. 0.2
AN562 3. Refclk and Clocking Architectures An external clock reference clock (Refclk) is required for transmitting data between two devices. A Refclk frequency of 100 MHz ±300 ppm is specified for all three line rates (2.5 Gbps, 5.0 Gbps, 8.0 Gbps). The burden has been placed on the TX PLL to multiply the 100 MHz Refclk frequency to the desired data rate. Although the Refclk frequency has remained the same, the jitter performance requirements of the Refclk have improved to support the higher data rates prevalent with PCI Express 2.1 and 3.1. We will look at the Refclk jitter requirements in the following sections. The standards allow for some flexibility in how Refclk is distributed to the devices in a system. The three supported clocking architectures are illustrated in Figure 3. The Common Clock RX Architecture is the simplest and most widely used form of clock distribution between devices. In this architecture the same 100 MHz Refclk source is distributed to both the transmitting and receiving device. In the Data Clocked RX Architecture, the receiving device does not require a Refclk. Instead it recovers the clock embedded in the transmitted datastream. The Separate Clocking Architecture uses different clocks for the transmitting and receiving devices. This is possible because the standard allows up to 600 ppm of frequency separation between the transmitter and receiver. Among the deciding factors in selecting the best clocking architecture are system partitioning and Refclk jitter performance requirements. We will explore these factors in the following sections. Common Clock Rx Architecture Data Clocked Rx Architecture Device A Link Device B Device A Link Device B 100 MHz ±300ppm 100 MHz ±300ppm Separate Clock Architecture Device A Link Device B 100 MHz ±300ppm 100 MHz ±300ppm Figure 3. Clock Architectures Rev. 0.2 3
AN562 4. Refclk Jitter Requirements Jitter of the reference clock has a direct impact on the efficiency of the data transfer between two devices. The data recovery process is able to track a portion of the jitter frequencies that are within its bandwidth, but it is the jitter frequencies that it cannot track that must be limited. This untrackable jitter spectrum is easily defined using a series of transfer functions that represent the loop bandwidths of the PLLs and the Clock Data Recovery (CDR) that affect the data recovery process. The standards defines the overall transfer function, parameters (bandwidth and peaking), and jitter limits for each of the three clocking architectures. 4.1. Filtering Applied to Refclk Measurements PCI-Express specifications include and require multiple filtering operations to be performed on the Refclk data in order to obtain the jitter results at the CDR latch. The reason for this is because some of the jitter will be tracked by the TX and RX PLLs and some will be removed, so the final result at the CDR latch is the only jitter that will impact the performance of recovering data. In revision 3.1 of the PCI-Express base specification, five filtering operations are applied to the data: SSC Separation, 0.01 1.5 MHz step band pass filter (BPF), 1.5 MHz step High Pass Filter (HPF), edge filtering, and architecture specific PLL difference functions. SSC Separation Spread Spectrum Clocking (SSC) separation is intended to remove the energy associated with the spread spectrum in the low frequency range (0.01-1.5 MHz) in order to define separate low frequency Rj and Dj components. 0.01-1.5 MHz Step BPF The intent of having a 0.01 MHz step on the low end of this band pass filter is to eliminate any 1/f noise in the clock data since that noise is 100% tracked by the CDR. This band also eliminates the high frequency jitter components 1.5 MHz and beyond that may not be tracked by the CDR. This range is where the low frequency Rj specification is defined. 1.5 MHz Step HPF This filter completely removes the low frequency jitter components, taking into account the high frequency components that may or may not be tracked by the CDR. This jitter will be the dominant jitter seen by the CDR latch causing system performance degradation. Edge Filtering The data taken for the reference clock jitter measurements is typically done on real time oscilloscopes that will have noise due to the scopes limitations from the finite sampling and voltage resolution aperture. A voltage averaging process should be applied at 5 GHz. This application can be done most accurately with a Fourier Transform filter, but can also be effectively achieved through a voltage averaging process if the FFT method is too computationally intensive. Most O-scopes allow you to change the effective bandwidth as well. PLL Difference Function and Max PLL Band Width Function The bulk of this application note pertains to the associated PLL difference and Max PLL BW functions for any given architecture. The intent of the jitter measurements for PCI-Express reference clocks is to determine what the jitter is that is seen by the data latch at the CDR. Clock jitter at this latch will directly impact how much margin the CDR has to the incoming degraded data stream. A typical PCI-Express system is the common clocked architecture that considers a TX and RX PLL as well as a CDR. All three of these have a characteristic transfer function associated with it that determines how much noise on the clock is either transmitted, tracked, or attenuated. 4 Rev. 0.2
4.2. Jitter Requirements for the Common Refclk RX Architecture AN562 Since the reference clock for the Common Clock RX Architecture is distributed to both the transmit and receive devices, its overall transfer function, H(s), becomes the difference between the transfer functions of the transmit path and receive paths. The transfer functions relevant to the 1.1, 2.1, and 3.1 standards for the Common Clock RX Architecture are shown in Figure 4. Device A Tx Latch Link Device B Rx Latch H 3 (s) Tx PLL PLL and CDR Transfer Functions 2 2 s 1 n1 n1 H 1 ( s) s 2 2 2 s 1 n1 n1 H 1(s) f 1_3dB Tx PLL T1 T2 CDR Rx PLL f 3_3dB H 2(s) f 2_3dB Rx PLL CDR 2 2 s 2 n2 n2 H 2 ( s) s 2 2 2 s 2 n2 n2 s H 3 ( s) n3 2 f 3_3dB s n3 Refclk Path Delay Difference: T = T1 T2 100 MHz ±300ppm Overall Jitter Transfer Functions Transfer Function Parameters Defined f 1_3dB 22.0 MHz 3.0 db Peaking n1 11.83 2 Mrad/s 1 0.54 1.1 H( s) H 1 ( s ) H 2 ( s ) e s T H 3 ( s ) where T = 10 ns max f 2_3dB 1.5 MHz 3.0 db Peaking n2 0.807 2 Mrad/s 2 0.54 f 3_3dB 1.5 MHz 2.1 H( s) H 1 ( s ) e s T H 2 ( s ) f 1_3dB 5.0 MHz f 1_3dB 8.0 MHz 1.0 db Peaking n1 1.82 2 Mrad/s 1 1.16 3.0 db Peaking n1 4.31 2 Mrad/s 1 0.54 where T = 12 ns max f 2_3dB 16.0 MHz 3.0 db Peaking n2 8.61 2 Mrad/s 2 0.54 3.1 H( s) H 1 ( s ) e s T H 2 ( s ) H 3 ( s ) H ( s) H 2 ( s ) e s T H 1 ( s ) H 3 ( s ) where T = 12 ns max f 1_3dB 2.0 MHz f 1_3dB MHz f 2_3dB 2.0 MHz f 2_3dB 5.0 MHz 0.01 db Peaking n1 0.448 Mrad/s 1 14 n1 0.896 Mrad/s 1 14 0.01 db Peaking n2 0.448 Mrad/s 2 14 n2 1.12 Mrad/s 2 14 2.0 db Peaking n1 6.02 Mrad/s 1 0.73 n1 12.04 Mrad/s 1 0.73 1.0 db Peaking n2 4.62 Mrad/s 2 1.15 n2 11.53 Mrad/s 2 1.15 f 3_3dB 10.0 MHz 64 Combinations Figure 4. Jitter Transfer Functions For The Common Clocked RX Architecture Rev. 0.2 5
AN562 Using 1.1 as an example, the overall transfer function H(s) becomes a bandpass filter as shown in Figure 5. The area under the curve becomes the untracked jitter that needs to be limited to ensure efficient data transmission. 10 Hs ( ) H 1 ( s) H 2 ( s) e s T H 3 ( s) 0 10 20 f 1_3dB : 22.0 MHz, 3.0 db peaking f 2_3dB : 1.5 MHz, 3.0 db peaking f 3_3dB : 1.5 MHz 30 Gain (db) 40 50 60 Untracked Jitter 70 80 90 100 1 10 4 1 10 5 1 10 6 1 10 7 1 10 8 Figure 5. 1.1 Overall Transfer Function for the Common Clock RX Architecture As shown in Figure 4 there are two possible TX PLL bandwidths available for 2.1, so we need to compute the worst case Refclk jitter using the two different bandwidth combination. 3.1 standard allows even more TX PLL and RX PLL bandwidth flexibility with 16 different bandwidth combinations and two transfer functions resulting in 32 unique combinations. Again, the resulting worst case jitter from these 32 combinations must be below the jitter limits specified by the standards. Refer to the Appendices at the end of this document for a listing of all possible parameter combinations and associated transfer functions. The Refclk jitter limits for all three standards after the overall transfer function(s) have been applied are shown in Table 1. Table 1: Common Refclk RX Architecture Jitter Limits Description Symbol Limit Units 1.1 Random Jitter R j 4.7 ps pk-pk 2.1. Frequency (Hz) Deterministic Jitter D j 41.9 ps pk-pk Total Jitter where Tj = Dj + 169 x Rj (for BER 10-12 ) High Frequency RMS Jitter Measured from 1.5 MHz to Nyquist (or f REFCLK 2) Low Frequency RMS Jitter Measured from 10 khz to 1.5 MHz T j 108 ps pk-pk J RMS-HF 3.1 ps RMS J RMS-LF 3.0 ps RMS 3.1 Random Jitter J RMS 1.0 ps RMS Note: All jitter measurements are filtered using the overall transfer function(s) defined in Figure 4 after all combinations of parameters have been exercised. See Appendix A D. 6 Rev. 0.2
AN562 4.3. Jitter Requirements for the Data Clocked RX Architecture The Refclk transmission path in a data clock RX architecture is much simpler than in the common clocked RX architecture since it only has one path. With this single path, the TX PLL and CDR do not share a common Refclk so the jitter transfer function only has the TX PLL transfer function plus the low pass characteristic of the CDR. This architecture requires the CDR to track all low frequency jitter including SSC. The jitter transfer functions for 2.1 and 3.1 are shown in Figure 7. The data clocked RX architecture is not defined for 1.1. Jitter limits are determined using all possible parameter combinations as outlined in Appendix A. The jitter limits for the data clocked RX architecture are shown in Table 2. Device A Tx Latch Link Device B Rx Latch Tx PLL PLL and CDR Transfer Functions 2 2 s 1 n1 n1 H 1 ( s) s 2 2 2 s 1 n1 n1 H1(s) Tx PLL CDR H3(s) f3_3db CDR 3.1 2 2 s 3 n3 n3 H 3 ( s) s 2 2 2 s 3 n3 n3 f1_3db 100 MHz +300ppm,-2800 Overall Jitter Transfer Functions Transfer Function Parameters 1.1 Not defined in standards 0.5 db Peaking 3.0 db Peaking 2.1 H( s) H 1 ( s ) H CDR (s) f 1_3dB 16.0 MHz n1 8.61 2 Mrad/s 1 1.75 n1 8.61 2 Mrad/s 1 0.54 H CDR (s) = s 2 s 2 + 2 ms + m 2 m = 2pƒ m = 0.707, and ƒ m = 2x5MHz 1+2 2+ 1+(1+(2 2 ) 2 f 1_3dB 2.0 MHz f 1_3dB 2.0 MHz 0.01 db Peaking n1 0.448 1 14 Mrad/s 2.0 db Peaking n1 6.02 Mrad/s 1 0.73 1.0 db Peaking n1 4.62 1 1.15 Mrad/s 0.01 db Peaking 2.0 db Peaking 3.1 H( s) H 1 ( s) 1 H 3 ( s) f 1_3dB MHz n1 0.896 Mrad/s 1 14 n1 12.04 Mrad/s 1 0.73 0.01 db Peaking 1.0 db Peaking f 1_3dB 5.0 MHz n1 1.12 1 14 Mrad/s n1 11.53 Mrad/s 1 1.15 0.5 db Peaking 2.0 db Peaking f 3_3dB 10 MHz n3 16.57 Mrad/s 3 1.75 n3 33.8 3 0.73 Mrad/s Figure 6. Jitter Transfer Functions for the Data Clocked RX Architecture Rev. 0.2 7
AN562 1.1 2.1 Table 2: Data Refclk RX Architecture Jitter Limits Not defined in standards Description Symbol Limit Units High Frequency RMS Jitter Measured from 1.5 MHz to Nyquist (or f REFCLK 2) Low Frequency RMS Jitter Measured from 10 khz to 1.5 MHz J RMS-HF ps RMS J RMS-LF 7.5 ps RMS 3.1 Random Jitter J RMS 1.0 ps RMS Note: All jitter measurements are filtered using the overall transfer function(s) defined in Figure 4 after all combinations of parameters have been exercised. See Appendix A. 4.4. Jitter Requirements for the No SSC Separate Clock Architecture (SRNS) The separate clock architecture uses two independent reference clocks for the transmitting and receiving devices as shown in Figure 7. Using two separate Refclks of 100 MHz ±300 ppm is possible because the standards allow for up to 600 ppm frequency separation between clocks. The consequence of using the entire frequency margin is that spread spectrum must be turned off for both Refclk sources. Device A Tx Latch Link Device B Rx Latch 2 2 s 1 n1 n1 H 1 ( s) s 2 2 2 s 1 n1 n1 2 2 s 2 n2 n2 H 2 ( s) s 2 2 2 s 2 n2 n2 H 1(s) f 1_3dB Tx PLL 100 MHz ±300ppm CDR Rx PLL 100 MHz ±300ppm H 2(s) f 2_3dB f 1_3dB 16.0 MHz f 2_3dB 16.0 MHz 3.0 db Peaking n1 8.61 2 Mrad/s 1 0.54 3.0 db Peaking n2 8.61 2 Mrad/s 2 0.54 2 X 2 ( s) H 2 ( s ) 2 Xs ( ) X 1 ( s) H 1 ( s ) where, X( s) X 1 ( s) X 2 ( s) Total Jitter Tx Refclk Jitter Rx Refclk Jitter Figure 7. Separate Clock Architecture There is no overall jitter transfer function defined in the standards for this architecture. Since both Refclks are independent, their phase jitter is passed through the TX and RX PLLs independently and a maximum PLL bandwidth of 16 MHz with 3.0 db of peaking should be assumed. Since both Refclks are independent, the random jitter components of each clock are added as a root sum square (RSS). The standards do not specify jitter limits for this clock architecture, although it states that jitter must be considerably tighter than for the other two architectures. Ultimately the jitter limits will depend on the TX and RX device specifications. 8 Rev. 0.2
AN562 5. Gen2 (5GB/s) and Gen3 (8GB/s) Jitter Requirements for the Separate Refclk with Independent SSC (SRIS) Similar to the SRNS architecture at 5 Gb/s and 8 Gb/s, it is now a possibility that spread spectrum clocking can be independently applied via the refclk for the TX and RX as diagrammed in Figure 7. This architecture now burdens the RX with tracking and rejecting the phase shift between the RX and TX that is inherent in the two independent refclks with SSC. The ability to support this architecture requires the CDR to have a second order high-pass filter in the transfer function in order to reject the phase shift that is inherent in the independent SSC implementation. Equations 1 and 2 are the CDR transfer functions that should be used in the Gen2 and Gen3 systems respectively. H CDR S = s 2 ------------------------------------------------ s 2 + 2 m s + 2 m Equation 1. Gen2 (5Gb/s) SRIS CDR Transfer Function Where: m = 2 f m = 0.70 and f m = --------------------------------------------------------------------- 2 5MHz 1 + 2 2 + 1+ 1 + 2 2 2 H CDR s = s 2 ----------------------------- s 2 + sa + B s 2 2 + 2 2 0 s + 0 -------------------------------------------- s 2 2 + 2 1 0 s + 0 Where: Equation 2. Gen3 (8GB/s) SRIS CDR Transfer Function 1 1 = ------, 2 = 1, 0 = 10 7 2, A= 2.2 10 12 2 and B= 2.2 10 12 2 () 2 Since the reference clocks are independent of each other and, given that their dominant jitter is random, then their combined impact on the system should be root sum square of the individual terms. X SRIS = X 1 s H 1 s H CDR s 2 + X 2 s H 2 s H CDR s 2 Where H 1 (s) and H 2 (s) follow the same transfer functions as used in Figure 7. Table 3. SRIS Jitter Limits for 5GB/s and 8GB/s Description Symbol Max Limit Units Gen2 RMS Refclk jitter for SRIS architecture at 5.0Gb/s (Gen2) T REFCLK-RMS-SRIS 2.0 ps RMS Gen3 RMS Refclk jitter for SRIS architecture at 8.0Gb/s (Gen3) T REFCLK-RMS-SRIS 0.5 ps RMS Rev. 0.2 9
AN562 6. Spread Spectrum Clocking (SSC) Spread spectrum clocking is a technique used to lower the amount of radiated electromagnetic interference (EMI) that is generated from high speed digital signals. Spread spectrum clocks use low frequency modulation of the carrier frequency to spread out the radiated energy across a broader range of frequencies. The frequency spectrum of a clock with and without spread spectrum is illustrated in Figure 8. Radiation from data lines transmitted with a device using a spread spectrum clock reference will also benefit from the same EMI reduction. Reduced Amplitude and EMI Clock with SSC Off Clock with SSC On (downspread) Carrier Frequency f Figure 8. Spectrum Analyzer Plot of a Clock With and Without Spread Spectrum devices are specified to reliably transmit data when using a Refclk with a spread spectrum modulation rate of 30 33 khz and modulation amplitude of 0 to 0.5% (i.e., downspread 0.5% in reference to the carrier frequency). Because each device must transmit within a bit rate of ±300 ppm of each other, the same Refclk must be supplied to both devices if SSC is used. Therefore, in some system implementations, separate clocking architecture will not work if SSC is turned on unless both clocks are synchronized to a common source. In the case where the system is SRIS capable, the CDRs will be designed with loop filter characteristics such that the SSC can be tracked independently by the receiver allowing for SRIS support. The bandwidth of such a synchronizing clock (i.e., a phase-locked loop) must be high enough to track the 30 33 khz modulation rate. For practical purposes, this means a TX or RX PLL must have a loop bandwidth greater than 1.5 MHz to ensure the SSC clock is tracked. Using SSC is possible for the Separate Reflck, Common Clocked RX Architecture, and Data Clocked RX Architecture. In addition to the SSC modulation rate and modulation amplitude, there is an additional requirement for the maximum rate of change of the frequency on a Refclk with SSC active at 1250 ppm/µs. Refclks with the SSC active will need to meet additional phase jitter requirements at low frequency as shown in Table 2. Table 4. Limits for Phase Jitter from the Reference Clock with SSC Active Frequency Maximum Peak to peak phase jitter (ps) 30 khz 33 khz 25000 100 khz 1000 500 khz 25 10 Rev. 0.2
AN562 7. HCSL Output Signal Format The host clock signal level (HCSL) is the output signal format specified by the PCI Express Card Electromechanical Specification 2.0 for the Refclk signal and it is commonly found in the PC and Server markets. Using a standardized signaling level for Refclk ensures compatibility between PC motherboards and add-in cards manufactured by different vendors. HCSL is a differential current mode signal that nominally swings from 0 V to 700 mv. HCSL is a point-to-point signal format meaning that a separate output driver is required to drive each device. Multidrop connections (one output driver to multiple devices) are not supported. HCSL drivers are source terminated as shown in Figure 9. Refclk PCI Express Clock Driver 22-33 22-33 Keep very close to driver 50 50 PCI Express Add-In Card Refclk 50 50 Connector Figure 9. HCSL Output Driver Termination Systems that don t require compatibility with add-in cards or functions implemented in FPGAs can use other Refclk signal formats. LVDS, LVPECL, and even LVCMOS are common. Rev. 0.2 11
AN562 8. REFCLK Test Setup The reference clock test setup as defined in the 3.1 specification assumes that only the reference clock generator is present. It takes the approach of measuring with the worst case system degradation in place using a 12-inch differential trace that is terminated by two 2 pf capacitors. 12 Inches Refclk Measurement Refclk Generator Differential PCB Trace 100Ω ±10% 2pF 2pF Figure 10. REFCLK Test Setup 12 Rev. 0.2
AN562 9. A Typical PCI Express Application Silicon Labs offers a variety of clock devices that allows for flexible Refclk distribution. For example, the Si5338 I 2 C Programmable Any-Frequency, Any-Output Quad Clock Generator is an ideal device for generating clocks: Compliant with PCI Express 3.1 and legacy standards (2.1, 1.1) PCI Express 3.1 jitter = 0.12 ps RMS (10x lower than the requirement) Generates up to four 100 MHz HCSL output clocks but is programmable with other frequencies and signal formats. This allows one clock device to generate Refclks and other board clocks of different frequencies and signal formats. Output frequencies are programmable per output from 5 MHz to 710 MHz. Independent VDDO for each output clock enables integrated level translation. Output signal formats are programmable per output as HCSL, LVDS, LVPECL or LVCMOS. Excellent jitter performance allows Refclk generation for Common Refclk RX, Data Clocked RX, and Separate Clock Architectures. Spread spectrum can be enabled or disabled per output with programmable modulation rate and modulation amplitude per output. Built-in HCSL terminations. Small 4x4 mm package A typical use of the Si5338 in a application is shown in Figure 11. In this example the Si5338 replaces a 100 MHz clock oscillator with spread spectrum, a 1:2 HCSL buffer, a 66.6667 MHz clock oscillator, and a 125 MHz clock oscillator. Motherboard Add-In Board CPU Device Device 25 MHz XTAL +/- 100ppm Si5338 Quad Clock Generator OSC PLL Multi- Synth 0 Multi- Synth 1 Multi- Synth 2 Multi- Synth 3 66.66 MHz LVCMOS 100 MHz HCSL 100 MHz HCSL 125 MHz LVCMOS Ethernet Figure 11. Application Using the Si5338 as the Refclk Generator Rev. 0.2 13
AN562 10. Conclusion There are several things to consider when choosing the right reference clock for a PCI Express application. Jitter performance is a key consideration for ensuring efficient and reliable data transfer between two devices. This can only be guaranteed by choosing a device that specifies jitter across all PLL and CDR bandwidths and clocking architecture transfer functions. A clock with selectable spread spectrum can also be an important consideration for meeting EMI requirements. In some cases clocks need flexible output signal formats and frequencies other than the standard 100 MHz HCSL signal format. A clock generator like the Si5338 provides the reliability and flexibility needed to meet all PCI Express applications and requirements. 14 Rev. 0.2
AN562 11. References PCI Express Base Specification Revision 1.1, March 28, 2005. PCI Express Jitter and BER Revision 1.0, February, 2005. PCI Express Card Electromechanical Specification Revision 2.0, April 11, 2007. PCI Express Base Specification Revision 2.1, March 4, 2009. PCI Express Base Specification Revision 3.1, October 8, 2014. Silicon Labs Si5338 I 2 C Programmable Any-Frequency, Any-Output Quad Clock Generator data sheet. Rev. 0.2 15
AN562 APPENDIX A PCIE COMPLIANCE REPORT 16 Rev. 0.2
PCI Express Report Page 1 of 27 Data File Overview File Type Waveform File Time Domain Differential C:\tmp\Si5338_SN001_waveform_85C_MinV.bin Waveform File Creation Date 2015-11-17 14:58:37 GMT-06:00 Edge Filtering Clock Frequency On 100.001 MHz Number of Edges 256,252 Sample Interval Average Threshold Voltage 50.000 ps -542.760 μv Jitter Summary # Class Data Rate Architecture Specs PLL1 BW PLL1 Peak PLL2 BW PLL2 Peak CDR BW CDR Peak Specification Analysis HF RMS LF RMS Pk-Pk HF RMS LF RMS Pk-Pk 1 GEN1 2.5 Gb/s Common Clock 1.1 2.1 3.1 22 MHz 3 db 1.5 MHz 3 db 1.5 MHz 0 db 86 ps 698.92 fs 350.31 fs 6.67 ps PASS 2 GEN2 5 Gb/s Common Clock 3.1 5 MHz 0.5 db 16 MHz 0.5 db N/A N/A 3.1 ps 3 ps 461.92 fs 178.88 fs 1.58 ps PASS 3 GEN2 5 Gb/s Common Clock 3.1 5 MHz 1 db 16 MHz 0.5 db N/A N/A 3.1 ps 3 ps 477.06 fs 166.69 fs 1.46 ps PASS 4 GEN2 5 Gb/s Common Clock 3.1 8 MHz 3 db 16 MHz 0.5 db N/A N/A 3.1 ps 3 ps 477.89 fs 50.40 fs 991.63 fs PASS 5 GEN2 5 Gb/s Common Clock 3.1 5 MHz 0.5 db 16 MHz 1 db N/A N/A 3.1 ps 3 ps 470.56 fs 191.83 fs 1.64 ps PASS 6 GEN2 5 Gb/s Common Clock 3.1 5 MHz 1 db 16 MHz 1 db N/A N/A 3.1 ps 3 ps 487.28 fs 180.72 fs 1.53 ps PASS 7 GEN2 5 Gb/s Common Clock 3.1 8 MHz 3 db 16 MHz 1 db N/A N/A 3.1 ps 3 ps 476.10 fs 63.36 fs 1.02 ps PASS 8 GEN2 5 Gb/s Common Clock 2.1 3.1 9 GEN2 5 Gb/s Common Clock 1.1 2.1 3.1 10 GEN2 5 Gb/s Common Clock 2.1 3.1 5 MHz 0.5 db 16 MHz 3 db N/A N/A 3.1 ps 3 ps 493.54 fs 198.46 fs 1.67 ps 5 MHz 1 db 16 MHz 3 db N/A N/A 3.1 ps 3 ps 515.28 fs 189.39 fs 1.57 ps 8 MHz 3 db 16 MHz 3 db N/A N/A 3.1 ps 3 ps 498.39 fs 73.02 fs 1.03 ps PASS PASS PASS 11 GEN2 5 Gb/s Data Clock 3.1 16 MHz 0.5 db N/A N/A 5 MHz 3 db 4 ps 7.5 ps 371.18 fs 33.86 fs 774.10 fs PASS (1) 12 GEN2 5 Gb/s Data Clock 3.1 16 MHz 3 db N/A N/A 5 MHz 3 db 4 ps 7.5 ps 414.27 fs 33.19 fs 857.17 fs PASS (1) 13 GEN2 5 Gb/s Separate Clock SRNS 3.1 16 MHz 3 db 16 MHz 3 db 5 MHz 3 db 415.59 fs 33.19 fs N/A N/A (2) 14 GEN3 8 Gb/s Common Clock 3.1 15 GEN3 8 Gb/s Common Clock 3.1 16 GEN3 8 Gb/s Common Clock 3.1 17 GEN3 8 Gb/s Common Clock 3.1 18 GEN3 8 Gb/s Common Clock 3.1 19 GEN3 8 Gb/s Common Clock 3.1 20 GEN3 8 Gb/s Common Clock 3.1 21 GEN3 8 Gb/s Common Clock 3.1 22 GEN3 8 Gb/s Common Clock 3.1 23 GEN3 8 Gb/s Common Clock 3.1 24 GEN3 8 Gb/s Common Clock 3.1 25 GEN3 8 Gb/s Common Clock 3.1 2 MHz 0.01 db 2 MHz 0.01 db 10 MHz 0 db 1 ps 63.94 fs 4.93 fs 572.50 fs 2 MHz 2 db 2 MHz 0.01 db 10 MHz 0 db 1 ps 71.63 fs 26.13 fs 693.36 fs 4 MHz 0.01 db 2 MHz 0.01 db 10 MHz 0 db 1 ps 117.69 fs 20.54 fs 1.08 ps 4 MHz 2 db 2 MHz 0.01 db 10 MHz 0 db 1 ps 97.40 fs 34.62 fs 898.37 fs 2 MHz 0.01 db 2 MHz 1 db 10 MHz 0 db 1 ps 65.38 fs 14.58 fs 604.16 fs 2 MHz 2 db 2 MHz 1 db 10 MHz 0 db 1 ps 57.64 fs 15.96 fs 549.71 fs 4 MHz 0.01 db 2 MHz 1 db 10 MHz 0 db 1 ps 123.25 fs 28.35 fs 1.17 ps 4 MHz 2 db 2 MHz 1 db 10 MHz 0 db 1 ps 103.18 fs 39.49 fs 934.67 fs 2 MHz 0.01 db 5 MHz 0.01 db 10 MHz 0 db 1 ps 143.03 fs 21 fs 1.32 ps 2 MHz 2 db 5 MHz 0.01 db 10 MHz 0 db 1 ps 156.07 fs 41.49 fs 1.52 ps 4 MHz 0.01 db 5 MHz 0.01 db 10 MHz 0 db 1 ps 145.17 fs 9.04 fs 1.32 ps 4 MHz 2 db 5 MHz 0.01 db 10 MHz 0 db 1 ps 152.08 fs 17.79 fs 1.38 ps PASS PASS PASS PASS PASS PASS PASS PASS PASS PASS PASS PASS Prepared by Silicon Labs Clock Jitter Tool v0.21 on 2015-11-17 15:05:55 GMT-06:00
PCI Express Report Page 2 of 27 # Class Data Rate Architecture Specs 26 GEN3 8 Gb/s Common Clock 3.1 PLL1 BW PLL1 Peak PLL2 BW PLL2 Peak CDR BW CDR Peak Specification Analysis HF RMS LF RMS Pk-Pk HF RMS LF RMS Pk-Pk 2 MHz 0.01 db 5 MHz 1 db 10 MHz 0 db 1 ps 129.31 fs 30.67 fs 1.20 ps PASS 27 GEN3 8 Gb/s Common Clock 3.1 28 GEN3 8 Gb/s Common Clock 3.1 29 GEN3 8 Gb/s Common Clock 3.1 2 MHz 2 db 5 MHz 1 db 10 MHz 0 db 1 ps 144.39 fs 44.61 fs 1.39 ps 4 MHz 0.01 db 5 MHz 1 db 10 MHz 0 db 1 ps 132.39 fs 15.07 fs 1.21 ps 4 MHz 2 db 5 MHz 1 db 10 MHz 0 db 1 ps 130.22 fs 11.11 fs 1.14 ps PASS PASS PASS 30 GEN3 8 Gb/s Data Clock 3.1 2 MHz 0.01 db N/A N/A 10 MHz 0.5 db 1 ps 107.87 fs 55.31 fs 977.89 fs PASS 31 GEN3 8 Gb/s Data Clock 3.1 2 MHz 1 db N/A N/A 10 MHz 0.5 db 1 ps 105.86 fs 61.53 fs 997.91 fs PASS 32 GEN3 8 Gb/s Data Clock 3.1 2 MHz 2 db N/A N/A 10 MHz 0.5 db 1 ps 106.53 fs 70.16 fs 1.04 ps PASS 33 GEN3 8 Gb/s Data Clock 3.1 4 MHz 0.01 db N/A N/A 10 MHz 0.5 db 1 ps 159.68 fs 61.13 fs 1.48 ps PASS 34 GEN3 8 Gb/s Data Clock 3.1 4 MHz 2 db N/A N/A 10 MHz 0.5 db 1 ps 164.62 fs 76.92 fs 1.48 ps PASS 35 GEN3 8 Gb/s Data Clock 3.1 5 MHz 0.01 db N/A N/A 10 MHz 0.5 db 1 ps 180.11 fs 61.99 fs 1.73 ps PASS 36 GEN3 8 Gb/s Data Clock 3.1 5 MHz 1 db N/A N/A 10 MHz 0.5 db 1 ps 180.78 fs 70.69 fs 1.67 ps PASS 37 GEN3 8 Gb/s Data Clock 3.1 2 MHz 0.01 db N/A N/A 10 MHz 2 db 1 ps 92.96 fs 22.68 fs 928.12 fs PASS 38 GEN3 8 Gb/s Data Clock 3.1 2 MHz 1 db N/A N/A 10 MHz 2 db 1 ps 84.63 fs 25.02 fs 831.19 fs PASS 39 GEN3 8 Gb/s Data Clock 3.1 2 MHz 2 db N/A N/A 10 MHz 2 db 1 ps 77.10 fs 28.46 fs 723.51 fs PASS 40 GEN3 8 Gb/s Data Clock 3.1 4 MHz 0.01 db N/A N/A 10 MHz 2 db 1 ps 156.30 fs 25.34 fs 1.53 ps PASS 41 GEN3 8 Gb/s Data Clock 3.1 4 MHz 2 db N/A N/A 10 MHz 2 db 1 ps 141.56 fs 32.42 fs 1.41 ps PASS 42 GEN3 8 Gb/s Data Clock 3.1 5 MHz 0.01 db N/A N/A 10 MHz 2 db 1 ps 181.99 fs 25.74 fs 1.76 ps PASS 43 GEN3 8 Gb/s Data Clock 3.1 5 MHz 1 db N/A N/A 10 MHz 2 db 1 ps 173.99 fs 29.54 fs 1.71 ps PASS 44 GEN3 8 Gb/s Separate Clock SRNS 3.1 4 MHz 2 db 4 MHz 2 db 10 MHz 3 db 81.07 fs 9.43 fs N/A N/A (2) (1) PCI-Express Gen2 Data Clocked equations have been updated from the base specification 3.1 (equation 4.3.6) to reflect the requirement for the CDR to track low frequency jitter and SSC. The CDR is modeled after the Gen2 SRIS CDR given that the overall architecture of Data Clocked is an equivalent subset of Separate Clock. (2) The SRNS (Separate Refclk with No SSC) specification for Gen2 and Gen3 data rates does not have a specification for jitter explicitly stated in the 3.1 Base Specification and is presented in this tool as informative only. The appropriate max PLL bandwidths of the RX and TX PLL are used in the measurement and the overall jitter is calculated from the Root Square Sum (RSS) of the RX and TX Reflck jitter values after applying the PLL and CDR filters to the original jitter spectrum. The jitter bandwidths for the RX and TX PLL for Gen2 is 16MHz/3dB and Gen3 is 4MHz/2dB. The CDR term used is that same is that used for SRIS since the expectation is the similar CDRs with be used in separate clock applications. (3) Spread Spectrum Clocking (SSC) separation is intended to remove the energy associated with the spread spectrum (30KHz-33KHz) in the low frequency range (0.01-1.5MHz) specified by the PCI-Express Base Specification in order to define separate low frequency Rj and Dj components. This feature should be turned off for data sets that do not have spread spectrum clocking. Prepared by Silicon Labs Clock Jitter Tool v0.21 on 2015-11-17 15:05:55 GMT-06:00
PCI Express Report Page 3 of 27 Unfiltered Waveform Jitter Information vs. Time Time Interval Error Period Cycle-to-Cycle Reference Clock AC Specifications Test Specification Analysis Min Max Min Max Avg Rising Edge Rate.6 V/ns 4 V/ns 1.49 V/ns 1.57 V/ns 1.53 V/ns PASS Falling Edge Rate.6 V/ns 4 V/ns 1.49 V/ns 1.57 V/ns 1.52 V/ns PASS Diff Input High 150 mv 225.70 mv 225.70 mv 225.70 mv PASS Diff Input Low -150 mv -225.70 mv -225.70 mv -225.70 mv PASS Average Clock Period Accuracy -300 ppm 2,800 ppm N/A N/A -10 ppm PASS Absolute Period 9.847 ns 10.203 ns 9.996 ns 10.004 ns 10.000 ns PASS Cycle to Cycle Jitter 150 ps 0.01 fs 7.50 ps 1.23 ps PASS Duty Cycle 40 % 60 % 49.5 % 50.0 % 49.9 % PASS Detailed Jitter Reports In the pages that follow, jitter response is analyzed for each selected standard, architecture and filter parameter combination. Prepared by Silicon Labs Clock Jitter Tool v0.21 on 2015-11-17 15:05:55 GMT-06:00
PCI Express Report Page 4 of 27 1 GEN1 2.5 Gb/s Common Clock 1.1 2.1 3.1 22 MHz 3 db 1.5 MHz 3 db 1.5 MHz 0 db 10 ns N/A Refclk HF RMS Jitter 698.922 fs N/A Refclk LF RMS Jitter 350.309 fs N/A Pk-pk Phase Jitter at BER 10^-6 86 ps 6.671 ps PASS 2 GEN2 5 Gb/s Common Clock 3.1 5 MHz 0.5 db 16 MHz 0.5 db N/A N/A 12 ns On (3) Refclk HF RMS Jitter 3.1 ps 461.920 fs PASS Refclk LF RMS Jitter 3 ps 178.885 fs PASS Pk-pk Phase Jitter at BER 10^-6 1.576 ps N/A Prepared by Silicon Labs Clock Jitter Tool v0.21 on 2015-11-17 15:05:55 GMT-06:00
PCI Express Report Page 5 of 27 3 GEN2 5 Gb/s Common Clock 3.1 5 MHz 1 db 16 MHz 0.5 db N/A N/A 12 ns On (3) Refclk HF RMS Jitter 3.1 ps 477.062 fs PASS Refclk LF RMS Jitter 3 ps 166.692 fs PASS Pk-pk Phase Jitter at BER 10^-6 1.458 ps N/A 4 GEN2 5 Gb/s Common Clock 3.1 8 MHz 3 db 16 MHz 0.5 db N/A N/A 12 ns On (3) Refclk HF RMS Jitter 3.1 ps 477.886 fs PASS Refclk LF RMS Jitter 3 ps 50.401 fs PASS Pk-pk Phase Jitter at BER 10^-6 991.629 fs N/A Prepared by Silicon Labs Clock Jitter Tool v0.21 on 2015-11-17 15:05:55 GMT-06:00
PCI Express Report Page 6 of 27 5 GEN2 5 Gb/s Common Clock 3.1 5 MHz 0.5 db 16 MHz 1 db N/A N/A 12 ns On (3) Refclk HF RMS Jitter 3.1 ps 470.563 fs PASS Refclk LF RMS Jitter 3 ps 191.833 fs PASS Pk-pk Phase Jitter at BER 10^-6 1.641 ps N/A 6 GEN2 5 Gb/s Common Clock 3.1 5 MHz 1 db 16 MHz 1 db N/A N/A 12 ns On (3) Refclk HF RMS Jitter 3.1 ps 487.285 fs PASS Refclk LF RMS Jitter 3 ps 180.716 fs PASS Pk-pk Phase Jitter at BER 10^-6 1.528 ps N/A Prepared by Silicon Labs Clock Jitter Tool v0.21 on 2015-11-17 15:05:55 GMT-06:00
PCI Express Report Page 7 of 27 7 GEN2 5 Gb/s Common Clock 3.1 8 MHz 3 db 16 MHz 1 db N/A N/A 12 ns On (3) Refclk HF RMS Jitter 3.1 ps 476.105 fs PASS Refclk LF RMS Jitter 3 ps 63.357 fs PASS Pk-pk Phase Jitter at BER 10^-6 1.018 ps N/A 8 GEN2 5 Gb/s Common Clock 2.1 3.1 5 MHz 0.5 db 16 MHz 3 db N/A N/A 12 ns On (3) Refclk HF RMS Jitter 3.1 ps 493.536 fs PASS Refclk LF RMS Jitter 3 ps 198.458 fs PASS Pk-pk Phase Jitter at BER 10^-6 1.667 ps N/A Prepared by Silicon Labs Clock Jitter Tool v0.21 on 2015-11-17 15:05:55 GMT-06:00
PCI Express Report Page 8 of 27 9 GEN2 5 Gb/s Common Clock 1.1 2.1 3.1 5 MHz 1 db 16 MHz 3 db N/A N/A 12 ns On (3) Refclk HF RMS Jitter 3.1 ps 515.277 fs PASS Refclk LF RMS Jitter 3 ps 189.391 fs PASS Pk-pk Phase Jitter at BER 10^-6 1.568 ps N/A 10 GEN2 5 Gb/s Common Clock 2.1 3.1 8 MHz 3 db 16 MHz 3 db N/A N/A 12 ns On (3) Refclk HF RMS Jitter 3.1 ps 498.392 fs PASS Refclk LF RMS Jitter 3 ps 73.024 fs PASS Pk-pk Phase Jitter at BER 10^-6 1.026 ps N/A Prepared by Silicon Labs Clock Jitter Tool v0.21 on 2015-11-17 15:05:55 GMT-06:00
PCI Express Report Page 9 of 27 11 GEN2 5 Gb/s Data Clock 3.1 16 MHz 0.5 db N/A N/A 5 MHz 3 db N/A On (3) Refclk HF RMS Jitter 4 ps 371.178 fs PASS Refclk LF RMS Jitter 7.5 ps 33.857 fs PASS Pk-pk Phase Jitter at BER 10^-6 774.100 fs N/A 12 GEN2 5 Gb/s Data Clock 3.1 16 MHz 3 db N/A N/A 5 MHz 3 db N/A On (3) Refclk HF RMS Jitter 4 ps 414.266 fs PASS Refclk LF RMS Jitter 7.5 ps 33.194 fs PASS Pk-pk Phase Jitter at BER 10^-6 857.168 fs N/A Prepared by Silicon Labs Clock Jitter Tool v0.21 on 2015-11-17 15:05:55 GMT-06:00
PCI Express Report Page 10 of 27 13 GEN2 5 Gb/s Separate Clock SRNS 3.1 16 MHz 3 db 16 MHz 3 db 5 MHz 3 db N/A N/A Refclk HF RMS Jitter 415.594 fs N/A Refclk LF RMS Jitter 33.194 fs N/A 14 GEN3 8 Gb/s Common Clock 3.1 2 MHz 0.01 db 2 MHz 0.01 db 10 MHz 0 db 12 ns Off (3) Refclk HF RMS Jitter 1 ps 63.941 fs PASS Refclk LF RMS Jitter 4.934 fs N/A Pk-pk Phase Jitter at BER 10^-6 572.498 fs N/A Prepared by Silicon Labs Clock Jitter Tool v0.21 on 2015-11-17 15:05:55 GMT-06:00
PCI Express Report Page 11 of 27 15 GEN3 8 Gb/s Common Clock 3.1 2 MHz 2 db 2 MHz 0.01 db 10 MHz 0 db 12 ns Off (3) Refclk HF RMS Jitter 1 ps 71.633 fs PASS Refclk LF RMS Jitter 26.129 fs N/A Pk-pk Phase Jitter at BER 10^-6 693.363 fs N/A 16 GEN3 8 Gb/s Common Clock 3.1 4 MHz 0.01 db 2 MHz 0.01 db 10 MHz 0 db 12 ns Off (3) Refclk HF RMS Jitter 1 ps 117.685 fs PASS Refclk LF RMS Jitter 20.538 fs N/A Pk-pk Phase Jitter at BER 10^-6 1.079 ps N/A Prepared by Silicon Labs Clock Jitter Tool v0.21 on 2015-11-17 15:05:55 GMT-06:00
PCI Express Report Page 12 of 27 17 GEN3 8 Gb/s Common Clock 3.1 4 MHz 2 db 2 MHz 0.01 db 10 MHz 0 db 12 ns Off (3) Refclk HF RMS Jitter 1 ps 97.395 fs PASS Refclk LF RMS Jitter 34.624 fs N/A Pk-pk Phase Jitter at BER 10^-6 898.365 fs N/A 18 GEN3 8 Gb/s Common Clock 3.1 2 MHz 0.01 db 2 MHz 1 db 10 MHz 0 db 12 ns Off (3) Refclk HF RMS Jitter 1 ps 65.384 fs PASS Refclk LF RMS Jitter 14.578 fs N/A Pk-pk Phase Jitter at BER 10^-6 604.163 fs N/A Prepared by Silicon Labs Clock Jitter Tool v0.21 on 2015-11-17 15:05:55 GMT-06:00
PCI Express Report Page 13 of 27 19 GEN3 8 Gb/s Common Clock 3.1 2 MHz 2 db 2 MHz 1 db 10 MHz 0 db 12 ns Off (3) Refclk HF RMS Jitter 1 ps 57.641 fs PASS Refclk LF RMS Jitter 15.964 fs N/A Pk-pk Phase Jitter at BER 10^-6 549.708 fs N/A 20 GEN3 8 Gb/s Common Clock 3.1 4 MHz 0.01 db 2 MHz 1 db 10 MHz 0 db 12 ns Off (3) Refclk HF RMS Jitter 1 ps 123.251 fs PASS Refclk LF RMS Jitter 28.354 fs N/A Pk-pk Phase Jitter at BER 10^-6 1.173 ps N/A Prepared by Silicon Labs Clock Jitter Tool v0.21 on 2015-11-17 15:05:55 GMT-06:00
PCI Express Report Page 14 of 27 21 GEN3 8 Gb/s Common Clock 3.1 4 MHz 2 db 2 MHz 1 db 10 MHz 0 db 12 ns Off (3) Refclk HF RMS Jitter 1 ps 103.177 fs PASS Refclk LF RMS Jitter 39.485 fs N/A Pk-pk Phase Jitter at BER 10^-6 934.670 fs N/A 22 GEN3 8 Gb/s Common Clock 3.1 2 MHz 0.01 db 5 MHz 0.01 db 10 MHz 0 db 12 ns Off (3) Refclk HF RMS Jitter 1 ps 143.030 fs PASS Refclk LF RMS Jitter 210 fs N/A Pk-pk Phase Jitter at BER 10^-6 1.322 ps N/A Prepared by Silicon Labs Clock Jitter Tool v0.21 on 2015-11-17 15:05:55 GMT-06:00
PCI Express Report Page 15 of 27 23 GEN3 8 Gb/s Common Clock 3.1 2 MHz 2 db 5 MHz 0.01 db 10 MHz 0 db 12 ns Off (3) Refclk HF RMS Jitter 1 ps 156.069 fs PASS Refclk LF RMS Jitter 41.492 fs N/A Pk-pk Phase Jitter at BER 10^-6 1.518 ps N/A 24 GEN3 8 Gb/s Common Clock 3.1 4 MHz 0.01 db 5 MHz 0.01 db 10 MHz 0 db 12 ns Off (3) Refclk HF RMS Jitter 1 ps 145.168 fs PASS Refclk LF RMS Jitter 9.037 fs N/A Pk-pk Phase Jitter at BER 10^-6 1.317 ps N/A Prepared by Silicon Labs Clock Jitter Tool v0.21 on 2015-11-17 15:05:55 GMT-06:00
PCI Express Report Page 16 of 27 25 GEN3 8 Gb/s Common Clock 3.1 4 MHz 2 db 5 MHz 0.01 db 10 MHz 0 db 12 ns Off (3) Refclk HF RMS Jitter 1 ps 152.081 fs PASS Refclk LF RMS Jitter 17.790 fs N/A Pk-pk Phase Jitter at BER 10^-6 1.382 ps N/A 26 GEN3 8 Gb/s Common Clock 3.1 2 MHz 0.01 db 5 MHz 1 db 10 MHz 0 db 12 ns Off (3) Refclk HF RMS Jitter 1 ps 129.314 fs PASS Refclk LF RMS Jitter 30.673 fs N/A Pk-pk Phase Jitter at BER 10^-6 1.203 ps N/A Prepared by Silicon Labs Clock Jitter Tool v0.21 on 2015-11-17 15:05:55 GMT-06:00
PCI Express Report Page 17 of 27 27 GEN3 8 Gb/s Common Clock 3.1 2 MHz 2 db 5 MHz 1 db 10 MHz 0 db 12 ns Off (3) Refclk HF RMS Jitter 1 ps 144.391 fs PASS Refclk LF RMS Jitter 44.609 fs N/A Pk-pk Phase Jitter at BER 10^-6 1.394 ps N/A 28 GEN3 8 Gb/s Common Clock 3.1 4 MHz 0.01 db 5 MHz 1 db 10 MHz 0 db 12 ns Off (3) Refclk HF RMS Jitter 1 ps 132.386 fs PASS Refclk LF RMS Jitter 15.069 fs N/A Pk-pk Phase Jitter at BER 10^-6 1.214 ps N/A Prepared by Silicon Labs Clock Jitter Tool v0.21 on 2015-11-17 15:05:55 GMT-06:00
PCI Express Report Page 18 of 27 29 GEN3 8 Gb/s Common Clock 3.1 4 MHz 2 db 5 MHz 1 db 10 MHz 0 db 12 ns Off (3) Refclk HF RMS Jitter 1 ps 130.223 fs PASS Refclk LF RMS Jitter 11.115 fs N/A Pk-pk Phase Jitter at BER 10^-6 1.143 ps N/A 30 GEN3 8 Gb/s Data Clock 3.1 2 MHz 0.01 db N/A N/A 10 MHz 0.5 db N/A Off (3) Refclk HF RMS Jitter 1 ps 107.870 fs PASS Refclk LF RMS Jitter 55.306 fs N/A Pk-pk Phase Jitter at BER 10^-6 977.893 fs N/A Prepared by Silicon Labs Clock Jitter Tool v0.21 on 2015-11-17 15:05:55 GMT-06:00
PCI Express Report Page 19 of 27 31 GEN3 8 Gb/s Data Clock 3.1 2 MHz 1 db N/A N/A 10 MHz 0.5 db N/A Off (3) Refclk HF RMS Jitter 1 ps 105.861 fs PASS Refclk LF RMS Jitter 61.533 fs N/A Pk-pk Phase Jitter at BER 10^-6 997.907 fs N/A 32 GEN3 8 Gb/s Data Clock 3.1 2 MHz 2 db N/A N/A 10 MHz 0.5 db N/A Off (3) Refclk HF RMS Jitter 1 ps 106.527 fs PASS Refclk LF RMS Jitter 70.159 fs N/A Pk-pk Phase Jitter at BER 10^-6 1.038 ps N/A Prepared by Silicon Labs Clock Jitter Tool v0.21 on 2015-11-17 15:05:55 GMT-06:00
PCI Express Report Page 20 of 27 33 GEN3 8 Gb/s Data Clock 3.1 4 MHz 0.01 db N/A N/A 10 MHz 0.5 db N/A Off (3) Refclk HF RMS Jitter 1 ps 159.685 fs PASS Refclk LF RMS Jitter 61.125 fs N/A Pk-pk Phase Jitter at BER 10^-6 1.485 ps N/A 34 GEN3 8 Gb/s Data Clock 3.1 4 MHz 2 db N/A N/A 10 MHz 0.5 db N/A Off (3) Refclk HF RMS Jitter 1 ps 164.616 fs PASS Refclk LF RMS Jitter 76.925 fs N/A Pk-pk Phase Jitter at BER 10^-6 1.480 ps N/A Prepared by Silicon Labs Clock Jitter Tool v0.21 on 2015-11-17 15:05:55 GMT-06:00
PCI Express Report Page 21 of 27 35 GEN3 8 Gb/s Data Clock 3.1 5 MHz 0.01 db N/A N/A 10 MHz 0.5 db N/A Off (3) Refclk HF RMS Jitter 1 ps 180.107 fs PASS Refclk LF RMS Jitter 61.986 fs N/A Pk-pk Phase Jitter at BER 10^-6 1.727 ps N/A 36 GEN3 8 Gb/s Data Clock 3.1 5 MHz 1 db N/A N/A 10 MHz 0.5 db N/A Off (3) Refclk HF RMS Jitter 1 ps 180.775 fs PASS Refclk LF RMS Jitter 70.687 fs N/A Pk-pk Phase Jitter at BER 10^-6 1.671 ps N/A Prepared by Silicon Labs Clock Jitter Tool v0.21 on 2015-11-17 15:05:55 GMT-06:00
PCI Express Report Page 22 of 27 37 GEN3 8 Gb/s Data Clock 3.1 2 MHz 0.01 db N/A N/A 10 MHz 2 db N/A Off (3) Refclk HF RMS Jitter 1 ps 92.962 fs PASS Refclk LF RMS Jitter 22.676 fs N/A Pk-pk Phase Jitter at BER 10^-6 928.119 fs N/A 38 GEN3 8 Gb/s Data Clock 3.1 2 MHz 1 db N/A N/A 10 MHz 2 db N/A Off (3) Refclk HF RMS Jitter 1 ps 84.630 fs PASS Refclk LF RMS Jitter 25.021 fs N/A Pk-pk Phase Jitter at BER 10^-6 831.194 fs N/A Prepared by Silicon Labs Clock Jitter Tool v0.21 on 2015-11-17 15:05:55 GMT-06:00
PCI Express Report Page 23 of 27 39 GEN3 8 Gb/s Data Clock 3.1 2 MHz 2 db N/A N/A 10 MHz 2 db N/A Off (3) Refclk HF RMS Jitter 1 ps 77.104 fs PASS Refclk LF RMS Jitter 28.458 fs N/A Pk-pk Phase Jitter at BER 10^-6 723.514 fs N/A 40 GEN3 8 Gb/s Data Clock 3.1 4 MHz 0.01 db N/A N/A 10 MHz 2 db N/A Off (3) Refclk HF RMS Jitter 1 ps 156.298 fs PASS Refclk LF RMS Jitter 25.343 fs N/A Pk-pk Phase Jitter at BER 10^-6 1.530 ps N/A Prepared by Silicon Labs Clock Jitter Tool v0.21 on 2015-11-17 15:05:55 GMT-06:00
PCI Express Report Page 24 of 27 41 GEN3 8 Gb/s Data Clock 3.1 4 MHz 2 db N/A N/A 10 MHz 2 db N/A Off (3) Refclk HF RMS Jitter 1 ps 141.557 fs PASS Refclk LF RMS Jitter 32.421 fs N/A Pk-pk Phase Jitter at BER 10^-6 1.412 ps N/A 42 GEN3 8 Gb/s Data Clock 3.1 5 MHz 0.01 db N/A N/A 10 MHz 2 db N/A Off (3) Refclk HF RMS Jitter 1 ps 181.994 fs PASS Refclk LF RMS Jitter 25.741 fs N/A Pk-pk Phase Jitter at BER 10^-6 1.765 ps N/A Prepared by Silicon Labs Clock Jitter Tool v0.21 on 2015-11-17 15:05:55 GMT-06:00
PCI Express Report Page 25 of 27 43 GEN3 8 Gb/s Data Clock 3.1 5 MHz 1 db N/A N/A 10 MHz 2 db N/A Off (3) Refclk HF RMS Jitter 1 ps 173.988 fs PASS Refclk LF RMS Jitter 29.536 fs N/A Pk-pk Phase Jitter at BER 10^-6 1.710 ps N/A 44 GEN3 8 Gb/s Separate Clock SRNS 3.1 4 MHz 2 db 4 MHz 2 db 10 MHz 3 db N/A N/A Test Specification Analysis Refclk HF RMS Jitter 81.071 fs N/A Refclk LF RMS Jitter 9.428 fs N/A Prepared by Silicon Labs Clock Jitter Tool v0.21 on 2015-11-17 15:05:55 GMT-06:00
PCI Express Report Page 26 of 27 Transfer Function Constants # Class Architecture Specs H1 BW H1 Peaking H1 Omega H1 Zeta H2 BW H2 Peaking H2 Omega H2 Zeta H3 BW H3 Peaking H3 Omega H3 Zeta Delay 1 GEN1 Common Clock 1.1 2.1 3.1 2 GEN2 Common Clock 1.1 2.1 3.1 3 GEN2 Common Clock 1.1 2.1 3.1 4 GEN2 Common Clock 1.1 2.1 3.1 5 GEN2 Common Clock 1.1 2.1 3.1 6 GEN2 Common Clock 1.1 2.1 3.1 7 GEN2 Common Clock 1.1 2.1 3.1 8 GEN2 Common Clock 1.1 2.1 3.1 9 GEN2 Common Clock 1.1 2.1 3.1 10 GEN2 Common Clock 1.1 2.1 3.1 11 GEN2 Data Clock 2.1 3.1 12 GEN2 Data Clock 2.1 3.1 22 MHz 3 db 7.46800E+7 5.40000E-1 1.5 MHz 3 db 5.09000E+6 5.40000E-1 1.5 MHz 0 db 9.42478E+6 0.00000E+0 10 ns 5 MHz 0.5 db 8.30009E+6 1.75000E+0 16 MHz 0.5 db 2.65716E+7 1.75000E+0 12 ns 5 MHz 1 db 1.14605E+7 1.16000E+0 16 MHz 0.5 db 2.65716E+7 1.75000E+0 12 ns 8 MHz 3 db 2.70428E+7 5.40000E-1 16 MHz 0.5 db 2.65716E+7 1.75000E+0 12 ns 5 MHz 0.5 db 8.30009E+6 1.75000E+0 16 MHz 1 db 3.66624E+7 1.16000E+0 12 ns 5 MHz 1 db 1.14605E+7 1.16000E+0 16 MHz 1 db 3.66624E+7 1.16000E+0 12 ns 8 MHz 3 db 2.70428E+7 5.40000E-1 16 MHz 1 db 3.66624E+7 1.16000E+0 12 ns 5 MHz 0.5 db 8.30009E+6 1.75000E+0 16 MHz 3 db 5.40919E+7 5.40000E-1 12 ns 5 MHz 1 db 1.14605E+7 1.16000E+0 16 MHz 3 db 5.40919E+7 5.40000E-1 12 ns 8 MHz 3 db 2.70428E+7 5.40000E-1 16 MHz 3 db 5.40919E+7 5.40000E-1 12 ns 16 MHz 0.5 db 2.65716E+7 1.75000E+0 5 MHz 3 db 3.05301E+7 7.07000E-1 16 MHz 3 db 5.40982E+7 5.40000E-1 5 MHz 3 db 3.05301E+7 7.07000E-1 13 GEN2 Separate Clock SRNS 3.1 16 MHz 3 db 5.40982E+7 5.40000E-1 16 MHz 3 db 5.40982E+7 5.40000E-1 5 MHz 3 db 3.05301E+7 7.07000E-1 14 GEN3 Common Clock 3.1 15 GEN3 Common Clock 3.1 16 GEN3 Common Clock 3.1 17 GEN3 Common Clock 3.1 18 GEN3 Common Clock 3.1 19 GEN3 Common Clock 3.1 20 GEN3 Common Clock 3.1 21 GEN3 Common Clock 3.1 22 GEN3 Common Clock 3.1 23 GEN3 Common Clock 3.1 24 GEN3 Common Clock 3.1 25 GEN3 Common Clock 3.1 2 MHz 0.01 db 4.48000E+5 1.40000E+1 2 MHz 0.01 db 4.48000E+5 1.40000E+1 10 MHz 0 db 6.28319E+7 0.00000E+0 12 ns 2 MHz 2 db 6.02000E+6 7.30000E-1 2 MHz 0.01 db 4.48000E+5 1.40000E+1 10 MHz 0 db 6.28319E+7 0.00000E+0 12 ns 4 MHz 0.01 db 8.96000E+5 1.40000E+1 2 MHz 0.01 db 4.48000E+5 1.40000E+1 10 MHz 0 db 6.28319E+7 0.00000E+0 12 ns 4 MHz 2 db 1.20400E+7 7.30000E-1 2 MHz 0.01 db 4.48000E+5 1.40000E+1 10 MHz 0 db 6.28319E+7 0.00000E+0 12 ns 2 MHz 0.01 db 4.48000E+5 1.40000E+1 2 MHz 1 db 4.62000E+6 1.15000E+0 10 MHz 0 db 6.28319E+7 0.00000E+0 12 ns 2 MHz 2 db 6.02000E+6 7.30000E-1 2 MHz 1 db 4.62000E+6 1.15000E+0 10 MHz 0 db 6.28319E+7 0.00000E+0 12 ns 4 MHz 0.01 db 8.96000E+5 1.40000E+1 2 MHz 1 db 4.62000E+6 1.15000E+0 10 MHz 0 db 6.28319E+7 0.00000E+0 12 ns 4 MHz 2 db 1.20400E+7 7.30000E-1 2 MHz 1 db 4.62000E+6 1.15000E+0 10 MHz 0 db 6.28319E+7 0.00000E+0 12 ns 2 MHz 0.01 db 4.48000E+5 1.40000E+1 5 MHz 0.01 db 1.12000E+6 1.40000E+1 10 MHz 0 db 6.28319E+7 0.00000E+0 12 ns 2 MHz 2 db 6.02000E+6 7.30000E-1 5 MHz 0.01 db 1.12000E+6 1.40000E+1 10 MHz 0 db 6.28319E+7 0.00000E+0 12 ns 4 MHz 0.01 db 8.96000E+5 1.40000E+1 5 MHz 0.01 db 1.12000E+6 1.40000E+1 10 MHz 0 db 6.28319E+7 0.00000E+0 12 ns 4 MHz 2 db 1.20400E+7 7.30000E-1 5 MHz 0.01 db 1.12000E+6 1.40000E+1 10 MHz 0 db 6.28319E+7 0.00000E+0 12 ns Prepared by Silicon Labs Clock Jitter Tool v0.21 on 2015-11-17 15:05:55 GMT-06:00
PCI Express Report Page 27 of 27 26 GEN3 Common Clock 3.1 27 GEN3 Common Clock 3.1 28 GEN3 Common Clock 3.1 29 GEN3 Common Clock 3.1 2 MHz 0.01 db 4.48000E+5 1.40000E+1 5 MHz 1 db 1.15300E+7 1.15000E+0 10 MHz 0 db 6.28319E+7 0.00000E+0 12 ns 2 MHz 2 db 6.02000E+6 7.30000E-1 5 MHz 1 db 1.15300E+7 1.15000E+0 10 MHz 0 db 6.28319E+7 0.00000E+0 12 ns 4 MHz 0.01 db 8.96000E+5 1.40000E+1 5 MHz 1 db 1.15300E+7 1.15000E+0 10 MHz 0 db 6.28319E+7 0.00000E+0 12 ns 4 MHz 2 db 1.20400E+7 7.30000E-1 5 MHz 1 db 1.15300E+7 1.15000E+0 10 MHz 0 db 6.28319E+7 0.00000E+0 12 ns 30 GEN3 Data Clock 3.1 2 MHz 0.01 db 4.48000E+5 1.40000E+1 10 MHz 0.5 db 1.65700E+7 1.75000E+0 31 GEN3 Data Clock 3.1 2 MHz 1 db 4.62000E+6 1.15000E+0 10 MHz 0.5 db 1.65700E+7 1.75000E+0 32 GEN3 Data Clock 3.1 2 MHz 2 db 6.02000E+6 7.30000E-1 10 MHz 0.5 db 1.65700E+7 1.75000E+0 33 GEN3 Data Clock 3.1 4 MHz 0.01 db 8.96000E+5 1.40000E+1 10 MHz 0.5 db 1.65700E+7 1.75000E+0 34 GEN3 Data Clock 3.1 4 MHz 2 db 1.20400E+7 7.30000E-1 10 MHz 0.5 db 1.65700E+7 1.75000E+0 35 GEN3 Data Clock 3.1 5 MHz 0.01 db 1.12000E+6 1.40000E+1 10 MHz 0.5 db 1.65700E+7 1.75000E+0 36 GEN3 Data Clock 3.1 5 MHz 1 db 1.15300E+7 1.15000E+0 10 MHz 0.5 db 1.65700E+7 1.75000E+0 37 GEN3 Data Clock 3.1 2 MHz 0.01 db 4.48000E+5 1.40000E+1 10 MHz 2 db 3.38000E+7 7.30000E-1 38 GEN3 Data Clock 3.1 2 MHz 1 db 4.62000E+6 1.15000E+0 10 MHz 2 db 3.38000E+7 7.30000E-1 39 GEN3 Data Clock 3.1 2 MHz 2 db 6.02000E+6 7.30000E-1 10 MHz 2 db 3.38000E+7 7.30000E-1 40 GEN3 Data Clock 3.1 4 MHz 0.01 db 8.96000E+5 1.40000E+1 10 MHz 2 db 3.38000E+7 7.30000E-1 41 GEN3 Data Clock 3.1 4 MHz 2 db 1.20400E+7 7.30000E-1 10 MHz 2 db 3.38000E+7 7.30000E-1 42 GEN3 Data Clock 3.1 5 MHz 0.01 db 1.12000E+6 1.40000E+1 10 MHz 2 db 3.38000E+7 7.30000E-1 43 GEN3 Data Clock 3.1 5 MHz 1 db 1.15300E+7 1.15000E+0 10 MHz 2 db 3.38000E+7 7.30000E-1 44 GEN3 Separate Clock SRNS 3.1 4 MHz 2 db 1.20400E+7 7.30000E-1 4 MHz 2 db 1.20400E+7 7.30000E-1 10 MHz 3 db 6.28319E+7 7.07107E-1 Prepared by Silicon Labs Clock Jitter Tool v0.21 on 2015-11-17 15:05:55 GMT-06:00
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