Computer-Aided Design (CAD) Logic Synthesis Tutorial. Prepared by Ray Cheung

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Computer-Aided Design (CAD) Logic Synthesis Tutorial Prepared by Ray Cheung

What is Logic Synthesis? Logic Synthesis - Takes the circuit description at the RTL level and generates an optimal implementation in terms of an interconnection of logic gates.

Tutorial Outline: SIS Tutorial Combinational & Sequential Circuit Rewiring Tutorial ATPG technique RAMBO, REWIRE, RAMFIRE, GBAW GBAW lab exercises

Part 1: Introduction to SIS package Sequential Interactive Synthesis

Outline : SIS Elements inside SIS Interactive SIS vs. SIS library BLIF & SIS file formats X-Windows based SIS (XSIS) SIS automated scripts Technology mapping libraries

What is SIS? SIS is an interactive tool for synthesis and optimization of sequential and combinational circuits. Why it is so important? It serves as a framework for various algorithms can be tested and compared. It can be used standalone or integrated into other programs. It provides a well-defined library for us. The current RAMBO and GBAW are both implemented on top of the SIS library.

The History of SIS It was born in UC Berkeley Built on top of MIS package which is a logic optimization system in 90. The latest SIS version is sis-1.4. It is particularly useful for synthesizing and optimizing sequential circuits.

SIS Family It contains NOVA (State assignment) JEDI (State assignment) STAMINA (State minimization) SRED (State minimization) ESPRESSO (Boolean function minimization) BLIF2VST (BLIF to structural VHDL translator) VST2BLIF (structural VHDL to BLIF translator) XSIS (a graphical interface to SIS)

SIS Package

SIS Capabilities All the capabilities are controlled interactively by the user, include: State minimization State assignment Optimization for area and delay by using retiming Optimization by using the standard algebraic and Boolean combinational techniques from MISII,

SIS Shell Input your command here

SIS commands?

Our concern SIS Library

SIS Library Model the circuit Model the logic gates

A closer look SIS library

Library Path

BLIF Format What is BLIF? Berkeley Logic Interchange Format Is it the same as our *.sis files? Yes, just different extension. It is used to describe a logic-level level hierarchical circuit in textual form. The circuit can be an arbitrary combinational or sequential network.

BLIF files

BLIF format Exercise : Can you sketch the circuit?

XSIS

SIS Scripts Some carefully crafted standard scripts of misii operations. Used to automate the process and guide the optimization steps. They are developed by experienced experts. Any novice designer can easily use these scripts.

SIS Scripts

Genlib Format Delay and load information Used to specify library gates in SIS. Logic function

How to Map Circuit? Technology mapping issue Map by mcnc1.genlib

How about mcnc11.genlib? Map into 2-input gates

Interactive Environment

Mapping Library

Script.boolean Reduce the number of literals

Script.algebraic

Area calculation A) F = X YZ X + X YZX YZ + XZ 8 literals (X,, Y, Z, X, X, Y, Z, Z, X, Z) B) F = X Y(Z X + Z ) Z ) + XZ = X Y X Y + XZ 4 literals (X,, Y, X, Z)

Part 2: Combinational and Sequential Circuit Synthesis

Outline : Circuit Synthesis Logic Synthesis Fundamentals Combinational Circuit It has outputs that depend only on the current value of the inputs. Sequential Circuit Composes of combinational logic blocks and registers. It has outputs that may depend upon the past value as well as the current input values.

Logic Synthesis Fundamentals Refer to CEG 5330 course materials Cover, minimum cover, prime, The Espresso Minimizer Cube, Kernel, Co-kernel Two-level logic minimization Multi-level level logic minimization Sequential vs. Combinational Technology mapping,

Combinational Circuit

Synchronous circuit & its representation

SDC, ODC & EDC Satisfiability don t t care sets (SDC) It captures conditions which can never happen in the network. Observability don t t care sets (ODC) It captures changes which may occur without affecting the outputs. External don t t care sets (EDC) User-specified specified

State Transition Graph (STG) Each state is symbolic STG and its logic representation

STG Manipulations From STG to netlist State minimization Produce a machine with fewer states State assignment Assign a binary code for each symbolic state A latch is used to store each bit of the binary code STG extraction Inverse of state assignment Extract the STG from the logic netlist SIS command: stg_extract

Sequential Circuit Optimization State minimization & assignment of FSM Retiming techniques Reduce cycle time Minimize the number of registers Cycle-Time Minimization Resynthesis Particularly use between registers Rewiring

Rewiring Example Both logic gates and the number of FF are reduced.

Part 3: Rewiring Engines

Outline : Rewiring Engines Introduction ATPG Technique RAMBO REWIRE RAMFIRE Graph based Technique GBAW

Introduction Alternative Wiring What is Alternative Wire? Add a redundant wire into a circuit (so as to make) Another wire (target( wire) ) becomes redundant Remove target wire. Without changing the circuit functionality. 2 fundamentally different approaches RAMBO/RAMFIRE Automatic Test Pattern Generation (ATPG)-based GBAW Graph-based

Alternative Wiring - Application 1 Useful in different areas Logic Optimization final circuit becomes smaller c g 4 b g 1 redundant d g 5 O 1 e alternative c g 2 g 6 w a wire d w r O 2 a g 7 g 8 g 9 b g 3 f target wire b g 1 d g 5 O 1 e c g 2 g 6 c a g 8 g 9 O 2 b g 3 f

Alternative Wiring - Application 2 Circuit Partitioning the interconnect wires between partitions is reduced from 3 to 2. e f a b O 1 e f a b O 1 c d O 2 c d O 2 (a) An alternative wire in an irredundant circuit (b) No gain for logic synthesis, but gain for partitioning

ATPG 1 0 0 1 0 a b c d e f 1 0 s-a-1 1 (0/1) (0/1) Logic Circuit A Fault A Fault value A Test Vector Test Vector: (a, b, c, d, e) = (1, 0, 0, 1, 0)

Definition Transitive Fanin & Fanout If there is a path connected from ni to nj ni is the transitive fanin of nj nj is the transitive fanout of ni Propagation path ni nj

Definition Transitive Fanin & Fanout Cone Fanin Cone of wire w are the wires connecting the transitive fanins of ni Fanout Cone of wire w are the wires connecting the transitive fanouts of nj ni w nj Transitive Fanin Transitive Fanin Not Transitive

Definition Dominator d of a wire w All paths from w to any primary outputs have to pass through d Dominator w PO Not Dominator

Definition Controlling Value It determines the output value of a gate without considering the side inputs 0 for AND gate 1 for OR gate Sensitizing/non-controlling value Complement of controlling value 1 for AND gate 0 for OR gate

Testing Single Stuck-at (SSA) fault The wire will always give 0 or 1 Stuck-at fault Test Propagate the fault Set the dominators side inputs to sensitizing value to propagate the fault to any primary output Activate the fault Set the wire under test to 0 for s-a-1 s 1 or 1 for s-a-0s

Testing c 1 b d 0 g1 g4 0 g5 0 0 For Propagate Activate d->g6 stuck the fault at 1 test o1 e c d 1 a b 1 f g2 0 0 D g3 g6 D g7 1 D 0 g8 D 1 g9 D o2 Test for stuck-at 1

Testing The values are called Mandatory Assignment (MA) MAs must be satisfied The MAs that used to propagate the fault are called Observability Mandatory Assigment (OMA)

Testing c 1 b d 0 g1 g4 0 g5 0 0 Green is OMA!!! o1 e c d 1 a b 1 g2 0 0 D g3 g6 D g7 1 D 0 g8 D 1 g9 D o2 f

How RAMBO works c g4 b d g1 g5 o1 e c d g2 g6 g7 g8 g9 o2 a b f g3 Wire becomes redundant

REWIRE Proposed by Professor S.C.Chang in Fast Boolean Optimization by Rewiring in 1996 ATPG-based algorithm Speed: GBAW > REWIRE > RAMBO AWs Searching Power: RAMBO > REWIRE > GBAW

How REWIRE works c b d e c d g1 g2 g4 g5 g6 1. Set all the dominators side input to non-controlling value 0 2. Recursive forward implication 3. Recursive backward implication g7 g8 g9 o1 o2 Every node is a destination node, n d Find OMA for n d Generate an array of wt a b f g3 1 1

How REWIRE works (2) c b d e c d g1 g2 g4 g5 g6 0 g7 g8 1. Transitive fanin cone of n d 2. Transitive fanout cone of n d 3. k levels of transitive fanin of dominator of n d g9 o1 o2 Every node is a destination node, n d Find OMA for n d Generate an array of wt Filter irredundant wire from wt a b f 1 1 g3 1 1 17 wires in wt

How REWIRE works (3) If one of the input node of an AND {OR} gate has an OMA of 0 {1}, all other input wires are irredundant c b d e c d g1 g2 g4 g5 g6 0 g7 All the direct inputs of an AND {OR} gate are irredundant if the AND gate has an OMA of 0 {1} g8 g9 o1 o2 Every node is a destination node, n d Find OMA for n d Generate an array of wt Filter irredundant wire from wt a b f 1 1 g3 1 1 12 wires in wt

How REWIRE works (4) v c b d e c d a b f 0 0 1 1 g1 g2 0 g3 0 D_ 1 g4 g5 g6 0 0 D_ g7 D_ 1 g8 D_ Suppose we consider d->g6 g9 D_ o1 o2 Every node is a destination node, n d Find OMA for n d Generate an array of wt Filter irredundant wire from wt Perform stuck-at-fault test at wt Determination of alternative wires Finally, we get the alternative wire g1->g6 and o1->g6 for target wire d->g6

RAMFIRE - Single-Pass Redundancy Addition And Removal Operation 1: Given a target wire w t to be removed, which redundant wires, when added, will make w t redundant? Operation 2: After the addition of a redundant wire w a, which wires become redundant and hence removable? RAMFIRE identifies redundant wires in one pass without trial-and and-error search.

GBAW * -- No Need of Boolean Knowledge. High Locality properties on AWs observed in benchmarks (analogy: RISC v.s. CISC) Topological locality: 96% 1 st. Aws are 2-local2 Pattern locality: very uneven appearance of AWs patterns Application locality: probably no need to try all patterns A Pre-analyzed Pattern (graph) - based AW Scheme Methodology: pattern matching Advantage: Fast, As Effective No need for porting ATPG package Equally easy to do backward transformations *received Honorable Mention Award of IEEE International VLSI Design 2000

GBAW Most AWs are close to target wires Graph-based AW scheme Search alternative wire by isomorphism between local sub-networks and the pre-defined patterns. Easy for both forward and backward search. Use Configuration to denote a Boolean network. No need of Boolean implication/operations. Powerful in finding alternative wires and Very Fast!

GBAW Configuration A Boolean network G with its sub-network S. Below shows the mapping from network to configuration. Node y define as a triplet (op, d - (y), d + (y)) op is the Boolean operator (AND, OR, NAND, NOR) d - (y)) is the in-degree of y, d + (y)) is the out-degree of y. (AND, dc, dc) both fanins or fanouts are also don t t care. a b g 1 S g 2 g 3 G f 1 c d f 2 (a) Boolean network G (AND,2,1) (AND,2,2) (AND,dc,1) (AND,dc,dc) a g 1 g 2 a g 1 g 2 b c b c D 1 D 2 (b) A configuration of S (c) Another configuration of S

How GBAW works Pattern Matching No Boolean implication a g1 g2 2-Local Pattern b g3 g4 g7 g8 c g6 g5

0-local pattern Bold line target wire Dotted line alternative wire 0-local means the edge distance between target and alternative wire is 0. (op 1,k,dc) (dc,dc,dc) a 1 a 2 g 1 g 2 a k g 3 (op 3,k,dc) g 4 (dc,dc,dc)

1-local patterns AND AND (or NAND) a (op 1,dc,1) g 1 (op 2,dc,dc) g 2 (a) Case 1-1, op 1 =AND, op 2 =AND (or NAND); or op 1 =OR, op 2 =OR(or NOR) (op 1,k,dc) a 1 g 1 a 2... a k (op 2,k,dc) g 2 (b) Case 1-2, op 1 =AND, op 2 =AND (or NAND); or op 1 =OR, op 2 =OR(or NOR) AND AND (or NAND) a (op 1,dc,1) g 1 (op 2,dc,dc) g 2 (c) Case 1-3, op 1 =NOR, op 2 =NAND (or AND); or op 1 =NAND, op 2 =OR(or NOR)

2-local patterns (NOR,dc,1) (NAND,dc,1) (NOR,dc,dc) a g 1 g 2 g 3 (OR,dc,1) (a) Case 2-1 (AND,dc,1) a 1 a 2... a k g 1 g 4 g 2 g 2 (NOR,dc,dc) or (OR,dc,dc) Forward alternative wire Backward alternative wire (AND,k,dc) (b) Case 2-2 dc (OR,dc,h) (AND,t,1) (OR,dc,dc) 1... t-1 dc (OR,s,dc) (AND,h,dc) dc 1... s-1 dc dc (c) Case 2-3 (AND,s,dc)

Forward & Backward capabilities Implement Reverse Searching Increase GBAW s search power Forward Order Search from fanin to fanout Search from fanout to fanin Backward Order

Verification of 2-local 2 pattern x (a*x) y ((a*x) *y) z (((a*x) *y) *z) Target wire exists: g 3 = (((a*x) *y)*z) *y)*z) = (((a +x +x )*y)*z) )*y)*z) = ((a y + x y)*z) )*z) Alternative wire exists: g 3 = ((a y) *( *(x y) *z) = original g 3

Pattern Clusters a What is the meaning of pattern Clusters? g3 2-Local Pattern (Cluster 3 Set 6a) a g1 g2 g3 b1 g5 b2 b g4 2-Local Pattern (Cluster 1) bn

Pattern Locality 1200 1000 800 600 400 200 0 6000 5000 4000 3000 2000 1000 0 5691 Matching Found 2843 448 13 181 11 12 13 111 131 Pattern Name Matching Found 21 23 24 26 2_2a 2_3a 2_4a 2_5 2_n3_2 2_n3_4 2_n3_6 Very uneven appearance of AW patterns Top figure: Pattern Locality for 1-1 Local Bottom figure: Pattern Locality for 2-2 Local Pattern Name

Rewiring GUI interface Benchmark: small.blif The current user interface allows users interactively locate any possible redundant rewires in the circuit by using either GBAW, RAMBO and REWIRE.

Rewiring GUI interface Benchmark: des.blif The system is built on top of Java and C languages.

Rewiring Framework application? application 3 Area 2 5? Power 4? 1 Delay efficient rewire engine design methodology RAMBO / GBAW / Logical/Physical Co-Design Applicationindependent rewiring engine provides efficient routines for for logic logic alternative exploration

Part 4 Implementation details Checking fan-in and fan-out and lab exercises Using sr_local2_n3_6.c as an example, we show how the code run and how the node is named

main() [program initialization] sram(); [statistic reporting] [statistic reporting]

sram() for a wire <node1< -> fanout1> transformxxx xxx(wire); [match different AW patterns]

For greedy simplification sram() for a wire <node1< -> fanout1> transformxxx xxx(wire); [match different AW patterns] [transform the first matched pattern]

For incremental perturbation sram() for a wire <node1< -> fanout1> transformxxx xxx(wire); [match different AW patterns] [record all matched patterns] transform_incremental(); [transform the min-cost pattern]

Check if any element with the structure is NULL (Function is_node_ok is defined in sr_util.c) /*** fanout1 ***/ if (!is_node_ok(fanout1)) if (gate_type(fanout1)!= T_NOT) fo1_not = fanout1; fanout1 = node_get_fanout(fo1_not, 0); node1 Not Not yet yet checked checked Checking Checking Require Require further further checking checking Checked Checked fanout1 a g 1 g 2 g 3 g 5 b g 4 if (!is_node_ok(fanout1)) if (gate_type(fanout1) == T_PO) if (node_num_fanin(fanout1)!= 2) if (node_num_fanout(fanout1)!= 1) /*** fanout2 ***/ fanout2 = node_get_fanout(fanout1, 0); if (!is_node_ok(fanout2)) if (gate_type(fanout2) == T_PO) if (node_num_fanout(fanout2)!= 1) if (node_num_fanin(fanout2)!= 2) /*** fanout3 ***/ fanout3 = node_get_fanout(fanout2, 0); if (!is_node_ok(fanout3)) if (gate_type(fanout3) == T_PO)

Check whether the fan-out of fanout1 is a NOT gate /*** fanout1 ***/ if (!is_node_ok(fanout1)) if (gate_type(fanout1)!= T_NOT) fo1_not = fanout1; fanout1 = node_get_fanout(fo1_not, 0); if (!is_node_ok(fanout1)) if (gate_type(fanout1) == T_PO) if (node_num_fanin(fanout1)!= 2) if (node_num_fanout(fanout1)!= 1) node1 fanout1 a g 1 g 2 g 3 g 5 b g 4 /*** fanout2 ***/ fanout2 = node_get_fanout(fanout1, 0); if (!is_node_ok(fanout2)) if (gate_type(fanout2) == T_PO) if (node_num_fanout(fanout2)!= 1) if (node_num_fanin(fanout2)!= 2) /*** fanout3 ***/ fanout3 = node_get_fanout(fanout2, 0); if (!is_node_ok(fanout3)) if (gate_type(fanout3) == T_PO)

/*** fanout1 ***/ if (!is_node_ok(fanout1)) Rename fanout1 to fo1_not if (gate_type(fanout1)!= T_NOT) fanout1 now become the fan-out of the NOT gate fo1_not = fanout1; fanout1 = node_get_fanout(fo1_not, 0); if (!is_node_ok(fanout1)) if (gate_type(fanout1) == T_PO) if (node_num_fanin(fanout1)!= 2) if (node_num_fanout(fanout1)!= 1) node1 fo1_not fanout1 a g 1 g 2 g 3 g 5 b g 4 /*** fanout2 ***/ fanout2 = node_get_fanout(fanout1, 0); if (!is_node_ok(fanout2)) if (gate_type(fanout2) == T_PO) if (node_num_fanout(fanout2)!= 1) if (node_num_fanin(fanout2)!= 2) /*** fanout3 ***/ fanout3 = node_get_fanout(fanout2, 0); if (!is_node_ok(fanout3)) if (gate_type(fanout3) == T_PO)

Again check if any element with the structure is NULL /*** fanout1 ***/ if (!is_node_ok(fanout1)) if (gate_type(fanout1)!= T_NOT) fo1_not = fanout1; fanout1 = node_get_fanout(fo1_not, 0); if (!is_node_ok(fanout1)) if (gate_type(fanout1) == T_PO) if (node_num_fanin(fanout1)!= 2) if (node_num_fanout(fanout1)!= 1) node1 fo1_not fanout1 a g 1 g 2 g 3 g 5 b g 4 /*** fanout2 ***/ fanout2 = node_get_fanout(fanout1, 0); if (!is_node_ok(fanout2)) if (gate_type(fanout2) == T_PO) if (node_num_fanout(fanout2)!= 1) if (node_num_fanin(fanout2)!= 2) /*** fanout3 ***/ fanout3 = node_get_fanout(fanout2, 0); if (!is_node_ok(fanout3)) if (gate_type(fanout3) == T_PO)

Fan-out of fanout cannot be Primary Output /*** fanout1 ***/ if (!is_node_ok(fanout1)) if (gate_type(fanout1)!= T_NOT) fo1_not = fanout1; fanout1 = node_get_fanout(fo1_not, 0); if (!is_node_ok(fanout1)) if (gate_type(fanout1) == T_PO) if (node_num_fanin(fanout1)!= 2) if (node_num_fanout(fanout1)!= 1) node1 fo1_not fanout1 a g 1 g 2 g 3 g 5 b g 4 /*** fanout2 ***/ fanout2 = node_get_fanout(fanout1, 0); if (!is_node_ok(fanout2)) if (gate_type(fanout2) == T_PO) if (node_num_fanout(fanout2)!= 1) if (node_num_fanin(fanout2)!= 2) /*** fanout3 ***/ fanout3 = node_get_fanout(fanout2, 0); if (!is_node_ok(fanout3)) if (gate_type(fanout3) == T_PO)

fanout1 must have 2 fan-in(s) /*** fanout1 ***/ if (!is_node_ok(fanout1)) if (gate_type(fanout1)!= T_NOT) fo1_not = fanout1; fanout1 = node_get_fanout(fo1_not, 0); if (!is_node_ok(fanout1)) if (gate_type(fanout1) == T_PO) if (node_num_fanin(fanout1)!= 2) if (node_num_fanout(fanout1)!= 1) node1 fo1_not fanout1 a g 1 g 2 g 3 g 5 b g 4 /*** fanout2 ***/ fanout2 = node_get_fanout(fanout1, 0); if (!is_node_ok(fanout2)) if (gate_type(fanout2) == T_PO) if (node_num_fanout(fanout2)!= 1) if (node_num_fanin(fanout2)!= 2) /*** fanout3 ***/ fanout3 = node_get_fanout(fanout2, 0); if (!is_node_ok(fanout3)) if (gate_type(fanout3) == T_PO)

fanout1 must have 1 fan-out /*** fanout1 ***/ if (!is_node_ok(fanout1)) if (gate_type(fanout1)!= T_NOT) fo1_not = fanout1; fanout1 = node_get_fanout(fo1_not, 0); if (!is_node_ok(fanout1)) if (gate_type(fanout1) == T_PO) if (node_num_fanin(fanout1)!= 2) if (node_num_fanout(fanout1)!= 1) node1 fo1_not fanout1 a g 1 g 2 g 3 g 5 b g 4 /*** fanout2 ***/ fanout2 = node_get_fanout(fanout1, 0); if (!is_node_ok(fanout2)) if (gate_type(fanout2) == T_PO) if (node_num_fanout(fanout2)!= 1) if (node_num_fanin(fanout2)!= 2) /*** fanout3 ***/ fanout3 = node_get_fanout(fanout2, 0); if (!is_node_ok(fanout3)) if (gate_type(fanout3) == T_PO)

Name fanout2 be the fan-out of fanout1 /*** fanout1 ***/ if (!is_node_ok(fanout1)) if (gate_type(fanout1)!= T_NOT) fo1_not = fanout1; fanout1 = node_get_fanout(fo1_not, 0); if (!is_node_ok(fanout1)) if (gate_type(fanout1) == T_PO) if (node_num_fanin(fanout1)!= 2) if (node_num_fanout(fanout1)!= 1) node1 fanout1 fanout2 fo1_not a g 1 g 2 g 3 g 5 b g 4 /*** fanout2 ***/ fanout2 = node_get_fanout(fanout1, 0); if (!is_node_ok(fanout2)) if (gate_type(fanout2) == T_PO) if (node_num_fanout(fanout2)!= 1) if (node_num_fanin(fanout2)!= 2) /*** fanout3 ***/ fanout3 = node_get_fanout(fanout2, 0); if (!is_node_ok(fanout3)) if (gate_type(fanout3) == T_PO)

Check if any element with the structure is NULL /*** fanout1 ***/ if (!is_node_ok(fanout1)) if (gate_type(fanout1)!= T_NOT) fo1_not = fanout1; fanout1 = node_get_fanout(fo1_not, 0); if (!is_node_ok(fanout1)) if (gate_type(fanout1) == T_PO) if (node_num_fanin(fanout1)!= 2) if (node_num_fanout(fanout1)!= 1) node1 fanout1 fanout2 fo1_not a g 1 g 2 g 3 g 5 b g 4 /*** fanout2 ***/ fanout2 = node_get_fanout(fanout1, 0); if (!is_node_ok(fanout2)) if (gate_type(fanout2) == T_PO) if (node_num_fanout(fanout2)!= 1) if (node_num_fanin(fanout2)!= 2) /*** fanout3 ***/ fanout3 = node_get_fanout(fanout2, 0); if (!is_node_ok(fanout3)) if (gate_type(fanout3) == T_PO)

Fan-out of fanout2 cannot be Primary Output /*** fanout1 ***/ if (!is_node_ok(fanout1)) if (gate_type(fanout1)!= T_NOT) fo1_not = fanout1; fanout1 = node_get_fanout(fo1_not, 0); if (!is_node_ok(fanout1)) if (gate_type(fanout1) == T_PO) if (node_num_fanin(fanout1)!= 2) if (node_num_fanout(fanout1)!= 1) node1 fanout1 fanout2 fo1_not a g 1 g 2 g 3 g 5 b g 4 /*** fanout2 ***/ fanout2 = node_get_fanout(fanout1, 0); if (!is_node_ok(fanout2)) if (gate_type(fanout2) == T_PO) if (node_num_fanout(fanout2)!= 1) if (node_num_fanin(fanout2)!= 2) /*** fanout3 ***/ fanout3 = node_get_fanout(fanout2, 0); if (!is_node_ok(fanout3)) if (gate_type(fanout3) == T_PO)

Number of fan-out of fanout2 must be 1 /*** fanout1 ***/ if (!is_node_ok(fanout1)) if (gate_type(fanout1)!= T_NOT) fo1_not = fanout1; fanout1 = node_get_fanout(fo1_not, 0); if (!is_node_ok(fanout1)) if (gate_type(fanout1) == T_PO) if (node_num_fanin(fanout1)!= 2) if (node_num_fanout(fanout1)!= 1) node1 fanout1 fanout2 fo1_not a g 1 g 2 g 3 g 5 b g 4 /*** fanout2 ***/ fanout2 = node_get_fanout(fanout1, 0); if (!is_node_ok(fanout2)) if (gate_type(fanout2) == T_PO) if (node_num_fanout(fanout2)!= 1) if (node_num_fanin(fanout2)!= 2) /*** fanout3 ***/ fanout3 = node_get_fanout(fanout2, 0); if (!is_node_ok(fanout3)) if (gate_type(fanout3) == T_PO)

Number of fan-in(s) of fanout2 must be 2 /*** fanout1 ***/ if (!is_node_ok(fanout1)) if (gate_type(fanout1)!= T_NOT) fo1_not = fanout1; fanout1 = node_get_fanout(fo1_not, 0); if (!is_node_ok(fanout1)) if (gate_type(fanout1) == T_PO) if (node_num_fanin(fanout1)!= 2) if (node_num_fanout(fanout1)!= 1) node1 fanout1 fanout2 fo1_not a g 1 g 2 g 3 g 5 b g 4 /*** fanout2 ***/ fanout2 = node_get_fanout(fanout1, 0); if (!is_node_ok(fanout2)) if (gate_type(fanout2) == T_PO) if (node_num_fanout(fanout2)!= 1) if (node_num_fanin(fanout2)!= 2) /*** fanout3 ***/ fanout3 = node_get_fanout(fanout2, 0); if (!is_node_ok(fanout3)) if (gate_type(fanout3) == T_PO)

Name fan-out of fanout2 be fanout3 /*** fanout1 ***/ if (!is_node_ok(fanout1)) if (gate_type(fanout1)!= T_NOT) node1 fanout1 fanout2 fanout3 fo1_not a g 1 g 2 g 3 g 5 b g 4 fo1_not = fanout1; fanout1 = node_get_fanout(fo1_not, 0); if (!is_node_ok(fanout1)) if (gate_type(fanout1) == T_PO) if (node_num_fanin(fanout1)!= 2) if (node_num_fanout(fanout1)!= 1) /*** fanout2 ***/ fanout2 = node_get_fanout(fanout1, 0); if (!is_node_ok(fanout2)) if (gate_type(fanout2) == T_PO) if (node_num_fanout(fanout2)!= 1) if (node_num_fanin(fanout2)!= 2) /*** fanout3 ***/ fanout3 = node_get_fanout(fanout2, 0); if (!is_node_ok(fanout3)) if (gate_type(fanout3) == T_PO)

Check if any element with the structure is NULL node1 fanout1 fanout2 fanout3 fo1_not a g 1 g 2 g 3 g 5 b g 4 /*** fanout1 ***/ if (!is_node_ok(fanout1)) if (gate_type(fanout1)!= T_NOT) fo1_not = fanout1; fanout1 = node_get_fanout(fo1_not, 0); if (!is_node_ok(fanout1)) if (gate_type(fanout1) == T_PO) if (node_num_fanin(fanout1)!= 2) if (node_num_fanout(fanout1)!= 1) /*** fanout2 ***/ fanout2 = node_get_fanout(fanout1, 0); if (!is_node_ok(fanout2)) if (gate_type(fanout2) == T_PO) if (node_num_fanout(fanout2)!= 1) if (node_num_fanin(fanout2)!= 2) /*** fanout3 ***/ fanout3 = node_get_fanout(fanout2, 0); if (!is_node_ok(fanout3)) if (gate_type(fanout3) == T_PO)

fanout3 itself cannot be Primary Output /*** fanout1 ***/ if (!is_node_ok(fanout1)) if (gate_type(fanout1)!= T_NOT) node1 fanout1 fanout2 fanout3 fo1_not a g 1 g 2 g 3 g 5 b g 4 fo1_not = fanout1; fanout1 = node_get_fanout(fo1_not, 0); if (!is_node_ok(fanout1)) if (gate_type(fanout1) == T_PO) if (node_num_fanin(fanout1)!= 2) if (node_num_fanout(fanout1)!= 1) /*** fanout2 ***/ fanout2 = node_get_fanout(fanout1, 0); if (!is_node_ok(fanout2)) if (gate_type(fanout2) == T_PO) if (node_num_fanout(fanout2)!= 1) if (node_num_fanin(fanout2)!= 2) /*** fanout3 ***/ fanout3 = node_get_fanout(fanout2, 0); if (!is_node_ok(fanout3)) if (gate_type(fanout3) == T_PO)

gt_fo1 = gate_type(fanout1); gt_fo2 = gate_type(fanout2); gt_fo3 = gate_type(fanout3); Now, let s consider this block of codes Name the other fan-in of fanout2 be fanin1 Check if fanin1 a non-primary output and has only 1 fan-out node1 fanout1 fanout2 fanout3 fo1_not a g 1 g 2 g 3 g 5 fanin1 b g 4 /*** fanin1 ***/ match=0; foreach_fanin(fanout2,j1,temp){ if (temp == fanout1) continue; fanin1 = temp; if (!is_node_ok(fanin1)) continue; if (gate_type(fanin1) == T_PO) continue; if (node_num_fanout(fanin1)!= 1) continue; gt_fi1 = gate_type(fanin1); foreach_fanin(fanin1,j2,temp){ fanin2 = temp; if (!is_node_ok(fanin2)) continue; if (gate_type(fanin2) == T_PO) continue; if (gate_type(fanin2)!= T_NOT) continue; node2 = node_get_fanin(fanin2, 0); if (!is_node_ok(node2)) continue; if (gate_type(node2) == T_PO) continue; foreach_fanin(fanout1,j3,temp){ fanin3 = temp; if (!is_node_ok(fanin3)) continue; if (gate_type(fanin3) == T_PO) continue; if (!strcmp(fanin3->name, node1->name)) continue; if (!strcmp(fanin3->name, node2->name)){ match=1; break; } if (match==1) break; } if (match==1) break; } if (match==1) break; } if (match==0)

gt_fo1 = gate_type(fanout1); gt_fo2 = gate_type(fanout2); gt_fo3 = gate_type(fanout3); Here are 3 nested for-loop (Marco) Name the fan-in of fanin1 to fanin2 fanin2 must be a NOT gate and must be be a Primary Output Name the fan-in of fanin2 to node2 match is a flag that check whether node2 is also fan-in of fanout1 node1 fanout1 fanout2 fanout3 fo1_not a g 1 g 2 g 3 fanin2 g 5 fanin1 b g node2 4 /*** fanin1 ***/ match=0; foreach_fanin(fanout2,j1,temp){ if (temp == fanout1) continue; fanin1 = temp; if (!is_node_ok(fanin1)) continue; if (gate_type(fanin1) == T_PO) continue; if (node_num_fanout(fanin1)!= 1) continue; gt_fi1 = gate_type(fanin1); foreach_fanin(fanin1,j2,temp){ fanin2 = temp; if (!is_node_ok(fanin2)) continue; if (gate_type(fanin2) == T_PO) continue; if (gate_type(fanin2)!= T_NOT) continue; node2 = node_get_fanin(fanin2, 0); if (!is_node_ok(node2)) continue; if (gate_type(node2) == T_PO) continue; foreach_fanin(fanout1,j3,temp){ fanin3 = temp; if (!is_node_ok(fanin3)) continue; if (gate_type(fanin3) == T_PO) continue; if (!strcmp(fanin3->name, node1->name)) continue; if (!strcmp(fanin3->name, node2->name)){ match=1; break; } if (match==1) break; } if (match==1) break; } if (match==1) break; } if (match==0)

Here are also several nested for-loop After performing some checking, we determine whether both node1 and node2 eventually meet at g4 after passing through a NOT gate. Finally, we check whether the combination of logic gates match the possible patterns node1 fanout1 fanout2 fanout3 fo1_not a g 1 g 2 g 3 /*** g4 ***/ /*** cluster a ***/ match=0; foreach_fanout(node1, gen1, fanout11) { if (!is_node_ok(fanout11)) continue; if (gate_type(fanout11) == T_PO) continue; if (!strcmp(fo1_not->name, fanout11->name)) continue; if (node_num_fanin(fanout11)!= 2) continue; foreach_fanout(node2, gen3, fanout12) { if (!is_node_ok(fanout12)) continue; if (gate_type(fanout12) == T_PO) continue; if (node_num_fanin(fanout12)!= 2) continue; if (!strcmp(fanout1->name, fanout12->name)) continue; if (!strcmp(fanout11->name, fanout12->name)){ if (((gt_fo3 == T_NAND) (gt_fo3 == T_AND))&& ( ((gt_fi1 == T_OR)&&(gt_fo2 == T_NAND)&&(gt_fo1 == T_OR)) ((gt_fi1 == T_NOR)&&(gt_fo2 == T_OR)&&(gt_fo1 == T_NOR)) )){ if (gate_type(fanout12) == T_OR){ not = 0; match=1; break; } else if (gate_type(fanout12) == T_NOR){ not = 1; match=1; break; } } else if (((gt_fo3 == T_NOR) (gt_fo3 == T_OR))&& ( ((gt_fi1 == T_OR)&&(gt_fo2 == T_AND)&&(gt_fo1 == T_OR)) ((gt_fi1 == T_NOR)&&(gt_fo2 == T_NOR)&&(gt_fo1 == T_NOR)) )){ if (gate_type(fanout12) == T_NOR){ not = 0; match=1; break; } else if (gate_type(fanout12) == T_OR){ not = 1; match=1; break; } } else if (((gt_fo3 == T_NAND) (gt_fo3 == T_AND))&&( ((gt_fi1 == T_AND)&&(gt_fo2 == T_OR)&&(gt_fo1 == T_AND)) ((gt_fi1 == T_NAND)&&(gt_fo2 == T_NAND)&&(gt_fo1 == T_NAND)) )){ if (gate_type(fanout12) == T_NAND){ not = 0; match=1; break; } else if (gate_type(fanout12) == T_AND){ not = 1; match=1; break; b node2 fanin2 g 5 fanin1 g 4 } } else if (((gt_fo3 == T_NOR) (gt_fo3 == T_OR))&&( ((gt_fi1 == T_AND)&&(gt_fo2 == T_NOR)&&(gt_fo1 == T_AND)) ((gt_fi1 == T_NAND)&&(gt_fo2 == T_AND)&&(gt_fo1 == T_NAND)) )){ if (gate_type(fanout12) == T_AND){ not = 0; match=1; break; } else if (gate_type(fanout12) == T_NAND){ not = 1; match=1; break; } } } if (match==1) break; } if (match==1) break; }

#ifdef WIRE printf("2_n3_6 add: %s to %s\n",fanout11->name, fanout3->name); printf("2_n3_6 rm: %s to %s\n",fo1_not->name, fanout1->name); printf("2_n3_6 rm: %s to %s\n",fanin2->name, fanin1->name); #endif #ifdef TRANSFORM_ALL_AW if (not == 0) do_add(fanout11,fanout3,t_buf,0); else if (not == 1) do_add(fanout11,fanout3,t_not,0); do_rm(fo1_not,fanout1); do_rm(fanin2,fanin1); #endif #ifdef LOGIC_OPTIMIZATION add_aw(node1, fanout1, node1, fanout2, T_BUF,0,12301); #endif return MY_OK; node1 fanout1 fanout2 fanout3 fo1_not If the 2_n3_6 pattern is found, the result will be display in stdout, perform redundancy addition and removal and logic optimization a g 1 g 2 g 3 g 5 fanin1 b node2 fanin2 g 4

Warm-up exercise

Answer of warming up exercise Finding the occurrence of pattern 2_n3_6 in circuit C7552.sis

How to get the answer Consider the code segment in sr_main.c #ifdef NEW_CLUSTER_3 #ifdef WIRE #endif flag1 = transform2_n3_6(node1, fanout1); if (flag1 == MY_OK) { printf("local 2_n3_6: Node %s -> Node %s.\n", node1_name,fanout1_name); After pattern is found, Local 2_n3_6 will be printed to stdout./gbaw.test /test/c7552.sis grep Local 2_n3_6 Number of lines give the number of pattern found

How to get the answer (con( con t) Output Local 2_n3_6: Node [60016] -> Node [61726]. Local 2_n3_6: Node [60292] -> Node [61970]. Local 2_n3_6: Node [60294] -> Node [62480]. Local 2_n3_6: Node [60317] -> Node [62350]. Local 2_n3_6: Node [60319] -> Node [62397]. Local 2_n3_6: Node [60321] -> Node [62289]. Local 2_n3_6: Node [60323] -> Node [62408]. Local 2_n3_6: Node [60365] -> Node [61983]. Local 2_n3_6: Node [60367] -> Node [62433]. Local 2_n3_6: Node [60339] -> Node [62241]. Local 2_n3_6: Node [60341] -> Node [62523]. Local 2_n3_6: Node [60274] -> Node [61806]. Local 2_n3_6: Node [60276] -> Node [61885]. Local 2_n3_6: Node [60270] -> Node [61796]. Local 2_n3_6: Node [60272] -> Node [61859]. Local 2_n3_6: Node [60230] -> Node [61850]. Local 2_n3_6: Node [60226] -> Node [61839]. Local 2_n3_6: Node [60228] -> Node [62027]. Totally 18 pattern is matched

Topological Statistics Exercise To change the Distribution Locality Version into Topological Locality Version & obtain statistics for both versions on circuits starts with C, e.g. C3540.sis, etc Verification of Stat can be found in ICCAD_02.doc document.

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