FZ Forschungszentrum nformatik Microelectronic System Design (SM) Performance Analysis of Sequence Diagrams for SoC Design Alexander Viehl, Oliver Bringmann, Wolfgang Rosenstiel S M UML for SoC Design Workshop Design Automation Conference DAC June, 12th 2005
Overview ntroduction/motivation Analysis Approach Transformation of UML 2/SysML specification Analysis of Communication Dependency Graphs Design Space Exploration Conclusion FZ Forschungszentrum nformatik 2
Motivation /O µc µc µc RAM HW HW A B OCB C D /O Specification of complete SoC by UML 2, add subsystems to existing solutions by UML specification nclusion of the target architecture Determination of the performance of a modeled system at the design stage Early validation and analysis of the system integration Detection of integration mistakes in system specification Reduction of the design time Accelerates evaluation of distributed embedded systems FZ Forschungszentrum nformatik 3
Motivation(2) /O µc µc µc RAM HW HW /O Analysis model allows combination of UML specifications with analytic results of existing P and libraries Structured reuse of qualified P, platform based design Evaluation of system using environment models like event streams without simulation Structural analysis enables recognition of conflicts due to shared media Generating optimized topologies Automated design space exploration FZ Forschungszentrum nformatik 4
Analysis Approach Specification Sequence Diagram Structured Classes Transformation Behavioural Transformation Structural Extraction Analysis Models Communication Dependency Graph Structural Model FZ Forschungszentrum nformatik 5
Semantics of Communication Dependency Graphs Nodes 1, 2 nitial synchronization point S 1 R 1 R Blocking receive 6, 7 1,3 S Non-blocking Send 3,5 S 2 R 2 Edges 1,4 13,17 e com Communications R 3 C 3 S 3 13,17 e cdg Control Flow Edges e cdg represent the control flow between nodes Edge weights l min, l max represent min. and max. latency between nodes or communication latency FZ Forschungszentrum nformatik 6
Transformation of Sequence Diagrams to CDG dentification of communication events Setting synchronization behavior relating to message type Summation of activity durations including method calls between communication events, flattening call hierarchy Edge weights represent min/max execution time Considering combined fragments, inserting relations between paths nserting loop boundaries and marking priorities of the edges ncluding referenced sequence diagrams in transformation 3,5 S 1 S 2 6, 7 1, 2 R 1 R 2 1,3 1,4 13,17 R 3 C 3 S 3 FZ Forschungszentrum nformatik 7
Structural Extraction Definition of structural/ architectural alternative mappings using UML structured classes/sysml assemblies Extracting properties like shared media access and stereotypes Delays for communication channels in library or as tagged values Refinement allows iterations of analysis cycles nclusion of architecture as constraint for the communication and conflict analysis Design space exploration using different designs for behavior and structure ECU ECU OCB sensor OCB <<CAN>> sensor ECU ECU FZ Forschungszentrum nformatik 8
Analysis Approach Specification Sequence Diagram Structured Classes Transformation Analysis Models Behavioural Transformation Communication Dependency Graph Structural Extraction Structural Model Analysis Communication and Conflict Analysis FZ Forschungszentrum nformatik 9
Analysis of CDG are synchronization points (SP) S 1 R 1 S 1, R 1 are SP, if 6, 7 latency(path min ({, R 3 } S 1 )) 1,3 S 2 R 2 latency(path max ({, } )) S 3 R 1 1,4 13,17 C 3 R 3 S 3 Synchronicity condition: min. path to S max. path to R Synchronization equation to calculate (min, max) slack time Slack values are used for further analysis like WCRT, /O ratio or detection of possible conflicts Negative slack value represents violated synchronicity condition, possible data loss FZ Forschungszentrum nformatik 10
Example Communication Analysis R 1 R 4 7,11 C 4 34 3,5 S 1 S 2 S 3 5,13 4, C10 2 10 4,6 Transformation to system of equations (using slack values): Min time to wait: x i : min. path to S, max. path to R 2 S 4 Max time to wait x i : max. path to C 3 3,4 S R 3, min. path to C1: x1 = 3 2 = 1 x1 = 5 1 = 4 C2: x2 = 3 + 4-6 = 1 x2 = 5 + 10-4 = 11 C3: x3 = 3 + 4 + 5-2 = 10 x3 = 5 + 10 + 13-1 = 27 C4: x4 = 6 + x2 + 11 (1 + x1 + 11) = 2 x4 = 4 + x2 + 20 (2 + x1 + 7) = 25 C1 C1: x1 = 4 + 5 + 32 (7 + x4 + 3) = 6 x1 = 10 + 13 + 34 (11 + x4 + 2) = 42 R R Negative min. slack represents a violated synchronization condition Communication latency defined by architectural description, additional parameter for communication analysis FZ Forschungszentrum nformatik 11
Example Conflict Analysis (1) Overlaps of the starting intervals of communication can lead to conflicts on shared media Using slack values to determine the intervals when communications take place Overlaps are possible even if no conflict can appear Communications can be separated by the control flow Consider the sequential order of the communication Traversing the CDG to create the relating Communication Scheduling Graph CSG Channel latencies included in conflict analysis R 1 R 4 7,11 34 C 4 3,5 4,6 S 1 4, 10 C 2 10 S 2 S 4 S 3 5,13 C 3 C 2 C 3 C 4 5 10 15 20 25 R 2 R 3 3,4 ntervals for the starting time of communications FZ Forschungszentrum nformatik 12
Example - Conflict Analysis (2) 3,5 4,6 R 1 R 4 7,11 34 S 1 S 2 4, 10 C 2 10 R 2 S 4 3,4 R 3 C 4 5,13 C 3 S 3 1. Communication Scheduling Graph 2. Check paths 3. Coloring of the conflict graph R 2 S [ 4 [11, 20] 1, 2, 3, 4 ] C 2 [R,S 1,R 2,R 3 ] 1 [5, 13] C 3 C 4 [R 4,S 2,R 2,R 3 ] C 2 Overlaps of [R intervals 4,S 3,R 4,R 3 ] C 3 C 4 Res 1,C 2,C 3 C 3 and C 4 can have C 3 and C 4 potentially parallel! conflict! Res 2 C 4 FZ Forschungszentrum nformatik S 2 S 3 13
Analysis Approach Specification Sequence Diagram Structured Classes Transformation Analysis Models Behavioural Transformation Communication Dependency Graph Structural Extraction Structural Model Analysis Communication and Conflict Analysis Exploration Design Space Exploration FZ Forschungszentrum nformatik 14
Example - Design Space Exploration R 1 R 4 A B C D 7,11 34 3,5 4,6 S 1 S 2 4, 10 C 2 10 5,13 C 4 C 3 S 3 R 2 S 4 R 3 3,4 Conflict graph Res 1 Res 2 C 2 C 3 C 4,C 2,C 3 C 4 Conflict Analysis based on conflict or compatibility graphs Approach can be used with communication duration Leads to design space exploration with different architectural and behavioral designs A B A B OCB OCB C D C D Evaluation of different architectures FZ Forschungszentrum nformatik 15
Conclusion Approach for global performance analysis in platform based design Estimation of the performance of a system/component specified with UML Translation of the behavior to a known analysis model allows combination of UML specifications with results from HW/SW communication analysis and environment models Early conflict analysis allows evaluation of system architectures defined by Structured Classes/ Composites Automated design space exploration by DiSCoE-Tool, allows fast refinement Transformation of analytical results to UML (Sequence Diagrams, Timing Diagrams) Generation of optimized topologies FZ Forschungszentrum nformatik 16