STLC2500D. Bluetooth V2.1 "Lisbon" + EDR. Features. Description

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Bluetooth V2.1 "Lisbon" + EDR Data Brief Features Based on Ericsson Technology Licensing Baseband Core (EBC) Bluetooth specification compliance: V2.1 ( Lisbon ) + EDR HW support for packet types ACL, SCO, esco Adaptive Frequency Hopping (AFH) Lisbon features Encryption Pause/Resume (EPR) Extended Inquiry Response (EIR) Link Supervision Time Out (LSTO) Secure simple pairing Sniff subrating Quality of Service (QoS) - Packet boundary flag - Erroneous data delivery Channel Quality Driven Data Rate (CQDDR) Power Class 2 and Power Class 1.5 (above 4 dbm) transmit power HCI H4 and enhanced H4 Transport Layer Implements Pitch-Period Error Concealment (PPEC) Fully flexible support for a wide range of WLAN and other co-existence scenarios Low power consumption Ultra low power architecture with 3 different low-power levels Dual wake-up mechanism Communication interfaces: UART, SPI, PCM... ARM7TDMI TM CPU On-chip RAM, on-chip ROM Supports 1.65 V to 2.85 V I/O systems Auto calibration (VCO, Filters) Description WBGA48 The STLC2500D is a single-chip Bluetooth solution that is fully optimized for mobile applications such as mobile phones, smart phones, PDAs and portable media players. Power consumption levels are targeted for battery powered devices and the integration allows a cost-effective solution. Manufacturers can easily integrate the STLC2500D to achieve a rapid time to market. Compared to its successful predecessor, the STLC2500C, the STLC2500D supports the Bluetooth specification V2.1 ( Lisbon )+ EDR and further optimizes the RF performances and cost. January 2008 Rev 1 1/5 For further information contact your local STMicroelectronics sales office. www.st.com 5

Overview STLC2500D 1 Overview Based on Ericsson Technology Licensing Baseband Core (EBC) Bluetooth specification compliance: V2.1 ( Lisbon ) + EDR Point-to-point, point-to-multi-point (up to 7 slaves) and scatternet capability Support ACL and SCO links Extended SCO (esco) links Faster connection HW support for packet types ACL: DM1, DM3, DM5, DH1, DH3, DH5, 2-DH1, 2-DH3, 2-DH5, 3-DH1, 3-DH3, 3-DH5 SCO: HV1, HV3 and DV esco: EV3, EV4, EV5, 2-EV3, 2-EV5, 3-EV3, 3-EV5 Adaptive Frequency Hopping (AFH) Channel Quality Driven Data Rate (CQDDR) Lisbon features Encryption Pause/Resume (EPR) Extended Inquiry Response (EIR) Link Supervision Time Out (LSTO) Secure simple pairing Sniff subrating Quality of Service (QoS) Packet boundary flag Erroneous data delivery Transmit power Power Class 2 and Power Class 1.5 (above 4 dbm) Programmable output power Power Class 1 compatible HCI HCI H4 and enhanced H4 transport layer HCI proprietary commands (for example peripherals control) Single HCI command for patch/upgrade download esco over HCI supported Implements Pitch-Period Error Concealment (PPEC) Fully flexible support for a wide range of WLAN and other co-existence scenarios 2/5

Overview Low power consumption Ultra low power architecture with 3 different low-power levels Deep sleep modes, including Host-power saving feature Dual wake-up mechanism: initiated by the Host or by the Bluetooth device Communication interfaces Fast UART up to 4 MHz Flexible SPI interface up to 13 MHz PCM interface Up to 10 additional flexibly programmable GPIOs External interrupts possible through the GPIOs Fast I 2 C interface as master Clock support System clock input (digital or sine wave) at 9.6 MHz, 10 MHz, 13 MHz, 16 MHz, 16.8 MHz, 19.2 MHz, 26 MHz, 33.6 MHz or 38.4 MHz Low power clock input at 3.2 khz, 32 khz or 32.768 khz ARM7TDMI TM CPU Memory organization On chip RAM, including provision for patches On chip ROM, preloaded with SW up to HCI Ciphering support up to 128-bit key Single power supply with internal regulators for core voltage generation Supports 1.65 V to 2.85 V I/O systems Auto calibration (VCO, Filters) Figure 1. STLC2500D block diagram 3/5

Ordering information STLC2500D 2 Ordering information Table 1. Ordering information Order codes Package Packing E-STLC2500D WFBGA48 Tray E-STLC2500DTR WFBGA48 Tape-on-reel 3 Revision history Table 2. Document revision history Date Revision Changes 22-Jan-2008 1 Initial release. 4/5

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