POWER DELIVERY CHALLENGES FOR NEXT GENERATION HIGH PERFORMANCE SOCS Stephen Kosonocky AMD Senior Fellow
AGENDA High Performance APU Overview Voltage rail requirements IP components Fine grain power gating SVI2 interface Package Power Delivery Constraints Physical constraints Potential issues for integrated voltage regulator (IVR) solutions System AC Response Simplified power distribution model Variable frequency clocks Minimal IVR efficiency requirement Concluding remarks 2 Power Delivery Challenges for Next Generation High Performance SOCs November 18, 2012 PWRSOC 2012
HIGH PERFORMANCE APU TRINITY Piledriver Cores Quad CPU Core with total of 4MB L2 2nd-Gen AMD Radeon with DirectX 11 support 384 Radeon Cores 2.0 HD Media Accelerator Accelerates and improves HD playback Accelerates media conversion Enhanced Display Support 3 Simultaneous DisplayPort 1.2 or HDMI/DVI links Up to 4 display heads with display multistreaming Nominal Max Load TDC (A) Voltage (V) Step (A) VDD Variable 50 42 VDDNB Variable 29 37 VDDIO 1.5 3.2 - VDDR 1.2 3.5 - VDDP 1.2 4 - VDDA 2.5 0.75-6 voltage rails 3 Power Delivery Challenges for Next Generation High Performance SOCs November 18, 2012 PWRSOC 2012
Northbridge AMD HD Media Accelerator TRINITY APU 32nm SOI, 246mm2, 1.303BN TRANSISTORS Multiple, mode configurable IP blocks Provides performance on demand DDR3 Controller Dual Channel DDR3 Memory Controller AMD HD Media Accelerator (UVD, AMD Accelerated Video Converter) L2 Cache L2 Cache Unified Northbridge Dual Core x86 Module Dual Core x86 Module GPU AMD Radeon GPU Up to 4 Piledriver Cores with total 4MB L2 HDMI, DisplayPort 1.2, DVI controllers PCIe PCIe PCIe Display PLL DP/ HDMI Display Controller PCI Express I/O 24 lanes, optional digital display interfaces Sebastien Nussbaum, Hot Chips, Palo Alto, 2012 4 Power Delivery Challenges for Next Generation High Performance SOCs November 18, 2012 PWRSOC 2012
AMD HD Media Accelerator TRINITY APU FINE-GRAIN POWER GATING ISLANDS DDR3 Controller GMC UNB L2 Cache L2 Cache GPU Dual Core x86 Module Dual Core x86 Module PCIe PCIe PCIe Display PLL DP / HDMI Display Controller 5 Power Delivery Challenges for Next Generation High Performance SOCs November 18, 2012 PWRSOC 2012
AMD HD Media Accelerator TRINITY FINE-GRAIN POWER GATING ISLANDS (2) DDR3 Controller UVD L2 Cache NB UNB L2 Cache GMC SIMD SIMD GPU VCE Independent on-die power gated islands x86 Module 1 x86 Module 1 SIMD SIMD SIMD SIMD PCIe PCIe PCIe PHYs PCIe Display PLL DP / HDMI DP / HDMI Display Controller 6 Power Delivery Challenges for Next Generation High Performance SOCs November 18, 2012 PWRSOC 2012
AMD HD Media Accelerator TRINITY FINE-GRAIN POWER GATING ISLANDS (3) DDR3 Controller L2 Cache x86 Module 1 UNB L2 Cache x86 Module 1 GMC Misc Graphics SIMD array SIMD GPU array SIMD array SIMD array UVD VCE Independent on-die power gated islands Additional power-down region when all graphics functions are shut down SIMD array SIMD array Power gating is very effective for configuring the power rails for different operating modes! PCIe PCIe PCIe PHYs PCIe Display PLL DP / HDMI DP / HDMI Display Controller Display Controller > 20X leakage current reduction 7 Power Delivery Challenges for Next Generation High Performance SOCs November 18, 2012 PWRSOC 2012
Efficiency (%) PLATFORM POWER SAVINGS AMD SERIAL VOLTAGE INTERFACE 2.0 (SVI2) SVI is the interface which allows the system power management unit to communicate information to and from voltage regulator SVI2 enables quicker power state transitions Faster data transmission rates (33Mhz) Adds regulator response when transition is complete 80+% improvement in 500mV set point change latency over SVI1 Power efficiency features Multiple Power State Indicators sent to regulator PSI0 Current low enough that regulator can shed phases PSI1 Current low enough that regulator can use pulse skipping / diode emulation Load Line trim, offset Ability to adjust DC offset and load line slope based on APU state SVI2 provides a fast power management control path 85 0 Regulator Efficiency vs. Load 1 phase regulation 2 phases regulation 0 Load Current (A) 30 8 Power Delivery Challenges for Next Generation High Performance SOCs November 18, 2012 PWRSOC 2012
CLIENT FM2 MOTHERBOARD Example Client configuration IR3550 PowIRstage ICs from International Rectifier 2X Copper PCB routes High current Ferrite Core Chokes rated up to 60A Minimal resistive losses from VRM to APU are possible Rs < 1mOhm typical (as seen in similar systems) http://www.irf.com Today s system power delivery solutions are highly optimized for low loss and efficiency http://www.pcper.com/news/motherboards/gigabyte- Unveils-Exclusive-Ultra-Durable-5-Technology- Computex-2012 9 Power Delivery Challenges for Next Generation High Performance SOCs November 18, 2012 PWRSOC 2012
TYPICAL PACKAGE CONSTRUCTION Package resources limitations Limited number of metal layers Competing resources z-height constraints Dielectric maximum voltage limits Additional layers or size increase costs Typical package cross-section Metal Resource Usage VDD VDDIO VDDNB VDDPCIE VDDR VDDA Signals VSS Package design is optimized for power delivery and signal integrity 10 Power Delivery Challenges for Next Generation High Performance SOCs November 18, 2012 PWRSOC 2012
PACKAGE LEVEL DISCRETE SURFACE MOUNT INDUCTOR Not as simple as it sounds Thermal heating of inductor I 2 R heating in inductor can be significant Physical height should match die Variations can cause problems Can have poor thermal conduction to heat spreader Power loss of route I 2 R loss in package trace CV 2 f loss in package trace Skin effect loss at high Fsw Thermal Conduction tl Rin tdie Rout Ctrace Integrated voltage regulation presents numerous challenges 11 Power Delivery Challenges for Next Generation High Performance SOCs November 18, 2012 PWRSOC 2012
PACKAGE SPACE CONSTRAINTS Limited number of locations available for passive components Keep-out regions add further limitations Back-side cavity locations can provide some relief At the cost of inductive connections Multi-chip packages Additional cost and complexity Possible IVR components Controller IC Power FETs Inductors Capacitors Physical package size is a major constraint for an integrated voltage regulator solution 12 Power Delivery Challenges for Next Generation High Performance SOCs November 18, 2012 PWRSOC 2012
IVR ROUTING CONSTRAINTS Top level metal already very congested with I/O routing New chip floorplans are required to optimize connections to discrete components Package routes still have significant resistance Resistance in the single digit mohm range for reasonable metal usage Potential routes to discrete inductors An IVR solution must compete with signal routes and external supplies 13 Power Delivery Challenges for Next Generation High Performance SOCs November 18, 2012 PWRSOC 2012
Supply voltage (V) Supply Droop TYPICAL FREQUENCY AND TRANSIENT STEP RESPONSE On-die de-caps Board de-caps 3 rd droop Package de-caps 2 nd droop 1 st droop 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08 1.E+09 1.E+10 1.35 1.30 1.25 1.20 1.15 1.10 1.05 Current excitation frequency (Hz) 1 st droop 2 nd droop 0 25 50 75 100 125 150 175 200 225 250 time (ns) 14 Power Delivery Challenges for Next Generation High Performance SOCs November 18, 2012 PWRSOC 2012
TYPICAL MICROPROCESSOR POWER DELIVERY NETWORK Simplified power distribution lumped model MB Package Die R MB L MB R pkg1 L pkg1 R pkg2 L pkg2 R die L die DVdd(t) VRM C MB C pkg C die i die (t) R MB L MB R pkg1 L pkg1 R pkg2 L pkg2 R die L die Different resonance frequencies (100s of MHz KHz) Sudden changes in load (i die (t)) cause undershoot/overshoot in supply De-cap added at different levels to suppress this supply noise On-die de-cap typically < 100nF per voltage rail Not enough to satisfy the demands of a high performance processor Significantly more will require expensive MIM cap technology IVR designs will require large filter capacitance Package mounted capacitors would have similar ESL as today s VRM based designs Transient response to noise would be very similar between an IVR and non-ivr solution 15 Power Delivery Challenges for Next Generation High Performance SOCs November 18, 2012 PWRSOC 2012
NON-IVR SOLUTIONS FOR DI/DT NOISE 1 st droop occurs very fast ~5ns from onset of current step Caused by the depletion of the low ESL on-die decoupling capacitance Variable frequency clocks can provide high speed adaptation to di/dt events at low cost VFCG PLL dynamically reduces the CPU clock when supply goes below a threshold > 5% performance increase for same power supply > 10% power saving at same performance level Techniques like variable frequency clocks can reduce the need for very high speed regulator response Variable frequency clock enabled Variable frequency clock disabled Alain Artieri: Embedded Multicore in Mobile Platforms, presented at the Power/Performance Optimization of Many-core Processor SoCs, ISSCC Forum, San Francisco, Feb 2012. 16 Power Delivery Challenges for Next Generation High Performance SOCs November 18, 2012 PWRSOC 2012
Efficiency SINGLE PHASE POWER DELIVERY EXAMPLE Today s VRM efficiencies can be very high Does not include PWM controller power High quality power components Low DCR inductor Low loss PCB routes Switching Frequencies 200KHz 1MHz Losses to board component I 2 R DCR loss I 2 R PCB route loss Multiple phases can further reduce losses 96% 94% 92% 90% 88% 86% 84% 82% 80% 78% 0 10 20 30 Load Current (A) +90% Efficiency across wide load range typical today VRM Component 17 Power Delivery Challenges for Next Generation High Performance SOCs November 18, 2012 PWRSOC 2012
Normalized Frequency Frequency Degredation SYSTEM CONSTRAINED POWER SENSITIVITY TO VRM POWER EFFICIENCY Example Fmax vs. Power FMAX 5% Lower Efficiency 1.2 1 0.8 0.6 0.4 0.2 0 0 0.2 0.4 0.6 0.8 1 Normalized Power Envelope 4.5% 4.0% 3.5% 3.0% 2.5% 2.0% 1.5% 1.0% 0.5% 0.0% Performance impact of power delivery efficiency can be significant, especially at low power points 18 Power Delivery Challenges for Next Generation High Performance SOCs November 18, 2012 PWRSOC 2012
IVR Efficiency HIGH CURRENT IVR REQUIREMENT Potential IVR based system 12V VR Fixed Voltage IVR1 IVR2 APU 1 st Stage IVR3 IVR5 IVR4 IVR6 Break Even Requirement Assume Today s VRM Efficiency > 90% 1 st stage regulation efficiency needs to be very high to avoid excessive loss Need enough package space to support components for all rails +2 High current rails, +4 low current rails Difficult to accommodate many high current multi-phase designs 100% 98% 96% 94% 92% Minimum IVR Efficiency for 90% Total Efficiency 90% 90% 95% 100% 1st Stage Regulator Efficiency 19 Power Delivery Challenges for Next Generation High Performance SOCs November 18, 2012 PWRSOC 2012
CONCLUDING REMARKS High performance SOC s are integrating more and more IP blocks Additional voltage rails will open up more possibilities for advanced power management Fine grain power gating has proven to be an effective solution for powering down unused IP blocks IVR solutions must compete with computational sprinting techniques SVI2 provides fast power state transitions and power management control Phase shedding Pulse skipping Load line trimming State-of-the-art external VRMs and good board design can provide a high efficiency power delivery solution Present solutions set a very high bar, integrated solutions need a high ROI Package constraints limit number and placement of discrete components on package We don t have unlimited space Variable frequency clocks can provide a low cost solution to di/dt droops High speed regulator response is not a large motivation 20 Power Delivery Challenges for Next Generation High Performance SOCs November 18, 2012 PWRSOC 2012
CONCLUDING REMARKS (CONTINUED) The three most important criteria for an integrated voltage regulator solution: 1. Efficiency 2. Efficiency 3. Efficiency At low cost 21 Power Delivery Challenges for Next Generation High Performance SOCs November 18, 2012 PWRSOC 2012
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