Labratry Exercise 3 Using the PIC18 Until this pint, the user has prgrammed the FPGA Interface Bard using the FTDI and has nt been intrduced t the n bard PIC18F2550 micrcntrller. The purpse f this experiment is t utilize the PIC18 t its full ptential. The user will be able t prgram the serial memry chip and thus cnfigure the FPGA thrugh the PIC, and als prgram the PIC with user cde which can be ruted thrugh the PIC s external IO header t the terminals and thrugh the FPGA. The experiment will create a simple junctin between the DC1_DIR and DC1_CLK terminals and use the PIC18 t prvide a clck signal t ne f the terminals thrugh the external IO header. The signal can then be bserved n the ther terminals. This experiment requires that the user has Xilinx ISE, FPGACnfig, and Micrchip MPLAB installed n their system. All surce cdes are prvided in the accmpanying flder. A) New Xilinx ISE Prject and Surces Create a new prject titled UsingPIC18 and place it in the FPGA Lab Manual\Experiment 3 flder The prject settings shuld assume the use f the XC3S250E and ISim, as in Experiment #1. As usual, add a new Verilg surce titled tp.v. Als add a Verilg surce titled junctin.v This mdule will be identical t the junctin.v mdule used in bth Experiment #1 and Experiment #2. The user is free t either type it up again, cpy the cde frm the previus experiments, r simply use cpy the junctin.v file frm the accmpanying flder and add it as a surce t the prject. B) tp.v The sle purpse f tp.v will be t call a single junctin.v mdule and prvide it with tw inut signals Inputs/Outputs Add inut DC1_DIR as the input signal t which the PIC will supply a clck Add inut DC1_CLK as the bservable utput signal Call a junctin.v mdule named J1 with the abve input and utput, and ctrl and dir values f 1 C) User Cnstraint File junctin J1 (.a(dc1_clk),.b(dc1_dir),.ctrl(1),.dir(0) );
- T avid ging thrugh the PlanAhead tl, the user cnstraint file fr this experiment is prvided in the prject. It cntains the lcatins and IO standards fr the tw DC mtr pins. The fllwing is an excerpt frm the file. NET "DC1_CLK" LOC = "p77" IOSTANDARD = LVCMOS33 ; NET "DC1_DIR" LOC = "p31" IOSTANDARD = LVCMOS33 ; This tp.ucf file is prvided in the accmpanying flder and can simply be pasted int the user s prject flder and added as a surce thrugh Add Cpy f Surce D) Generating Bit File At this pint, with J1 and tp.ucf under the tp.v hierarchy, the bit file can be generated and the prject can be clsed E) Creating PIC18 User Cde Open up MPLAB and create a new prject titled PIC18UserCde Create a new main.asm surce file which will cntain a blinking pin n the PIC18 When creating user cde fr the PIC18 n the FPGA Interface Bard, it s imprtant t make sure that the user des nt alter the state f any f the fllwing pins: RA4, RB0, RB1, RC7 as they cnnect t the SPI bus and may affect the bard s ability t prgram the serial chip and/r cnfigure the FPGA. It s advised that the user nly use the IO pins available n the external IO male header. In main.asm, begin by adding the necessary include parameter #include <p18f2550.inc> Add the necessary cunter values and write a shrt functin fr the PIC18 If the user is nt familiar, please refer t lab experiments fr the Micrcntrller bard fr instructins n writing assembler cde Set the cde s rigin as 0x2500 It s very imprtant that all user cde written fr the PIC18 n the FPGA Interface Bard has an rigin f 0x2500. This is dne with the fllwing statement befre any instructins. rg 0x2500 Set the TRIS value f the RB7 pin as 0 t cnfigure it as an utput with the fllwing instructin TRISB,7 Next create a label and cntinue by setting RB7 t high, then calling the, then setting it t lw, and calling the, then a gt statement which wuld jump back t the label An example f a main.asm is attached at the end f this lab, and a wrking prject is als added in the accmpanying flder
F) Exprting the User Cde Having cmpiled the assembly cde in MPLAB, a special prcedure must be fllwed t exprt this cde t a recgnizable frmat which may be appended t the PIC s default firmware By using the exprt feature (File>Exprt..) in MPLAB, exprt the cde frm 0x2500 t the end f file withut the Cnfiguratin Bits, EEPROM, r User ID Exprt this file as lab3user.hex in a memrable lcatin and clse the prject G) Appending the User Cde t PIC18 Firmware Launch FPGACnfig Click n Open Hex File.. and lad the recently exprted user cde The HEX File Selectin bx shuld shw the name f the user s hex file Click Append Hex File t FPGA Prgramming Firmware and save the new hex file in anther memrable lcatin as lab3full.hex The Cnfiguratin Status shuld shw that the firmware was saved with the name f yur chice If FPGACnfig des nt perfrm the append fr example the sftware freezes it is likely because the user cde was nt exprted as required. If this ccurs, clse FPGACnfig (End Task may be required) and repeat the exprt as described in Sectin F abve Nte that the accmpanying flder prvides the Xilinx ISE Design prject, the MPLAB prject, all f the hex files and all f the bit files H) Lading the New Firmware nt the PIC18 Having appended the user cde t the firmware, it must nw be placed nt the PIC18 While hlding the Btlader buttn beside the PIC, pwer n the bard in PIC/PIC PROG mde (bth switches high) and let g f the Btlader buttn Click n Dwnlad Firmware t PIC18 in FPGACnfig t bring up Micrchip s PDFSUSB Tl Select the PIC in the drp dwn menu Click Lad HEX File and select the newly created Hex file which cntains bth the firmware and the user cde If a cnfiguratin data warning appears, click yes Click Prgram Device and wait fr the tl t burn the cde nt the PIC After prgramming is cmplete, the tl will acknwledge that everything was written crrectly, hwever the cnfiguratin bit data may fail t write. This can be ignred as it is imprtant fr the final hex file t cntain the cnfiguratin data f the Btlader/Prgrammer cmbinatin Once the prgramming is cmplete, clse PDFSUSB and press the PIC18 RESET buttn n the FPGA Interface Bard
I) Cnfiguring the FPGA in PIC Mde In FPGACnfig, click Cnnect T Device and bserve that the device is fund in PIC Mde If the device is nt detected, try again t cnnect, making sure that the bard is in PIC (nt FTDI) and PIC PROG (nt FPGA ENABLE) mdes n the tw switches in the PRGM mdule Click Open Bitstream and select the tp.bit file created in Sectin D abve This file cntains the FPGA cnfiguratin with the single junctin between DC1_DIR and DC1_CLK created earlier At this pint, FPGACnfig shuld lk as belw Click Prgram Bit File T FPGA Nte that the PIC Mde prgramming takes a lnger time than the FTDI mde While the PIC prgrams the serial memry, the PIC LED beside the PIC18 shuld remain lit Once the device is prgrammed, switch the right mst switch t FPGA ENABLE It is nw a gd idea t test the signal n the RB7 pin f the external IO header with a lgic prbe r scillscpe t make sure the pin is blinking as required
J) Sending PIC18 Signals t the FPGA Using a wire with a single female header cnnectin, cnnect the RB7 pin t the DC1_CLK terminal in the DC Mtrs blck in the Driver Bard mdule n the right f the bard Using a lgic prbe r scillscpe, the pulses can nw be bserved in the DC1_DIR terminal as required. Sample assembler cde fr a blinking RB7 #include <p18f2550.inc> cunt1 EQU 0x22 cunt1_1 EQU 0x23 cunt1_2 EQU 0x24 ;start the prgram at address 0x2500 rg 0x2500 main TRISB,7 a_1 bsf call call gt PORTB,7 PORTB,7 a_1 mvlw mvwf mvlw mvwf mvlw mvwf d'1' cunt1 d'35' cunt1_1 d'42' cunt1_2 gt gt gt return cunt1, f cunt1_1, f cunt1_2, f end