Performance Evaluation & Design Methodologies for Automated CRC Checking for 32 bit address Using HDLC Block 32 Bit Neeraj Kumar Misra, (Assistant professor, Dept. of ECE, R D Foundation Group of Institution Ghaziabad, India Email: neeraj.mishra3@gmail.com) ABSTRACT For design methodology of CRC or cyclic redundancy check is very used technique for error checking and shows the transmission reliability we are using the HDLC block. HDLC block is very useful in data communication these block operated in data link layer. For design methodology of CRC is to generate the CRC polynomial using XOR s gate and shift register these polynomial are implement on software Xilinx Plan Ahead 13.1 and verify for simulation result for random testing of CRC bit on receiver side same result are obtained to show that it is more reliable. Keywords CRC, XILINX, HDLC, LFSR, OSI III. Fig a. Network Layer Interaction COMPETITIVE OVERVIEW OF CRC AND HDLC BLOCK I. INTRODUCTION In OSI model first layer is physical layer. This layer takes care of getting data on the wire and off of it again. At the data link layer, we must take this incoming stream of data from higher or lower layers and create frames from it. Handling the data requires a solid protocol that can perform better error checking and more efficient throughputs. That data is performed by HDLC block. Basically ISO termed it as High level Data Link Control (HDLC).HDLC has own standard frame format. In the framing of HDLC one block is CRC [Cyclic Redundancy Checking] it is basically error checking number that the Destination can use to verify that the packet is error free. This is usually done by the data link protocol and calculated CRC is appended to the end of the data link layer frame. In HDLC overview HDLC device contains a fullduplex transceiver with independent transmit and receive sections for bit-level HDLC protocol operations. The core is designed for easy integration into wide range of applications implemented on most ASIC s and FPGA s technologies. Now the controllers generate and detect flags that indicate the HDLC status. They provide 32-bit CRC on data packets using defined polynomial, and recognize the single byte address in the received frame. II. LITERATURE SURVEY Main focus of the survey is to understand the data link layer and develop a protocol which can offer its services to the layer above it i.e. is the network layer and the layer below it i.e. the physical layer. Function of this protocol controller is to perform a number of separate activities like physical addressing, to check for errors, flow control etc. Fig b. Transmit Section of HDLC
Division may be performed in software, it usually performed using a shift register and X-OR gates. The hardware solution for implementing a CRC is much simpler than a software approach. For example for a CRC-32bit is: Fig c. Receiver section of HDLC In transmitting and receiving section of HDLC the packet data are serially, while providing the data transparency through zero insertion and deletion. These controllers generate and detect flags that indicate the HDLC status. They provide 32-bit CRC on data packets using the CRC defined polynomial, and recognize the single byte address in the received frame. CRC 32bit Polynomial [32 bits] = X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X + 1 HEX CODE 04C11DB7 In CRC overview it is powerful method for detecting errors in the received data is by grouping the bytes of data into a block and calculating a Cyclic Redundancy Check (CRC). This is usually done by the data link protocol and calculated CRC is appended to the end of the data link layer frame. The CRC is calculated by performing a modulo 2 division of the data by a generator polynomial and recording the remainder after division Fig e. Software approach of CRC generation Depending upon the data of the MSB register in the Linear Feedback shift register (LFSR), shifting and XOR operations occur. This serial LFSR implementation is converted into a one shot or single cycle operation. Now this approach is converted into polynomial that is CRC polynomial. Suppose polynomial x 3 +x+1 is generated the generated circuit for CRC is shown fig e. IV. Fig d. Modular division of CRC SOFTWARE APPROACH INTENTION OF MODULAR DIVISION OF CRC Fig f. CRC GENERATOR CIRCUIT V. DESIGN METHODOLOGIES OF CRC USING HDLC BLOCK A practical implementation of a decoder also requires a method to initialize the encoder prior to transmission of the first bit of data in a frame, and to flush the encoder after sending the last byte. In the example below (which uses a different representation of the schematics for X- OR gates and shift register elements), the process starts by initializing the encoder with zero bits, by setting the switch to B. Some CRC's initialize the register to a non-
zero value, which can give added detection capability when the first set of bits in a frame may themselves be zero. Then the switch is moved to position A and one data bit enter the encoder for each clock cycle. The data bits are immediately available at the output. After the last bit has been sent, the switch is returned to position B and the contents of the encoder are sent to the output. This is often called flushing the encoder and requires one clock cycle per bit held in the shift register. On reception, the process is reversed. The CRC register is first set to zero (or the initial value on transmission, if non-zero). The bits (this time including the CRC) are fed into the register on each clock cycle. If the CRC contains the value zero (assuming initialization was zero), the CRC is valid, if not it has detected an error. The CRC-32 is able to detect all single errors, all double errors, all odd numbers of errors and all errors with burst less than 32 bits in length. In addition 99.9984 % of other error patterns will be detected. Protocols at the network layer and higher (e.g. IP, UDP, TCP) usually use a simpler checksum to verify that the data being transported has not been corrupted by the processing performed by the nodes in the network. Change the Polynomial to a divisor of size N+1 Make a shift register of size N Align the shift register cells with the divisor so that the cells are located between the bits Put a XOR gate where there is a 1 in the divisor except for the leftmost bit Make a feedback connection from the leftmost bit to the XORs. Fig h. Design Methodology of 32Bit CRC After the packet with the polynomial the remainder comes out to be zero that means the transmission and reception are error free and in case the remainder is not zero that means an error has occurred during the process and hence the packet is discarded and the whole packet is retransmitted. Fig g. Implementation of encoder and decoder Fig i. CRC Checking Method VI. SOFTWARE USED PARAMETER OF CRC Initially, the digital design (block diagram) will be drafted showing the basic functioning of the hardware
in terms of the blocks. This will then be coded in a hardware description language (VHDL). The functioning of the coded design is to be simulated on simulation software (e.g. ModelSim). After proper simulation, the design is to be synthesized and then translated to a structural architecture in terms of the components on the target FPGA device (Spartan 3) and the perform the post-translate simulation in order to ensure the proper functioning of the design after translation. CRC Parameter taken VII. data<=11110000 16bitaddress txaddressinlo<=11110000, txaddressinhi<=11110000, txadrressout<=1111000011110000 clock=1,reset=0, wrtaddresshi=1 wrtaddresslo=1. PERFORMANCE EVALUATION OF CRC CHECKING CRC parameter taken to simulate the simulation software modelsim after the address and the data are attached together, we divide them with a constant polynomial of 32 bits and append the remainder of the division along the data and address. Fig j. Simulation result for CRC at transmit section In this simulation coded in Xilinx software transmitter crc32 bit is 11000110011 that crc 32 bit is verified in same in receiver obtained a crc32<=0000000000000000000000000000000 which indicates an error free transmission and simulation result is shown below Fig k. Simulation result for CRC at receiver section
VIII. FUTURE IMPROVEMENT Design methodology of CRC is checking properly using HDLC block. The main agenda is HDLC it improve performance of HDLC like it more features can be added to increase its utility. There are several modifications, which can further improve its performance. These are listed below- It can be further enhanced to256 Independent, Bidirectional HDLC Channels, Large 16kB FIFO in Both Receive and Transmit Directions and Transmit Packet Priority Setting. IX. CONCLUSION This paper explains an easy and efficient method of generating automated CRC generations for synthesizable use software Xilinx Plan Ahead 13.1. The check frame sequence generation using cyclic redundancy checks CRC-32 to ensure error free transmission. REFERENCE Journal Papers: [1] Neeraj Mishra, Xilinx HDLC Controller Supporting IP over SONET AND Calculation of 16, 32 Bit CRC for 8,16 bit address International Conference on Communications & Electronics 19th 20th October, 2012 Books: [2]. Z.Navabi, VHDL Analysis & Modeling of Digital systems, McGraw Hill Inc., 1993. [3] Behrouz A. Forouzan, Data communications and networking, Tata Mc-graw Hill Publishing Company Limited, 3rd edition [4 ] A.Tannenbaum, Computer Networks, Prentice Hall of India, 1993. [5] K.C&hang, Digiful Design & Modeling with VHDL and Synthesis, IEEE Computer Society Press, 1995. [6] Charles H. Roth, Digital Systems Design Using VHDL, PWS Publishing Company. [7] Douglas L. Perry, VHDL: Programming By Example, McGraw-hill, 3rd edition [8] Shu Lin, Daniel J. Costello, Jr. Error Control Coding: Fundamentals and Applications. Prentice Hall. ISBN 0-13-283796-X.1983. [9] Neeraj Kumar Mishra, Design of HDLC Controller Supporting IP over SONET and Calculation of 16,32Bit CRC,M.Tech diss.2012, Amity University Proceedings Papers: [10] Heidi Joki, Jarkko Paavola and Valery Ipatov Analysis of Reed-Solomon Coding Combined with Cyclic Redundancy Check in DVB-H link layer, 2nd international symopsium on wireless communication systems, page(s) 313-317, publication year: 2005. [11] Yan Sun and Min Sik Kim, A Table-Based Algorithm for Pipelined CRC Calculation, IEEE international conference on communications (icc ).PP 1-5, publication year 2010. [12] Qasim, S.M. Abbasi, S.A. (2003) FPGA implementation of a single-channel HDLC Layer-2 protocol transmitter using VHDL, Proceedings of the 15th International Conference on Microelectronics, IEEE, pp 265-268. [13 ] S. L. Shieh, P. N. Chen, and Y. S. Han, Flip CRC modification for message length detection, IEEE Transactions on Communications,vol. 55, no. 9, pp. 1747 1756, publication year 2007. [14] FPGA implementation of a single-channel HDLC Layer-2 protocol transmitter using VHDL Qasim, S.M.; Abbasi, S.A.; Microelectronics, 2003. ICM 2003. Proceedings of the 15th International Conference [15] Guozheng Li Nanlin Tan State key Lab. of Rail Traffic control and saftey, Beijing J iaotong Univ.,Beijin,china "Design and Implementation of HDLC Protocol and Manchester Encoding based on FPGA in train communication Networking.' Information and Computing (ICIC), 2010 Third International Conference. Theses: