Low energy and High-performance Embedded Systems Design and Reconfigurable Architectures Ass. Professor Dimitrios Soudris School of Electrical and Computer Eng., National Technical Univ. of Athens, Greece dsoudris@microlab.ntua.gr 1
What about Europe? 2
MicroLab: : Profile 3 Professors o o o Prof. Kiamal Pekmestzi Ass. Prof. Dimitrios Soudris Lect. George Economakos 4 Post-doc researchers 7 Ph.D. Students Infrastructure: Hardware, Software and CAD tools Main research topics Embedded systems design, System level design, specification and modelling, Reconfigurable Architectures, Hardware (ASIC & FPGA) implementation of telecom systems and DSP apps 3D IC Integration Cooperation with leading universities, institutes and industry Funding from National, Industrial and EU projects. More 55 projects Running 7th-IST projects: MNEMEE www.mnemee.org and MOSART www.mosart-project.org 3
MicroLab: AWARDS VLSI 2005 Award of 2,000$ sponsored by Intel and IBM, Arizona, USA LPGD project SAMOS 2007 3 rd award 10,000 euros 1st award 5,000 euros 2nd award 3,000 euros AHS 2007 4-th Position for AMDREL project 4
Cooperation Academia & Industry Academia/Institutes IMEC, Leuven, Belgium (strategic partnership) [>10 years!!] TUD: Delft Technical University, Dept. Electrical and Computer Engineering Univ. of Roechester, USA University of Dortmund, Computer Science, Embedded Systems Group Technical Univ. of Eidhoven, The Netherlands University of Gent, Belgium Royal Institute of Technology (KTH) Industry ST Microelctronics, Milano, Italy THALES, France CSEM: Centre Suisse d'electronique et de Microtechnique, Neuchâtel, Switzerland CoWare, Belgium ARTERIS, Paris, France ΙΝΤΡΑCΟΜ Telecom Solutions 5
Embedded Systems 6
Motivation - Vision Current multimedia and wireless network applications Very complex => designed with high-level languages Dynamic Memory (DM) required => several sources of unpredictability: user movements? image features? Final platforms: Portables: limited Resources (e.g. memory, cpu, power) Low power and high performance 7
Methodology for Dynamic Data Type Refinement Management Multimedia and Network Applications Significant improvements in energy consumption >80% Trade-offs of memory footprint, performance, energy consumed in DDT Refinement are possible 8
Custom Dynamic Memory Manager Construction Wireless LAN Application Application: DRR Boundary Tags for every Memory Block Coalescing Memory Blocks Next Fit Algorithm One Pool per Size FIFO Block Order within Pools PROFILING TOOL Physical Memory 9
Customized Dynamic Memory Manager: Reduced Power Consumption Single-functioned Executes a single program, repeatedly Tightly-constrained Low cost, low power, small, fast, etc. Reactive and real-time 84% more Continually than reacts to changes in the system s AMDREL s environment 25% more Must compute certain than results in real-time without delay AMDREL 10
Results for Infineon EasyPort Lower fragmentation level than Lea 2.7.2 Higher performance than the WinXP allocator model 11
Coarse Grained Reconfigurable Architectures For High Performance - DSP Datapath Synthesis Automated Code Mapping and Synthesis C-to-Synthesized Netlist Tool Flow DSP Datapath Synthesis Exploiting 1. Instruction Level Parallelism 2. Inter-Tile Pipelined Execution 3. Intra-Tile Operation Chaining 4. Fast Operation Level Reconfigurability We achieved: Hardware Flexibility + High Performance + Low Area Up to 35% Execution Latency Gains Over CRISP slice Up to 40% Area Gains Over CRISP slice 12
Low Energy FPGA layout Fine-grain Specs -8X8 array -Area: 5.8 X 6.1mm^2 -Up to 330MHz(register-toregister delay) -0.18 um CMOS STM -6 metal layers -Core Power Supply: 1.8V -LSE configuration time: 42ns -Full Configuration time: 2.9us -20 tracks on routing channels I/O PINS -96 Data I/Os -1 Global Reset -1 Global Clock -12-bit Configuration Address Bus -16-bit Configuration Data Bus - Power/Ground pins 13
Design 3D FPGA architectures Architecture level exploration of FPGAs Design an interconnection network based on the connectivity demands Temperature/Power Aware Placement and Routing Alternative interconnection schemes for 3D vias 3D stack: Reduced system size Short interconnects Reduced packaging cost Lower power consumption Higher perfomance 14
CAD Tools for 2D and 3D reconfigurable architectures: MEANDER Design Framework Application description in HDL Synthesis 2D Flow Technology Mapping 3D Flow 2D or 3D Architecture? 2D architecture EX-VPR 3DPRO 3D architecture library 2D P&R PowerModel 3DPower library 3D P&R Bitstream generation Available for on-line execution at http://vlsi.ee.duth.gr/amdrel 15
Case study: MPEG4 Logic Block Memory Block Dual-Port Memory 16 60
MPEG4 implementation: (a) in a 2-D 2 die and into a 3D IC with three dies 2-D die Output from SoCEncounter Cadence tool 17
Current and Future research trends MicroLab Roadmap Static & Dynamic multimedia and network applications System Level modeling, exploration and optimization Run-time resource management Reconfigurable Computing APPLICATIONS METHODOLOGIES AND TOOLS Multi-core architecture Network-on on-chip interconnections FPGAS 3D integrated circuits PLATFORMS SILICON TECHNOLOGY 18
Thank you very much!!! 19