Matoshri College of Engineering & Research Centre Nashik Department of Computer Engineering Class :- Second Year Computer Engineering Sem - 1 Subject :- MICROPROCESSOR ARCHITECTURE UNIT-IV 1 Accumulator based microprocessor example are: Intel 8085 Motorola 6809 A and B None of these C 1 2 EOC stands for: End of conversion Emphasize of conversion End of controller None of these A 1 3 IRR stands for: Interrupt request register Input request register Interrupt Input resolver resolver registe register A 1 4 Which is the commonly used programmable interface and particular used to provide handshaking: 8251 8254 8259 8255 D 2 5 Which provide a mechanism to establish a link between the microprocessor and i/o device: Input interface Output interface Both a and b None of these C 2 7 8 In which the processor uses a protection of the Memory mapped I/O memory memory address to represent I/O ports: I/O mapped Both a and b None of these A 2 9 The standard I /O is also called: I/O mapped I/O Isolated I/O Both a and b None of these C 1 10 In which the processor uses a protection of the memory address to represent I/O ports: Memory mapped I/O I/O memory mapped Both a and b None of these A 2 11 A processor that has 32 address lines can access how many memory locations? 32 4 4giga 32giga C 2 12 A 32TB requires how many address lines? 5 15 35 45 D 2 13 80386 has ---bit address bus? 8 16 32 64 C 2 Page 1
14 80386 has data bus? 8 16 32 64 C 2 15 80386 supports ---levels of protection? 2 3 4 5 C 2 16 AL stand for: Accumulator low Address low Appropriate low Application low A 1 is the most important segment and it 17 contains the actual assembly language Stack Data segment Code segment instruction to be executed by the segment Extra segment B 3 microprocessor: 18 The offset of a particular segment varies from 0000H to 000H to FFFH : FFFFH 00H to FFH 00000H to FFFFFH B 3 19 20 21 Which formula is used to calculate the number of read stall cycles: Which formula is used to calculate the number of write stall cycles: Which formula is used to calculate the number of memory stall cycles Reads* Read miss rate * Read miss Reads* Read miss rate * Read miss Reads* Read miss rate * Read miss Write* (Write Write miss )+write buffer stalls Write* (Write Write miss )+write buffer stalls Write* (Write Write miss )+write buffer stalls Memory access * Cache miss rate * Cache miss Memory access * Cache Cache miss Memory access * Cache Cache miss None of these A 4 None of these B 4 None of these C 4 22 A 16 bit address bus can generate addresses: 32767 25652 65536 none of these C 3 23 The processor 80386/80486 and the Pentium processor uses bits address bus 16 32 36 64 B 2 Page 2
24 CPU can read & write data by using : Control bus Data bus Address bus None of these B 2 Which bus transfer singles from the CPU to 25 external device and others that carry singles from external device to the Control bus Data bus Address bus None of these B 3 26 Which is not the control bus signal: READ WRITE RESET None of these C 2 27 When memory read or I/O read are active data is Input to the processor Output Processor None of these A 1 28 Using 12 binary digits how many unique house addresses would be possible 28=256 212=4096 216=65536 None of these B 4 30 Each memory location has Address Contents Both A and B None of these C 2 31 32 33 The DMA controllers are special hardware embedded into the chip in modern integrate processor that and to the system; The area of memory with addresses near zero are called: The information on the data bus is transferred to the register: Data transfer arbitrate access Both A and B None of these C 4 High memory Mid memory Memory Low memory D 2 MOC MDR VAM CPU B 1 34 80386 has------registers of --- bit each 8 16 32 64 C 2 35 80386 has --- byte prefetch queue 6 16 32 64 B 1 36 System Bus Contains: Address Bus Data Bus Control Bus All of these D 1 37 Microprocessor is the of computer: Hand Heart Brain Leg C 1 38 Microprocessor is fabricated on single chip using: MOS ALU CPU ALL A 39 Which is the components of microprocessor: Register unit Arithmetic and logical unit Timing and control unit All of these D 40 The physical memory of 80386 can be maximum of--- 4MB 4GB 64MB 64TB B 2 Page 3
41 The virtual memory of 80386 can be maximum of------ 4MB 4GB 64MB 64TB D 2 42 80386 does not supports virtual mode of protection TRUE FALSE None All of these B 2 43 is object code compatible with 8086 TRUE FALSE None All of these A 2 44 80386 does have on chip TLB TRUE FALSE None All of these B 2 45 A computer which has the microprocessor as is called as a microcomputer: CPU ALU RU None of these A 46 80386 can be interfaced with ------math coprocessor 80287 80387 A and B None of these C 3 47 80386 can operate in --------------mode Real mode Protected mode Virtual 8086 All A 3 48 In real mode 80386 can access---------------size memory 1MB+64KB 1MB 4GB 1MB+64KB-16B D 4 49 In real mode 80386 uses ------------formula to generate physical address Segment register*10h+effect ive address Segment Segment Segment register+10h*e register*10h*e register+10h+effec ffective address ffective address tive address A 4 50 PC stand for: program counter project counte protect counter planning counter A 1 51 HLD stands for: High Hour Hold None of these C 1 Address Acknowledg Acknowledgment 52 AEN stands for: Address enable A equivalent ment enable equivalent 53 MEMER and MEMW means: Memory read Memory write Both a and b None of these C 2 54 55 The processor of knowing the status of device and transferring the data with matching speeds is called: Which technology using the microprocessor is fabricated on a single chip: Handshaking Peripheral Ports None of these A 3 POS MOS ALU ABM B 2 Page 4
56 57 58 59 60 61 The act of acquiring an instruction is referred as the the instruction: How many bit of instruction on our simple computer consist of one_ How many parts of single address computer instruction : Which is used to store critical pieces of data during subroutines and interrupts: The area of memory with addresses near zero are called: The point where control returns after a subprogram is completed is known as the : Fetching Fetch cycle Both a and b None of these A 2 2-bit 6-bit 12-bit None of these C 2 1 2 3 4 B 1 Stack Queue Accumulator None of these A 2 High memory Mid memory Memory Low memory D 3 Return address Main Address Program Address Current Address A 3 62 How can we make computers work faster? The fetch-execute cycle and pipelining The assembly Both A and B None of these A 3 63 a subsystem that transfer data between computer components inside a computer or Chip Processor Register Bus D 2 between computer: 64 65 Which is called superhighway: Processor Multiplexer Backbone bus None of these C 2 66 The external system bus architecture is created Pascal Dennis Ritchie Charles using from architecture: Babbage Von Neumann D 2 67 Which Bus connects CPU & level 2 cache: Rear side bus Front side bus Memory side bus None of these B 2 68 Which bus carry addresses: System bus Address bus Control bus Data bus B 1 69 A 16 bit address bus can generate addresses: 32767 25652 65536 none of these C 2 70 Page 5
71 The processor 80386/80486 and the Pentium processor uses bits address bus: 16 32 36 64 B 2 72 CPU can read & write data by using : Control bus Data bus Address bus None of these B 73 Which bus transfer singles from the CPU to external device and others that carry singles Control bus Data bus Address bus None of these A 2 from external device to the CPU: 74 Which is not the control bus signal: READ WRITE RESET None of these C 2 75 Which technique is used for main memory array Fully Linear decoding design: decoding Both A and B None of these C 2 76 CS stands for: Cable select Chip select Control select Cable system B 1 77 In linear decoding address bus of 16-bit wide can connect only of RAM. 16 KB 6KB 12KB 64KB B 2 78 The problem of bus confect and sparse address distribution are eliminated by the use of Fully decoding Half decoding Both A and B None of these A 3 address technique: 79 Which is an integral part of any microcomputer system and its primary purpose is to hold Memory unit Register unit A and B None of these A 4 program and data: 80 How many group of memory unit: Four Three Two One B 2 81 Which is the parts of memory unit: Processor memory Main memory Secondary memory All of these D 3 82 Which system communicates with the outside word via the I/O devices interfaced to it: Microprocessor Microcomputer Digital computer None of these B 4 83 84 A computer which has the microprocessor as is called as a microcomputer: The organization of I/O devices create a difference between : CPU ALU RU None of these A 2 Digital computer Micro computer A and B None of these C 2 Page 6
85 How are the successful microprocessor: 8004 5006 4004 All of these C 2 86 The status register is also called the : Condition code register Flag register A and B None of these C 2 87 BIU STAND FOR: Bus interface unit Bess interface unit A and B None of these A 1 88 The subprogram finish the return instruction recovers the return address from the: Stack Queue Accumulator Data register A 89 The register can be divided are: 3 4 5 6 B 1 90 CS Stand for: Code segment Coot segment Cost segment Counter segment A 1 91 Which are the segment: CS: Code segment CS: Code SS: Stack segment segment All of these D 1 92 The acculatator is 16 bit wide and is called: AX AH AL DL A 2 93 The upper 8 bit are called : BH BL AH CH C 2 94 The lower 8 bit are called : AL CL BL DL A 1 95 IP stand for: Industry pointer Instruction pointer Index pointer None of these B 1 96 Which has great important in modular programming: Stack segment Queue segment Array segment All of these A 3 97 How many type of addressing in memory: Logical address Physical address Both A and B None of these C 2 98 Which bus carry addresses: System bus Address bus Control bus Data bus B 2 99 A 16 bit address bus can generate addresses: 32767 25652 65536 none of these C 2 100 The processor 80386/80486 and the Pentium processor uses bits address bus: 16 32 36 64 B 4 101 CPU can read & write data by using : Control bus Data bus Address bus None of these B 4 Page 7
102 Which bus transfer singles from the CPU to external device and others that carry singles Control bus Data bus Address bus None of these A 1 from external device to th 103 Which is not the control bus signal: READ WRITE RESET None of these C 1 104 When memory read or I/O read are active data is Input to the processor : Output Processor None of these A 2 105 When memory write or I/O read are active data is from the processor: Input Output Processor None of these B 3 106 Using 12 binary digits how many unique house addresses would be possible: 28=256 212=4096 216=65536 None of these B 3 107 Each memory location has: Address Contents Both A and B None of these C 1 108 Which is the type of microcomputer memory: Processor memory Primary Secondary memory memory All of these D 2 109 CS stands for: Cable select Chip select Control select Cable system B 1 110 The size of each segment in 8086 is: 64 kb 24 kb 50 kb 16kb A 2 111 The physical address of memory is : 20 bit 16 bit 32 bit 64 bit A 2 112 The address of a memory is a 20 bit address for the 8086 microprocessor: Physical Logical Both None of these A 3 113 tandard I/O uses which control pin on the micro processor: IO/M A 114 A central processing unit, fabricated on a single chip of semiconductor is called: Microprocessor RAM ROM None of these A 3 115 Which is the architecture of microprocessor: CISC RISC All of these None of these C 2 116 CISC stands for: Complex Instruction System Computer Complex Instruction Set Car Complex Instruction Set Computer None of these C 2 Page 8
117 RISC stands for: Reduced Instruction Set Computer Reduced Resource Intergraded Set Instruction Set Computer Computer Resource Instruction System Computer A 2 118 Which is the components of computer: System Bus CPU Memory All of these D 2 119 System Bus Contains: Address Bus Data Bus Control Bus All of these D 2 120 Which process information at a much faster rate Microprocesso ALU Processor than it can retrieve it from memory: r CPU D 2 121 memory system which is discussed later can improve matters in this respect: Data memory Cache memory Memory None of these B 3 122 The fetch-execute cycle is to use a system know as: Assembly line Pipelining Cache None of these B 2 123 The time taken for all stages of the assembly line to become active is called the: Flow through time Clock period Throughput All of these A 4 124 The clock period is denoted by: T p T1+T2+T3------- +T n Pt None of these A 3 125 Ti is the time taken for the ith stage and there are Throughput n stages in the: Assembly line Both A and B None of these B 3 126 Who is the determined by the time taken by the stages the requires the most processing time: Clock period Flow through Throughput None of these A 2 127 The of can assembly line to be I/t p: Clock period Pipelining Throughput Flow through C 2 2.5 Million 1.5 Million 3.5 Million 1.6 Million How many speed of 8088,8085,8086 128 instruction per instruction per instruction per instruction per A 2 microprocessor: second second second second 129 Which is 16 Bit microprocessor: 8088 8086 8085 All of these D 2 Page 9