CoreTile Express for Cortex-A5 For the Versatile Express Family The Versatile Express family development boards provide an excellent environment for prototyping the next generation of system-on-chip designs. Through a range of plug-in options, hardware and software applications can be developed and debugged. The CoreTile Express for Cortex -A5 is a structured ASIC implementation offering: Early Access to the Cortex-A5 MPCore processor. Benchmarking capability. Early device driver and software development. ARM JTAG and Trace connectors for debug support. User logic prototyping with optional FPGA boards. Features Processor Subsystem - Dual Cortex-A5 with VFP and NEON, r0pi-rc0 - L1 Cache 32KB Instr and 32KB Data - L2 Cache 256KB - 100 MHz operation speed - CoreSight support ITM, 8KB ETB AXI Subsystem - Internal AXI 50MHz - External AXI Master port 40MHz - External AXI Slave port 40MHz - PL341 DDR2 memory interface - 1 GB 64-bit SODIMM @ 120MHz - PL354 Static Memory Bus Interface - 32-bit 50MHz to motherboard - Boot from NOR flash on motherboard - HDLCD video controller Expansion support - AXI Master and Slave links to expansion FPGA daugherboard Peripheral set compatible with the Versatile family Debug - ARM JTAG - ARM 32-bit parellel trace Simplified configuration via motherboard - USB flash drive to PC - Fast programming and configuration - Configuration files for system settings - Automated/remote operation Deliverables CoreTile Express A5x2 V2P-CA5x2 daughterboard 1GB DDR2 SODIMM Versatile Express support DVD Example AXI design (additional LTE 3MG required) SelfTest software Debian Linux BSP The implementation contains a dual-core Cortex-A5 MPCore processor with NEON and on-chip controllers for DDR2 memory and HD color LCD. The Architecture for the Digital World
CoreTile Express for Cortex-A5 Architecture CoreTile Express A5x2 architecture diagram When connected to a Versatile Express motherboard the configuration system enables configuration of the CoreTile Express A5x2. Configuration and operation parameters of the daughterboard are defined in a file stored on the motherboard. The daughterboard communicates to the motherboard via the static memory interface for all peripheral and flash memory accesses. The external AXI interfaces have dedicated routing for an optimal prototyping solutuion directly linking the test chip and FPGA (on a separate daughterboard). PART NUMBER: V2P-CA5-0305A www.arm.com/boards All brand names or product names are the property of their respective holders. Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder. The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given in good faith. All warranties implied or expressed, including but not limited to implied warranties of satisfactory quality or fitness for purpose are excluded. This document is intended only to provide information to the reader about the product. To the extent permitted by local laws ARM shall not be liable for any loss or damage arising from the use of any information in this document or any error or omission in such information. Copyright 2011 ARM Ltd. ARM Ltd. www.arm.com UK T: +44 1223 400400 US T: +1 408 576 1500 FRANCE T: +33 1 39 30 47 89 GERMANY T: +49 89 928 615 0 JAPAN T: +81 45 477 5260 KOREA T: +82 31 712 8234 TAIWAN T: +886 2 2627 1681 ISRAEL T: +972 9 7632000 CHINA T: +86 21 62351296 INDIA T: +91 80 5138 4000 SINGAPORE +65 6728 0950 ARM CoreTile Express CA5x2 07.11
CoreTile Express A9x4 For the Versatile Express Family The Versatile Express family development platform provides an excellent environment for prototyping the next generation of system-on-chip designs. Through a range of plug-in daughterboards hardware and software applications can be developed and debugged. The CoreTile Express A9x4 is a daughterboard for use on the Motherboard Express µ ATX for evaluation, and prototyping of the Cortex -A9 processor. It enables: nevaluation of the new ARM Cortex-A9 quad core processor nsystem benchmarking noperating system ports ncustomer peripheral driver development nearly software development CoreTile Express A9x4 for Cortex-A9 The daughterboard uses a TestChip containing a quad Cortex-A9 processor with NEON, and DDR2 memory controller. This provides a high performance sub-subsystem for software development and benchmarking. The external AXI master and slave ports allow user prototyping in the LogicTile Express daughterboards. This is useful when proving peripheral hardware designs, and software/device driver development at near real-time with a real processor. Features nprocessor Subsystem - Quad Cortex-A9 processor each with NEON (r0p1) at 400MHz - L1 Cache 32kInst and 32kData - L2 Cache 512K (L2C-310) - Debug via PTM and CoreSight naxi Subsystem - Internal AXI Fast at 200MHz Slow at 50MHz - External AXI Master 50MHz - External AXI Slave 30 MHz - DMC-341 DDR2 memory 1GB x 32 bit at 266MHz - SMC-354 Static Memory Bus Interface 32bit at 60MHz to motherboard - TrustZone support TZASC (PL280) and TZPC - Boot from NOR Flash or over external AXI nexpansion support - AXI master and slave links to FPGA daughterboard nperipheral set and address space compatible with Versatile family - EB, PB-11MPCore, PB-A8 and PBX nsimplified configuration of system - USB flash drive to PC - Remote power cycling - Fast programming and configuration - Configuration file for system settings - Support for automated/remote operation Deliverables ndaughterboard nversatile Express support DVD nboot monitor software - Retarget of C I/O libraries nself Test software - Peripheral driver example nos support - Linux Debian 2.6.28 - Symbian to follow - WinCE to follow www.keil.com
CoreTile Express A9x4 Architecture Trace/Debug Connector Test Chip Trace/Debug Clock Generator Clocks TestChip Config Quad A9 Cluster L2 Cache Fast AXI Bus Matrix DMC Slow AXI Bus Matrix SMC AXI S mux AXI M mux AXI expansion AXI expansion System Initialisation Controller DDR2 32bit 1GB Interrupts System configuration CoreTile Express A9x4 Architecture diagram Boot Flash and peripherals When connected to a Versatile Express motherboard the configuration system enables programming and updating of the CoreTile Express A9x4. Configuration and operation parameters of the daughterboard are defined in a configuration file stored on the motherboard. The exported AXI interfaces have dedicated routing for an optimal prototyping solution. PART NUMBER: V2P-CA9-0301A The daughterboard communicates to the motherboard via a static memory interface for all peripheral and flash memory accesses. Information in this data sheet is subject to change without notice, and does not represent a commitment on the part of ARM. 2 CoreTile Express A9x4 www.arm.com ARM CoreTile Express A9x4 05.10
CoreTile Express for Cortex-A15 For the Versatile Express Family The Versatile Express family development boards provide an excellent environment for prototyping the next generation system-on-chip designs. Through a range of plug-in options, hardware and software applications can be developed and debugged. The CoreTile Express for the ARM Cortex -A15 is a test chip-based development platform which implements a complete SoC design around the Cortex-A15 MPCore processor. It enables: Architecture exploration with the fast Cortex-A15 processor test chip Boot code, hypervisor, device driver and application software development Software debug and development of software tools through the on-chip CoreSight debug and trace infrastructure Custom SoC IP component prototyping in an adjacent FPGA board Features Processor Subsystem - Dual ARM Cortex-A15 with VFP and NEON r0p0-1.2ghz operating speed - L1 Cache 32KB Instruction and Data - L2 Cache 1MB - Debug support: CoreSight ITM, 8KB ETB AMBA AXI Subsystem - Internal AMBA AXI: NIC301, 128/64-bit, 600MHz - External AMBA AXI: Master port 64-bit, 50MHz - DDR2 memory interface: PL341-2GB 32-bit DDR2 memory - DMAC: PL330, 128-bit - PL354 Static Memory Bus Interface - 32-bit 50MHz to motherboard - Boot from motherboard NOR Flash - HDCLD video controller: 1920 x 1080p, 60Hz Expansion support - AMBA AXI Master link to expansion FPGA daugherboard Peripheral set compatible with the Versatile family Debug - ARM JTAG: 20-way DIL box header - ARM 32-bit parallel trace: dual 38-pin Mictors Simplified configuration via motherboard - System appears as a USB flash drive on a PC - Fast programming and configuration - Configuration text files for system settings - Remote power control via RS232 Deliverables V2P-CA15x2 daughterboard Versatile Express support DVD Example AMBA AXI subsystem design - Additional LogicTile required SelfTest software CoreTile Express A15x2 for Cortex-A15 Linux BSP The Architecture for the Digital World
CoreTile Express for Cortex-A15 Architecture V2P-CA15 CoreTile Debug connectors Test Chip ACP Cortex-A15 Dual MPCore + NEON JTAG CoreSight Debug Logic Trace 40-bit Addr 128-bit Data M DMAC SCC AXI (128-bit) AXI (128) AXI (128) AHB(32) NIC301 AXI bus matrix AXI (64) AXI (32) AXI (64) APB (32) AXI (64) SMC DMC HDLCD AXI MUX 2GB 32-bit DDR2 memory AXI Expansion to LogicTile FPGA board Timer LEDs Switches GPIO SD Card CF Card NOR Flash Real Time Clock Audio Codec Watchdog UART Kbd / Mouse 10/100 Ethernet DVI V2M-P1 Motherboard CoreTile Express A15x2 architecture diagram When connected to a Versatile Express motherboard the CoreTile Express forms the basis of an early access software development platform. Developers can use the system for porting OS kernel or driver code to the Cortex-A15 CPU architecture. A microcontroller-based configuration mechanism provides an easy, USB-based plug-and-play method for programming software, firmware and FPGA images into the system flash memory from an attached PC. The system can be expanded by adding a LogicTile Express board to the second tile site on the motherboard. This adds a large FPGA for prototyping custom logic blocks along side the ARM processor. The exported AMBA AXI interface from the CoreTile has dedicated routing, directly linking the Test Chip and FPGA. This ensures maximum bandwith is available for the user AMBA AXI system. www.arm.com/boards AVAILABILITY: END 2011 PART NUMBER: V2P-CA15-0237A All brand names or product names are the property of their respective holders. Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder. The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given in good faith. All warranties implied or expressed, including but not limited to implied warranties of satisfactory quality or fitness for purpose are excluded. This document is intended only to provide information to the reader about the product. To the extent permitted by local laws ARM shall not be liable for any loss or damage arising from the use of any information in this document or any error or omission in such information. Copyright 2011 ARM Ltd. ARM Ltd. www.arm.com UK T: +44 1223 400400 FRANCE T: +33 1 39 30 47 89 JAPAN T: +81 45 477 5260 TAIWAN T: +886 2 2627 1681 CHINA T: +86 21 62351296 SINGAPORE +65 6728 0950 US T: +1 408 576 1500 GERMANY T: +49 89 456040-20 KOREA T: +82 31 712 8234 ISRAEL T: +972 9 7632000 INDIA T: +91 80 5138 4000 ARM CoreTile Express CA15 11.11