Session 4a Burn-in & Test Socket Workshop 2000 Burn-in Board Design
BURN-IN & TEST SOCKET WORKSHOP COPYRIGHT NOTICE The papers in this publication comprise the proceedings of the 2000 BiTS Workshop. They reflect the authors opinions and are reproduced as presented, without change. Their inclusion in this publication does not constitute an endorsement by the BiTS Workshop, the sponsors, or the Institute of Electrical and Electronic Engineers, Inc. There is NO copyright protection claimed by this publication. However, each presentation is the work of the authors and their respective companies: as such, proper acknowledgement should be made to the appropriate source. Any questions regarding the use of any materials presented should be directed to the author/s or their companies.
Presentations Burn-in Board Design For Manufacturing Aamir Jamil Pycon, Inc. Burn-in Board Design Consideration For High Speed & High Power Devices Aamir Jamil Pycon, Inc. Burn-in Board Design Considerations Tony Valente Unisys Unigen
Burn-In Board Design For Manufacturing 2000 Burn-in and Test Sockets Workshop Aamir Jamil aamir@pycon.com
Agenda Transition in Design Constraints SMT (Surface Mount Technology) contact: Case study Step board: Case Study 10/11/99 2
Transition in Design BIB(Burn-in Board) Devices require Higher speed Lower voltage Design file: 5ZONE2DUT.TLN BoardSim/LineSim, 7.000 HyperLynx volts Probe 1:C(G0).1 1 V/div 0.0 volts -2.000 volts 0.000ns 50 nsec/div 500.000ns Date: Tuesday Dec. 14,1999 Cursor 1, Voltage = 2.52 V, Time = 14.815 ns Cursor 2, Voltage = 275.9 mv, Time = 5.556 ns Delta Voltage = 2.24 V, Delta Time = 9.259 ns 10/11/99 3
Transition in Design Cont BIB(Burn-in Board) Devices require Sockets with Higher pin count BIB design with higher density 10/11/99 4
Transition in Design Cont BIB(Burn-in Board) Devices require More Layers Matched impedance Shorter cycle time Higher efficiencies = better reliability 10/11/99 5
Transition in Design Cont BIB(Burn-in Board) Devices require SMT(Surface Mount Technology) BGA (Ball Grid array) 10/11/99 6
Constraints Board size & thickness Dedicated to 62 mils(10layer MAX with 50 Imped.) BURN-IN BOARD MECHANICAL SPEC. OF THE CIRCUIT BOARD STANDARD 10 LAYER CONSTRUCTION FOR RELIABILITY STYLE OVEN LAYER 1 COMP 50 OHM 5 MIL LAYER 2 PWR 5 MIL LAYER 3 INR 1 46 OHM 5 MIL LAYER 4 INR 2 46 OHM 5 MIL LAYER 5 PWR 5 MIL LAYER 6 PWR 5 MIL LAYER 7 INR3 46 OHM 5 MIL LAYER 8 INR4 46 OHM 5 MIL LAYER 9 PWR 5 MIL LAYER 10 SOLD 50 OHM 1. All Cores are of 1oz Cu 2. Trace Width = 8 Mils 3. Over all board thicknes 62 MILS +/- 10% 4. Impedance is 50 OHMS 5. Material is POLYIMIDE 6. Traces must be running Perpendicular to the adjacent layers in the Dual Stripline only. 10/11/99 7
Constraints Cont SMT Sockets Device contact reliability Socket contact reliability Top probe for testing 10/11/99 8
Constraints Cont Thru-hole sockets Higher drill count Increases layer count Higher aspect ratio required 10/11/99 9
Constraints Cont SMT Components Vias too close to Pads, causes solder bridge and Solder Escape 10/11/99 10
Constraints Cont SMT Components Assembly to use Re-Flow for SMT and Wave solder for Through Hole components. Wave Solder Re-flow Chamber 10/11/99 11
Constraints Cont Power planes Require higher CU count Additional Power planes Signal Layer Require higher number of signal layers Require smaller trace width and line spacing 10/11/99 12
SMT contact: Case study Problem Devices fail randomly in SMT sockets. Diagnosis Contact issues b/w BIB Pads and socket pins Contact issues b/w socket pins and DUT contacts Oxidation on BIB SMT pads 10/11/99 13
SMT contact: Case study Solution High pressure wash and bake BIB BIB Pad cleaning using Alcohol before installing sockets 10/11/99 14
2 Step Board: Case Study Problem Need 70+ Mils of layers on a 62 Mil BIB Non-Solutions Squeezing design creates crosstalk issue Squeezing layers creates impedance issue Step-board Solution 70+ Mils in socket area, 62 Mils connector area Add signal layers only under the socket area 10/11/99 15 5 BIB Thickness 0.062 BIB Thickness 0.070 + 4 TOP VIEW 3 SIDE VIEW 1 3 2 1
Burn-In Board Design consideration for High Speed & High Power Devices 2000 Burn-in and Test Sockets Workshop Aamir Jamil aamir@pycon.com
Agenda Introduction to Design Memory Board Design Logic Board Design Simulation Fabrication & Assembly 10/11/99 2
Introduction to Design Static/Dynamic Static: Constant power to device Dynamic: Signals toggling TDBI (Test During Burn-In) Monitor sign of life from device Compare actual vs. expected Memory/Logic Memory: Read & Write on the same channel Logic: Dedicated output 10/11/99 3
MEM DUT 2 Memory Board Design Device Address inputs I/O Bi-Directional Small Foot Print - High Density Design 150+ devices per bib Load per channel is higher Isolation recommended Rise time controlled by routing techniques ADD I/O 6 7 8 9 10/11/99 4 5 4 3 1 7 6 5 4 3 2 1
Memory cont Routing & Termination Parallel routing yields equal delay AC termination yields low signal loss Yields 10Mhz frequencies Isolation protects from interference AC Term. Parallel Routing Serial Routing 10/11/99 5
2 Logic Board Design Device BIST (Built-In Self Test) Unidirectional channels CLK parameters critical PLL: Noise, Tr, Tf, Jitter Design Large device - Low density Density = Channels dedicated for output Skew: Clocks synchronized with inputs for expected output CLK INPUT OUT DUT 10/11/99 6 5 4 3 1 3 2 1
Logic Board Design Cont Routing & Termination Pre design simulation for routing technique CLK routing point to point for Tr Serpentine routing for limited channels DC termination for better Tr AC termination avoids signal attenuation Impedance matched for device load Serpentine Routing 10/11/99 7
Simulation Specification Rise/Fall time Over/Under shoot Signal Losses Design file: 5ZONE3DUT_NOR.TLN BoardSim/LineSim, HyperLynx 7.000 volts 1 V/div 0.0 volts Probe 1:C(J1).1-2.000 volts 0.000ns 50 nsec/div 500.000ns Date: Wednesday Dec. 15,1999 Cursor 1, Voltage = 3.41 V, Time = 16.667 ns Cursor 2, Voltage = 3.03 V, Time = 83.333 ns Delta Voltage = 379.3 mv, Delta Time = 66.667 ns 10/11/99 8
Simulation Cont Pre-Fabrication Simulation V/T graphs for all critical pins Adjust termination values Measure skew between signals Calculate Signal Integrity crosstalk 5% Accuracy between simulated and actual design Design file: 5ZONE3DUT_NOR.TLN BoardSim/LineSim, HyperLynx 7.000 volts 1 V/div 0.0 volts Probe 1:C(J1).1-2.000 volts 0.000ns 50 nsec/div 500.000ns Date: Wednesday Dec. 15,1999 Cursor 1, Voltage = 3.41 V, Time = 16.667 ns Cursor 2, Voltage = 3.03 V, Time = 83.333 ns Delta Voltage = 379.3 mv, Delta Time = 66.667 ns 10/11/99 9
Simulation Cont 10/11/99 10
Simulation Cont 10/11/99 11
Simulation Cont 10/11/99 12
Simulation Cont BURN-IN BOARD MECHANICAL SPEC. OF THE CIRCUIT BOARD LAYER CONSTRUCTION LAYER 1 COMP 51 OHM 5 MIL PREPREG LAYER 2 GND 8 MIL CORE LAYER 3 INR 1 54 OHM 25 MIL PREPREG LAYER 4 INR 2 54 OHM 8 MIL CORE LAYER 5 VCC 5 MIL PREPREG LAYER 6 SOLD 51 OHM 1. All Cores are of 1oz Cu 2. Trace Width = 8 MILS 4. Over all board thickness 62 MILS +/-10% 5. Impedance is 50 Ohms +/-10% 6. Material is POLYIMIDE 7. Minimum distance b/w the Traces on COMP is 15 MILS 8. Minimum distance b/w the Traces on INR 1 & INR 2 is 25 MILS 9. Direction of Traces on INR 1 & INR 2 must be Perpendicular 10/11/99 13
Simulation Cont Pre-layout simulation What-if scenario Routing methodology for critical parameters Termination selection Component value estimation AC Term. DUT 500 Ohm PIN 10/11/99 14
Simulation Cont Data Td = 2.15nS Clock Td = 3.45nS Skew = 1.3nS Data Td = 1.72nS Clock Td = 2.76nS Skew = 1.04nS Data Td = 1.23nS Clock Td = 2.1nS Skew = 0.87nS Data Td = 0.86nS Clock Td = 1.4nS Skew = 0.54nS Data Td = 0.43nS Clock Td = 0.72nS Skew = 0.29nS 15 MIL 15 MIL 15 MIL 15 MIL 15 MIL L=2" L=2.75" L=2" ck L=2.75" L=2" ck L=2.75" L=2" L=2.75" L=2" ck ck ck 15MIL L=5" CLOCK 1 50 GND 15 MILL L = 26" 15 MILL L = 42" CLOCK 2 CLOCK 3 12 MIL 15MIL 12 MIL 15MIL 12 MIL 15MIL 12 MIL 15MIL 12 MIL L=2" L=2.75" L=2" ck L=2.75" L=2" ck L=2.75" L=2" L=2.75" L=2" Data Td = 3.01nS Clock Td = 3.7nS Skew = 0.69nS ck ck ck Data Td = 3.44nS Clock Td = 4.38nS Skew = 0.94nS Data Td = 3.84nS Clock Td = 5.06nS Skew = 1.22nS Data Td = 4.3nS Clock Td = 5.75nS Skew = 1.45nS Data Td = 4.73nS Clock Td = 6.43nS Skew = 1.7nS 50 GND 15 MIL 13 MIL 13MIL 13 MIL 13 MIL 13 MIL 13 MIL 13 MIL 13 MIL 13 MIL L=2" L=2.75" L=2" ck L=2.75" L=2" ck L=2.75" L=2" L=2.75" L=2" ck ck ck 50 GND Data Td = 7.31nS Clock Td = 8.73nS Skew = 1.42nS Data Td = 6.88nS Clock Td = 8.05nS Skew = 1.17nS Data Td = 6.45nS Clock Td = 7.36nS Skew = 0.91nS Data Td = 6.02nS Clock Td = 6.68nS Skew = 0.66nS Data Td = 5.59nS Clock Td = 6nS Skew = 0.41nS 10/11/99 15
FAT Fabrication Number of layers, drill count/size and impedance requirement add to complexity Assembly Pin count, pin length and mounting affect assembly Test Design probe Verify actual board with schematic 10/11/99 16
Burn-In Board Design Considerations 2000 Burn-in and Test Sockets Workshop Tony Valente PCB Design Manager unisys
Agenda Mechanical Structures Clam shell ( shadow spacing ) Mounting hardware Electrical impact Pitch of pins Routing layers Through Hole Clam shell ( shadow spacing ) More stable mounting structure Surface Mount Buried vias Open routing paths Testability 10/11/9912/29/99 2 unisys
Mechanical Structures Clam Shell Shadow spacing Open Top Ability to move sockets closer than Clam Shell Creates access to heat removal Mounting Hardware Especially needed for SMT devices. Pin pitch Reduces manufacturability 10/11/9912/29/99 3 unisys
Calculating Shadow Spacing X = COS 85⁰ * 1.673 X =.087 * 1.673 X =.146 Shadow Spacing =.394 +.146 Shadow Spacing =.540 Total distance between sockets would the length of the socket (1.555) plus the shadow spacing (.540). In this example the distance is 2.095 minimum between sockets. 10/11/9912/29/99 4 unisys
Electrical Impact Pin pitch Tighter pitch decreases trace width (signal and power) Spacing between rows of pins (in QFPs) decreases routing space Hole diameter for pins (and pad size needed) decrease routing space Routing Layers Decreased trace width may mean using multiple routing layers for Power and Ground. With increased layer counts, overall board thickness will be effected. 10/11/9912/29/99 5 unisys
Through Hole vs. Surface Mount PROs More stable structure (pin vs vias) Access for all pins for testing. CONs Pin lead length Holes for all pins through board. PROs Blind vias would increase routing paths Easier to drill tolerance for vias vs pin diameter. Not limited by board thickness CONs Blind vias limit accessibility for test. More handling needed in assembly. 10/11/9912/29/99 6 unisys