ECE342 Intro. to Embedded Systems Lecture 5: MSP430 Interrupt Ying Tang Electrical and Computer Engineering Rowan University 1
How A Computer React to Inputs? Polling: the processor regularly looks at the input and react accordingly Easy to implement and debug Intensive processing If an event is rare, CPU wastes lots of time checking Processor can t go into low-power mode Interrupt: the processor is interrupted by an event Time effective Energy saving: processor can be asleep most of time Hard to debug 2
Polling vs. Interrupt void main (void) { int j; WDTCTL = WDTPW WDTHOLD; P1SEL =0; P2SEL=0; P1DIR =BIT0; P2DIR&=~BIT1; P2REN =BIT1; P2OUT =BIT1; P1OUT &=~(BIT0); } while (1){ j= P1IN&BIT1; if(j!=2) P1OUT^=0x01; else P1OUT &=~(BIT0); } void main(void) { WDTCTL = WDTPW WDTHOLD;// Stop watchdog timer P1SEL =0; P1DIR =BIT0; //set Port 1.0 output ---LED P1DIR &=~(BIT1); //set Port 1.1 input --- pushbutton } P1REN =BIT1;//enable pull-up resistor on P1OUT =BIT1; P1IE =BIT1;//enable the interrupt on Port 1.1 P1IES =BIT1;//set as falling edge P1IFG &=~(BIT1);//clear interrupt flag //enter LPM4 mode and enable global interrupt _BIS_SR(LPM4_bits + GIE); //Port 1 ISR #pragma vector=port1_vector _interrupt void PORT_1(void) { P1OUT ^=0x01; P1IFG &=~(BIT1); } The details are not important now, we will come back to the interrupt version later and go over it line by line, bit by bit 3
What is an Interrupt Interrupt is an event that will cause the CPU to stop the normal program execution and provide some service to the event Internal interrupt: generated by the hardware circuitry inside the chip and caused by software errors External interrupt: generated when the external hardware asserts an interrupt signal to the CPU Software interrupt: dealing with abnormal situations that occur during program execution, such as illegal opcodes, overflows, divide-by-zero, and underflow 4
Applications Coordinate I/O activities and prevent CPU from being tied up during the data transfer process. Perform time-critical operation one example is process control. Provide a graceful way to exit from the application when a software error occurred. Remind the CPU to perform routine tasks: Keep track of time of day Periodic data acquisition Task switching in a multi-tasking operating system Others 5
Attributes Maskability Maskable interrupts: not desirable under some situations and should be ignored by the CPU Effective only if the general interrupt enable (GIE) bit is set in the status register (SR); otherwise the interrupt is ignored Nonmaskable interrupts: can t be suppressed by clearing GIE Nonmaskable interrupts also require bits to be set/clear in special function or peripheral registers to enable/disable 6
Attributes Priority The MSP430 uses vectored interrupts, each of which has a distinct priority based on its address (higher address, higher priority) Each vector is associated with a unique interrupt in most cases, but some sources share a vector (e.g., TAIFG shares a vector with the capture/compare interrupts for all channels of Timer_A) The priorities are fixed in hardware and can t be changed by the user 7
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What Happens on Interrupts Interrupt Acceptance 9
What Happens on Interrupts Return From Interrupt (c) After return from interrupt return address status register 10
Operating Modes MSP430 is designed for ultra-low-power applications w/ different operating modes The low-power modes LPM0 ~LPM4 are configured w/ the CPUOFF, OSCOFF, SCG0, and SCG1 bits in SR 11
Getting In/Out of LPM An enabled interrupt event wakes the MSP430 from any of the low-power modes Enter an interrupt service routine (ISR): The PC and SR are stored on the stack The CPUOFF, OSCOFF, and SCG1bits are automatically reset Return from the interrupt service routine (ISR): The SR is popped from the stack, restoring the previous operating mode The SR bits stored on the stack can be modified within the ISR returning to a different operating mode when RETI instruction is executed 12
Getting In/Out of LPM Code Example 13
Getting In/Out of LPM Code Example Enter LPM0 Mode Set CPUOFF bit in SR (see ASM code) There is no C instruction to change the value of status register as it does not know about any process registers To do the same, the compiler adds intrinsic called pseudo function to perform a specific function outside of the C language scope (e.g., bis_sr_register()) Check io430.h for such intrinsic functions Exit LPM0 Mode Clear CPUOFF bit in SR (see ASM code) 14
Interrupts on Port 1/Port 2 P1IE, P1IFG, P1IES If a bit in P1IES is set 0, the corresponding bit in P1IFG is set on rising edge on corresponding input pin (P1IN); otherwise, P1IFG is set on falling edge If the interrupt enable bit in P1IE is set, and global interrupts are enabled (i.e., GIE is SR), an interrupt is requested when the corresponding interrupt flag is set. P2IE, P2IFG, P2IES Port 2 interrupt is similar to Port 1 described above 15
Port 1 Interrupt Example Toggle Port 1.0 on each push of Port 1.1 void main(void) { WDTCTL = WDTPW WDTHOLD;// Stop watchdog timer P1SEL =0; P1DIR =BIT0; //set Port 1.0 output ---LED P1DIR &=~(BIT1); //set Port 1.1 input --- pushbutton P1REN =BIT1;//enable pull-up resistor on P1OUT =BIT1; Information for interrupt vectors can be found in msp430f5529.h } P1IE =BIT1;//enable the interrupt on Port 1.1 P1IES =BIT1;//set as falling edge P1IFG &=~(BIT1);//clear interrupt flag //enter LPM4 mode and enable global interrupt _BIS_SR(LPM4_bits + GIE); //Port 1 ISR #pragma vector=port1_vector _interrupt void PORT_1(void) { P1OUT ^=0x01; P1IFG &=~(BIT1); } 16
Port 1 Interrupt Example C ASM 17
Time A 18
Time A Operations 16-bit timer counter Register TAxR increments/decrements (depending on the mode of operation) with the rising edge of the clock signal TAxR can be read or written w/ software Clock sources can be chosen by setting TASSEL bits The chosen clock source can be further divided using TAIDEX bits 19
Time A Operations (cont.) Timer Mode Control Timer Start Timer counts when MC >{0} and the clock source is active When timer mode is either up or up/down, the timer is stopped by setting TAxCCR0=0; otherwise the timer starts when TAxCCR0= nonzero value 20
Time A Registers 21
TAxCTL Time A Control Register 22
TAxCCTLn Time A Capture/Compare Control 23
TAxCCTLn Time A Capture/Compare Control 24
TAxCCRn Register 25
TAxR Register Time A Counter Register 26
TAxIVRegister Time A Interrupt Vector 27
Time A Interrupts Two Interrupt Vectors TAxCCR0 interrupt vector for TAxCCR0 CCIFG TAxIV interrupt vector for all other CCIFG flags and TAIFG Interrupt Priorities TAxCCR0 interrupt has the highest Timer_A priority TAxCCR0 CCIFG flag is automatically reset when the TAxCCR0 interrupt request is served TAxCCRy CCIFG flags and TAIFG flags are prioritized (1-6 in the descending order) 28
Time A Interrupts Compare Mode CAP =0 CCIFG flag is set when TAxR counts to the associated TAxCCRn value This mode is used to generate periodic signals of whose frequency and duty cycle can be altered Capture Mode CAP =1 CCIFG flag is set when a timer value is captured in the associated TAxCCRn register 29
Time A Interrupts Vectors Each timer block has two sets of vectors Timerx_A0 for CCR0; Timerx_A1 for others (x=0, 1, 2) Timer0_A0_Vector Timer0_A1_Vector Timer1_A0_Vector Timer1_A1_Vector Timer2_A0_Vector Timer2_A1_Vector 30
Example Use Timer A CCR0 in the compare mode to trigger LED blink Step 1 set up Timer A0 control register. Let s choose a clock source Set up Timer A0 in Up mode TA0CTL=TASSEL_1+MC_UP Step 2 set up LEDs. A LED is connected with PORT1.0 P1DIR =BIT0 31
Step 3 set up Timer A0 interrupt Enable compare/capture interrupt Set up Timer A0 in the compare mode TA0CCTL0 = 0x10 Step 4 set up TA0CCR0, and have Timer A0 (TA0R) to count to its contents TA0CCR = 12000; Step 5 write the interrupt routine and put it in the predefined program memory #pragma vector=timer0_a0_vector _interrupt void Timer_A(void) { PIOUT^=0x01; } 32