1. (a) 1. (b) T.E. Sem. V [ETRX] Microprocessors and Microcontrollers I Prelim Question Paper Solution Priority modes. 1) Fully Nested Mode : It is a general purpose mode. IR 0 highest priority IR 1 lowest priority Any IR can be assigned to highest priority In that case priority sequence will begin at that IR. e.g. IR 4 has highest priority then IR 0 IR 1 IR 2 IR 3 IR 4 IR 5 IR 6 IR 7 4 5 6 7 0 1 2 3 7 lowest priority 0 Highest priority 2) Automatic Rotation Mode : In this mode, device after being serviced, receives the lowest priority. e.g. IR 4 is just being serviced IR 0 IR 1 IR 2 IR 3 IR 4 IR 5 IR 6 IR 7 3 4 5 6 7 0 1 2 3) Specific Rotation Mode : This mode is similar to Automatic Rotation Mode except that the user can select any IR for the lowest priority, thus fixing all other priorities Addressing Modes : The addressing modes of 8051 are as follows: 1) Immediate addressing Mode: In this mode, data is present as a part of instruction. Here before data, # has to be used. For Eg: MOV A, # 44H 44H placed in A MOV DPTR, # 2500H 2500H placed in DPTR. MOV R2, # 0AAH AAH is placed in R2 reg. 2) Register Addressing Mode: In this type, the name of the register is specified in the instruction itself. The permitted registers are A, R7-R0 of each memory bank. MOV A, R0 move data in R0 into A. MOV R2, A move data in A into R2. 3) Direct Addressing Mode: In this type, the address of internal RAM ( 00 to 7F) and address of SFR ( 80 to FF) is given in the instruction. For Eg: MOV A, 21H the content of RAM loc 21H is moved into A. MOV A, 80H move data from port 0 into A. 4) Indirect Addressing Mode: In this type, registers R0 and R1 are called data pointers as they hold the address of internal RAM locations from (00)H to (7F)H. here, before R0 or R1, @ is used. 1113/Engg/TE/Pre Pap/2013/ETRX/Soln/MPMC_I 1
: T.E. MPMC_I 1. (c) For Example : MOV A, @R0 contents of internal RAM pointed by R0 is moved into A. MOV @R1, #35H data 35 h is moved into RAM whose address is pointed by R1. Indirect addressing is also used for external RAM. For external addressing, indirect addressing is given by using R0 or R1 and by using DPTR. Here, a letter X is used in the mnemonic to indicate external RAM. For Example : MOVX A, @R1 move data from external RAM whose address is pointed by R1 is moved into A. [range is 00 FF]. MOVX @ DPTR, A move data from A into external RAM whose address is pointed by DPTR [range is 0000 to FFFF]. 5) Indexed Addressing Mode: It is used to access data in internal ROM and external ROM ( code memory). In this type, indirect address is given by using A with PC or A with DPTR. Here letter C is used in the mnemonic. For Example : MOVC A, @ A+DPTR content of memory location (Whose address is obtained by adding A & DPTR) is moved into A MOVC A, @ A+PC move contents of memory location (whose address is obtained by adding A with PC) is moved into A. Timing Diagram for I/O Read (Refer Figure (a)) Changes from Memory read : (1) The address is obtained from W, Z temporary register only. (2) IO / M is high and S o, S 1 is 0 1 indicate read operation. (3) The byte read from I/O device is loaded in accumulator only. T 1 T 2 T 3 T 1 T 2 T 3 CLK CLK ALE AD 0 AD 7 A 8 A 15 I0/M S 0 S 1 RD 8-bit Port Address DATA BYTE 8-Bit Port Address (Duplicated) ALE AD 0 AD 7 A 8 A 15 IO /M S 0 S 1 1 RD PORT ADD. (Z) from Acc. to I/O BYTE PORT ADDRESS (w) 1 WR WR Fig. (a) Fig. (b) 2 1113/Engg/TE/Pre Pap/2013/ETRX/Soln/MPMC_I
Timing Diagram for I/O Write (Refer Figure (b)) Changes from Memory Write : (1) The address is obtained from W, Z temporary registers only. (2) IO / M is high and S o, S 1 is 1 0 indicate write operation. (3) The byte to be written in I/O devices is taken from accumulator only. Prelim Question Paper Solution 1. (d) 2. (a) I/O Ports 8051 has four I/O ports: port 0, port 1, port2, port 3. Latch is used to control each port. Different opcode is used to access latch and port. The contents of latch is different from content of port. PORT 2: It is used as I/O port for data like port 1. It is also used to have higher byte memory address during memory expansion. Interrupts Interrupts of 8085 are divided into 2 types. 1. Hardware interrupts and 2. Software interrupts. Interrupt request generated by activating the available interrupt pins on 8085 are called hardware interrupts. The signal is initiated or activated by some external device or circuit which requires some service or attention. The service is provided by p by executing a special set of instructions written as an ISR (Interrupt Service Routine). If the programmer wants to execute a particular ISR at a point in the program then the programmer can write RST n instruction within the program so that the ISR is executed. Such a technique of activating the ISR by writing an instruction within program is called software interrupt. Hardware Interrupts : There are 5 hardware interrupt pins available on 8085. They are TRAP, RST 7.5, RST 6.5, RST 5.5 and INTR. i) TRAP : It is a non maskable interrupt having highest priority. It is edge as well as level sensitive. TRAP is a vectored interrupt. Its service routine starts from memory location 0024 H onwards. ii) RST 7.5 : It is edge sensitive interrupt. It has second highest priority amongst various interrupts. It is maskable through DI or through SIM instruction. RST 7.5 is a vectored interrupt and the location for its service routine is from 003CH onwards. iii) RST 6.5 and RST 5.5 : There are level triggered or level sensitive maskable interrupts. These can also be masked through DI or SIM instruction. Their level must be maintained high so as to get recognized by p. The priority of RST 6.5 and RST 5.5 is 3 rd and 4 th respectively. They are vectored interrupts and the address of their ISR is 0034 H and 002CH respectively. 1113/Engg/TE/Pre Pap/2013/ETRX/Soln/MPMC 3
: T.E. MPMC_I iv) INTR : It is a general purpose level triggered maskable interrupt. It can be masked through DI instruction. It should maintain high level to be recognized by p. It is a non vectored interrupt. Hence in order to get the information about the ISR address p sends INTA. i.e., Interrupt Acknowledge when p execute INTA cycle it expects RST n instruction or a CALL instruction from external hardware circuit or device. 2. (b) 3. (a) Instructions related to Interrupts : (1) EI (Enable Interrupt) : This instruction enables the maskable interrupts (which are not masked through SIM instruction). (2) DI (Disable Interrupt ) : This instruction disables (i.e. masks) all the maskable interrupts (All except TRAP). (3) SIM (Set Interrupt Mask) : This instruction is used to perform the following functions : i) To mask/unmask RST 7.5, RST 6.5 & RST 5.5 interrupts individually. ii) To clear any pending interrupt for RST 7.5 by clearing the RST 7.5 latch. (4) RIM (read interrupt mask) : This instruction gets the following information from interrupt control unit. i) Weather RST 7.5, RST 6.5 & RST 5.5 are internally masked or unmasked. ii) Weather RST 7.5, RST 6.5 & RST 5.5 are pending for service or not. iii) Weather interrupts are internally enabled or disabled. Crystal frequency = 6MHz Operating frequency = 3 MHz 1 1 loads pulse = = 0.33 sec 3MHz Delay = [10 + (FFFEH) (6 + 4 + 4 + 4 + 10) 3 + 10] 0.33 sec Since, loads pulses required by the instructions in given program are 10, 6, 4, 4, 4, 10 7 respectively). Delay = 605.539 msec. and 10 Instruction Cycle The CPU fetches one instruction from the memory at a time and execute it. The essential steps required by CPU to fetch and execute an instruction is called as instruction cycle. Machin Cycle The time required by the microprocessor to complete the operation of accessing memory or Input / Output device is called as a machine cycle. T-state Microprocessor performs an operation in a specific time period i.e. specific clock cycles. Each clock cycle is called as T state. (i) (ii) (iii) (iv) (v) Instruction LDA address LX1 INR M RRC DAD H Mnemonic LDA address LX 1 R P, 16-bit data INR M RRC DAD H Operation A = R P = 16 bit (HL) = (HL) + 1 B n = B n + 1 HL = HL + HL (Address) data OR (M) = (M) + 1 (for n = to 6) B 7 = Cy = B 0 No. of bytes 3 bytes 3 bytes 1 bytes 1 bytes 1 bytes Machine 4 (OF + MR 3 (OF + MR + 3 (DF + MR + 1 (OF) 3 (OF + B1 + + MR + MR) MR) cycles Algorithm A (address) R P 16-bit data NW) M M + 1 or (HL) (HL) + 1 B n B n + 1 (for n = 0 to 6) B1) HL HL + HL 4 1113/Engg/TE/Pre Pap/2013/ETRX/Soln/MPMC_I
3. (b) Flags No flags are affected. No flags are affected. All the flags except carry are modified. Prelim Question Paper Solution B 7 B 0, Cy B 0 Only the carry Only carry flag flag is affected. is affected. No All other flags other flags are are unmodified. modified to reflected the result of operation. Implied address Register address mode mode Addressing Direct Immediate Indirect address mode address mode address mode mode T-State 13 (4 + 3 + 3 10 (4 + 3 +3) 10 (4 + 3 + 3) 4 10 (4 + 3 + 3) + 3) IC 8254 can be used as square wave generator and divide by n counters by operating it in modes 3 and 2. For this, 8254 has be configurid using CWR. Mode 2 : Rate Generation 1. It is a divide by n counter. 2. OUT pin is initially high after control word is written. 3. OUT pin goes low only for 1 clock cycle when count value becomes 1. 4. When GATE is low counting stops and OUT pin forced high. Counter starts from initial count when rising edge arrives at GATE and it can be used to synchronize counter (Case 2). 5. If counter is reloaded with new count then present period is not affected. Counter starts counting with new count only after current count gets over. 6. As it is a generator, it gives continuous waveform. CLK WR Case 1: GATE OUT Case 2 : GATE OUT 1 n = 3 3 3 2 1 0/3 2 1 0/3 2 1 0/3 2 1 2 2 2 3 2 1 0/3 2 1 0/3 2 1 Mode 3 : Square Wave generator 1. OUT pin remains high for half of the count and low for remaining half of the count; if even count is loaded. 2. If ODD count is loaded, then OUT pin remains high for n 1 counts and low for n 1 2 2 counts where n is the value of count loaded. 3. For even count, count decrements by 2 on falling edge of every clock pulses (Case 1). 1113/Engg/TE/Pre Pap/2013/ETRX/Soln/MPMC 5
: T.E. MPMC_I 4. (a) 4. For ODD count on first clock pulse count decrements by 1 and on subsequent clock pulses count decrements by 2. After Terminal count, OUT pin goes low and on first clock pulse count decrements by 3 and on subsequent clock pulses count decrements by 2. (Case 2) 5. On reaching Terminal count pin changes the state, counter is reloaded and process repeats. 6. High level at gate is must for counting. Low level at GATE disables counting and forces OUT pin high. Rising edge at GATE reloads the counter and counting starts. 7. If reloaded with new values, then present period is not affected new value is consider only after present count gets over. It gives continuous waveform being a generator 8. Thus counter of 8254 can work as a square wave generator where period can be controlled by changing the value of count. CLK Special Function Registers: SFRS Address range from 80 to FF H are given to special function registers. Not all of the addresses from 80 to FF H are used for SFRs, and attempting to use an address that is not defined, results in unpredictable results. Following are the SFRs with their internal RAM addresses and utility. i) A Accumulator, Address 0E0 H. ii) B Address iii) DPTR DPH DPL iv) PSW Address WR Case 1 : 1 even GATE count 0 Case 2 : odd count OUT OUT Arithmetic, 0F0 H External data pointer, 83 H 82 H Program status word, 0D0H v) SP Stack pointer, Address 81 H n n = 6 LASTCOUNT n = 7 LASTCOUNT 6 4 2 0/6 4 2 0/6 4 2 0/6 n/2 C.C n/2 C.C 7 6 4 2 0/7 4 2 0/7 6 4 2 0/7 n 1 C.C n 1 2 C.C 2 vi) SBUF Serial port data buffer, Address 99 H. Utility: It is used to hold data byte which is to be transmitted serially hold the data byte received. 6 1113/Engg/TE/Pre Pap/2013/ETRX/Soln/MPMC_I
Prelim Question Paper Solution vii) TMOD Address viii)tcon Address Timer/Counter mode control, 89 H Timer/Counter control, 88 H ix) SCON Address Serial port control, 98 H x) IE Interrupt enable control, Address 0A8 H EA: ET2: ES: ETX: EA - ET2 ES ET1 EX1 ET0 EX0 Enable interrupt bits. Cleared to 0 by program to disable all interrupts. Set to 1 to enable interrupts. Reserved for future use. Enable serial port interrupt, 1: enable 0: disable. Enable timer X overflow interrupt, 1: enable 0: disable. EX1/0:Enable external interrupt 1/0, 1: enable 0: disable. xi) IP register: ( Address 0B8 H) - - PT2 PS PT1 PX1 PT0 PX0 PT2: Reserved for future use. PS: Priority of serial port interrupts. Set/ cleared by program. PTX: Priority of timer X overflow interrupts. PX1/0:Priority of external interrupts 1/0. xii) P0 80 H PORT 0 P1 90 H PORT 1 P2 0A0 H PORT 2 P3 0B0 H PORT 3 xiii) Some of the SFRs are bit addressable also. E.g. CLR A ( byte operation) SETB 0E3 H ( bit operation) Set only bit 3 of accumulator. Other bits are not affected. 1113/Engg/TE/Pre Pap/2013/ETRX/Soln/MPMC 7
: T.E. MPMC_I 4. (b) : 5. (a) 5. (b) : Single Stepping Mode : Single Stepping Operation is implemented in 8051 by using software. In this technique, at a time only one instruction of main program is executed. This is possible in 8051 because interrupt structure of 8051 has 2 properties. a) When 8051 is executing an ISR, it will not respond to another interrupt of equal or lower priority. b) After executing RETI 8051 will execute one instruction of main program and only then it responds to interrupt request. To implement this, following steps are used. a) Make INTO low level triggered. b) Make INTO highest priority. ( IP reg. ). c) The last 3 statements in ISR are given by ISR corresponding to INTO HERE JNB P3.2, HERE Wait state till INTO SAME JB P3.2, SAME goes high to low RET1 Return to main program If second instruction is not there, then only some instruction will be debugged. The INTO pin [P3:2] is kept low normally after executing n th instruction. 8051 enters ISR of INT0, 8051 stays in this ISR until Wait state till INTO is pulsed [low to high and high to low]. Now, 8051 executes RETI and then execute main program. After this it again enters into the same ISR. 8051 stays in this ISR until INTO is pulsed again i.e. one step of main program is executed. Each time INTO is pulsed single stepping operation takes place. i) SCON SFR : 7 6 8 7 3 2 1 0 SM0 SM1 SM2 REN TB8 RB8 TI RI SM0, SM1: SM0 SM1 MODE DESCRIPTION 0 0 0 SHIFT REG. 0 1 1 8 BIT UART 1 0 2 9 BIT UART 1 1 3 9 BIT UART 8 1113/Engg/TE/Pre Pap/2013/ETRX/Soln/MPMC_I
6. (a) Prelim Question Paper Solution SM2: Multiprocessor communication bit. When set to 1, an interrupt is generated if bit 9 of the received data is 1, no interrupt is generated if bit 9 is 0. If set to 1 for mode 1, no interrupt is generated unless a valid stop bit is received. Cleared to 0 if mode 0 is in use. REN: Receive Enable Bit. Set to 1 to enable reception, cleared to 0 to disable reception. TB8: Transmitted bit 8. Set / Cleared by program in modes 2 and 3. RB8: Received bit 8. Bit 8 of received data in modes 2 & 3, stop bit in mode 1. Not used in mode 0. TI: Transmit Interrupt Flag. Set to 1 at the end of bit 7 time in mode 0 and at the beginning of stop bit time for other modes. Must be cleared by program. RI: Receive Interrupt Flag. Set to 1 at the end of bit 7 time in mode 0 and halfway through the stop bit time for other modes. Must be cleared by program. ii) PCON SFR: SMOD GF1 GF0 PD IDL SMOD: Serial baud rate modify bit. Set to 1 by program to double baud rate using timer 1 for modes 1, 2 and 3. Cleared to 0 by program to use timer 1 baud rate. f baud = 2 SMOD x frequency. The following steps show the 8051 connection to the stepper motor and its programming. 1. Use an ohmmeter to measure the resistance of the leads. This should identify which COM leads are connected to which winding leads. 2. The common wire(s) are connected to the positive side of the motor's power supply. In many motors, +5 V is sufficient. 3. The four leads of the stator winding are controlled by four bits of the 8051 port (P l.0 P1.3). However, since the 8051 lacks sufficient current to drive the stepper motor windings, we must use a driver such as the ULN2003 to energize the stator. Instead of the ULN2003, we could have used transistors as drivers, as shown in figure (1). However, notice that if transistors are used as drivers, we must also use diodes to take care of inductive current generated when the coil is turned off. One reason that using the ULN2003 is preferable to the use of transistors as drivers is that the ULN2003 has an internal diode to take care of back EMF. MOV A,#66H ;load step sequence BACK: MOV P1,A ;issue sequence to motor RR A ;rotate right clockwise ACALL DELAY ;wait 1113/Engg/TE/Pre Pap/2013/ETRX/Soln/MPMC 9
: T.E. MPMC_I 6. (b) SJMP BACK... DELAY MOV R2,#100 Hl: MOV R3,#255 H2: DJNZ R3,H2 DJNZ R2,H1 RET [ ;keep going Steps per second and rpm relation Change the value of DELAY to set the speed of rotation. We can use the single-bit instructions SETB and CLR instead of RR A to create the sequences. The relation between rpm (revolutions per minute), steps per revolution, and steps per second is as follows. Steps per second = rpm Steps per revolution 60 Fig. 1 : 8051 Connection to Stepper Motor 8255 Functional Block Diagram (40 pin IC) 8255 is a programmable peripheral interface (PPI) (i.e., it is a general purpose programmable parallel I/O device). It contains 3 8 bit input/output ports which can be programmed in different modes. To programme the function of these ports 8255 contains a register called control register. Modes/functions of 8255 BSR (Bit Set Reset Mode) [For port C only] Input /Output Mode (I/O) Mode 0 Mode 1 Mode 2 Simple I/O Strobed I/O Bidirectional [For ports A, B & C] (or Handshake I/O) [For port A only] [For ports A & B] Note : Port C bits Note : Port B can are used for be in mode 0 or1 handshake with port A in signals. mode 2 and port C is used for hand shake signals. 10 1113/Engg/TE/Pre Pap/2013/ETRX/Soln/MPMC_I
Prelim Question Paper Solution RD WR A 1 A o Reset 7. (a) Bidirectional Data Bus D 0 D 7 8 bits Power Supplies CS +5V V Data Bus Buffer Read / Write Control Logic Group A Control 8 bit internal data bus Group B Control Group A Port A (8 bits) Group A Port C Upper (4 bits) Group B Port C Lower (4 bits) Group B Port B (8 bits) PA o PA 7 PC 4 PC 7 PC o PC 3 The 3-stage pipeline ARM processors up to the ARM7 employ a simple 3-stage pipeline with the following pipeline stages : Fetch The instruction is fetched from memory and placed in the instruction pipeline. Decode The instruction is decoded and the datapath control signals prepared for the next cycle. In this stage, the instruction owns the decode logic but not the datapath. Execute The instruction owns the datapath: (i) The register bank is read. (ii) An operand is shifted. (iii) The ALU result is generated, and written back into a destination register. I/O I/O I/O PB o PB 7 I/O 1113/Engg/TE/Pre Pap/2013/ETRX/Soln/MPMC 11
: T.E. MPMC_I 7. (b) Fig. 1: ARM single-cycle instruction 3-stage pipeline operation. At any one time, three different instructions may occupy each of these stages, so the hardware in each stage has to be capable of independent operation. When the processor is executing simple data processing instructions the pipeline enables one instruction to be completed every clock cycle (that is, the throughput is one instruction per cycle), although an individual instruction takes three clock cycles to complete, that is, it has a three-cycle latency. When a multi-cycle instruction is executed, as illustrated in figure, the pipeline flow is less regular. Fig.: ARM multi-cycle instruction 3-stage pipeline operation. The cycle colored in yellow is accessing main memory, so it can be seen that memory is used in every cycle. The datapath is likewise used in every cycle, being involved in all the execute cycles, the address calculation and the data transfer. The decode logic is always generating the control signals for the datapath to use in the next cycle, so in addition to the explicit decode cycles, it is also generating the control for the data transfer during the address calculation cycle of the STR. Rotate Instructions 1. RAL (Rotate Accumulator Left with carry) D CF 7 D6 D5 D4 D3 D2 D1 D0 This instruction rotates the contents of accumulator left by one bit position including carry. The D 0 th bit enters into D 1 th bit position, D 1 into D 2, D 2 into D 3 and so on D 6 into D 7, the D 7 th bit enters into carry flag and the carry flag enters into D 0 th bit. Width : 1 byte 12 1113/Engg/TE/Pre Pap/2013/ETRX/Soln/MPMC_I
Prelim Question Paper Solution Addressing : implied addressing. Flags affected : only carry Machine cycle : 1 (op code fetch) T states : 4 2. RLC (rotate accumulator left without carry) CF D 7 D6 D5 D4 D3 D2 D1 D0 This instruction rotates the contents of accumulator left by one bit position without including carry. The D 0 th bit enters into D 1 th bit position, D 1 into D 2, D 2 into D 3 and so on D 6 into D 7, the D 7 th bit enters into D 0 th bit and also in carry flag. Width : 1 byte Addressing : implied addressing. Flags affected : only carry. Machine cycle : 1 (op code fetch) T states : 4 3. RAR (Rotate accumulator right with carry) CF D 7 D6 D5 D4 D3 D2 D1 D0 This instruction rotates the contents of accumulator right by one bit position including carry. The D 7 th bit enters into D 6 th bit position, D 6 into D 5, D 5 into D 4 and so on D 1 into D 0, the D 0 th bit enters into carry flag and the carry flag enters into D 7 th bit. Width : 1 byte Addressing : implied addressing. Flags affected : only carry. Machine cycle : 1 (op code fetch) T states : 4 4. RRC. (Rotate accumulator right without carry) D 7 D6 D5 D4 D3 D2 D1 D0 This instruction rotates the contents of accumulator right by one bit position without including carry. The D 7 th bit enters into D 6 th bit position, D 6 into D 5, D 5 into D 4 and so on D 1 into D 0, the D 0 th bit enters into D 7 th bit and also into carry flag. Width : 1 byte Addressing : implied addressing. Flags affected : only carry. Machine cycle : 1 (op code fetch) T states : 4 CF 1113/Engg/TE/Pre Pap/2013/ETRX/Soln/MPMC 13
: T.E. MPMC_I 7. (c) 7. (d) Memory Mapped I/O i) Instead of memory, I/O device is connected in the memory map. ii) All 20 address lines of 8086 are used in this technique. Hence upto 2 20 = 1 MB devices can be connected. iii) Memory related control signals like memory read, memory write are used for interacting with I/O devices. iv) All instructions related to memory access are used for accessing data from I/O device. v) All memory related addressing modes can be used vi) Some memory space is used for connecting I/O devices. Hence effective memory capacity is less than 1 MB. vii) Efficiency of I/O access is less as memory related instructions are used for accessing I/O devices. I/O mapped I/O (Isolated I/O) i) Separate I/O space is utilised in this technique. ii) Only 16 address lines are active in I/O mapped I/O. Hence upto 2 16 = 64K devices can be connected. iii) I/O related control signals like I/O read and I/O write are used for interacting with I/O devices. iv) Dedicated instructions, IN and OUT are used for accessing data from I/O devices. v) Only I/O related addressing modes are available (direct I/O, Indirect I/O) vi) Separate address space is used for connecting I/O devices. Hence effective memory capacity is 1 MB. vii) IN and OUT instructions are designed for high throughput. Hence accessing I/O is efficient. Baud rate in the 8051 The 8051 transfers and receives data serially at many different baud rates. The baud rate in the 8051 is programmable. This is done with the help of Timer 1. Before we discuss how to do that, we will look at the relationship between the crystal frequency and the baud rate in the 8051. The 8051 divides the crystal frequency by 12 to get the machine cycle frequency. In the case of XTAL = 11.0592 MHz, the machine cycle frequency is 921.6 khz (11.0592 MHz /12 = 921.6 khz). The 8051's serial communication UART circuitry divides the machine cycle frequency of 921.6 khz by 32 once more before it is used by Timer l to set the baud rate. Therefore, 921.6 khz divided by 32 gives 28,800 Hz. This is the number we will use throughout this section to find the Timer l value to set the baud rate. When Timer l is used to set the baud rate it must be programmed in mode 2, that is 8-bit, auto-reload. To get baud rates compatible with the PC, we must load TH l with the values shown in Table 2. Example 4 shows how to verify the data in Table 2. Table 2 : Timer 1 TH1 Register Values for Various Baud Rates Baud Rate TH1 (Decimal) TH1 (Hex) 9600 3 FD 4800 6 FA 2400 12 F4 1200 24 E8 Note: XTAL = 11.0592 MHz. Example : With XTAL = 11.0592 MHz, find the TH l value needed to have the following baud rates, (a) 9600 (b) 2400 (c) 1200 Soln.: With XTAL= 11.0592 MHz, we have : 14 1113/Engg/TE/Pre Pap/2013/ETRX/Soln/MPMC_I
Prelim Question Paper Solution The machine cycle frequency of the 8051 11.0592 MHz /12 = 921.6 khz, and 921.6 khz / 32 = 28,800 Hz is the frequency provided by UART to Timer l to set baud rate. (a) 28,800 / 3 = 9600 where -3 = FD (hex} is loaded into TH1 (b) 28,800 /12 = 2400 where -12 = F4 (hex) is loaded into TH1 (c) 28,800 / 24 = 1200 where -24 = E8 (hex) is loaded into TH1 7. (e) Notice that 1/12th of the crystal frequency divided by 32 is the default value upon activation of the 8051 RESET pin. We can change this default setting. This is explained at the end of this chapter. 11.0592kHz XTAL oscillator 12 Machine cycle freq. 32 921.6 khz by UART Methods of Parameter Passing : 1) Parameter passing through register : If parameters to pass are few then registers can be used to pass parameter. Parameters are stored in registers before the subroutine is called. The subroutine processes these parameters and gives the result back either in same registers or in different registers. e.g. : The main program can load the registers with multiplicand and multiplier and then calls a subroutine that multiplies the 2 numbers and sends back the results in either the same registers or in different registers. 2) Parameter passing through reserved memory locations : If many parameters are to be passed, then they are stored in specific locations reserved earlier and then subroutine is called which processes them and sends back the result through same or different memory locations. 3) Parameter passing through memory pointers : If memory location needed to pass the parameter, cannot be fixed then memory pointer can be used as parameter. Through a register pair microprocessor can pass the memory pointer to a subroutine which indicate the starting address for the stored parameters. The subroutine processes them and returns the result either through registers or memory locations. 4) Parameter passing through stack memory : Stack can also be used to pass parameters. Appropriate program should be written for this technique. The parameters to be passed are first pushed into stack and then subroutine is called. The subroutine pops out the parameters and processes them. The result can also be passed through stack memory. 28,800 Hz To Timer 1 to set the baud rate 1113/Engg/TE/Pre Pap/2013/ETRX/Soln/MPMC 15