Memory Interfacing & decoding. Intel CPU s

Memory Interfacing & decoding in Intel CPU s

Outline Address decoding Chip select Memory configurations

Minimum Mode - - A19 - A19 - Simplified Drawing of 8088 Minimum Mode MEMORY MEMW When Memory is selected?

Minimum Mode 2 20 bytes or 1MB - - A19 - A19 - Simplified Drawing of 8088 Minimum Mode MEMORY MEMW

What are the memory locations of a 1MB (2 20 bytes) Memory? A19 to 1111 1111 1198 7654 3210 (HEX) 9876 5432 1000 00000 0000 0000 0000 0000 0000 FFFFF 1111 1111 1111 1111 1111 Example 34F 0011 0100 11111 1101 0000

Interfacing a 1MB Memory to the 8088 Microprocessor FFFFD FFFFE FFFFF 19 25 36 A19 A19 CX BX AX 0000 0023 3F1C FCA1 DX 20020 20021 20022 20023 29 12 7D 13 ES DS SS 2000 10007 10008 F4 8A BP SP 10002 10003 10004 10005 10006 27 39 42 88 07 SI IP DI 00001 10000 10001 95 45 98 MEMW 23 00000 00001 95

Instead of Interfacing 1MB, what will happen if you interface a 512KB Memory?

What are the memory locations of a 512KB (2 19 bytes) Memory? to 1111 1111 1198 7654 3210 (HEX) 9876 5432 1000 00000 0000 0000 0000 0000 0000 7FFFF 0111 1111 1111 1111 1111

Interfacing a 512KB Memory to the 8088 Microprocessor AX BX CX DX SS DS ES BP SP 3F1C 0023 0000 FCA1 2000 A19 What do we do with A19? 7FFFF 36 7FFFE 7FFFD 20023 20022 20021 20020 25 19 13 7D 12 29 SI DI IP MEMW 00001 95 00000 23

What if you want to read physical address 023? AX BX CX DX SS DS ES BP SP 3F1C 0023 0000 FCA1 00 A19 7FFFF 36 7FFFE 7FFFD 20023 20022 20021 20020 25 19 13 7D 12 29 SI DI IP MEMW 00001 95 00000 23

What if you want to read physical address 023? A19 to 1111 1111 1198 7654 3210 (HEX) 9876 5432 1000 023 1010 0000 0000 0010 0011 A19 is not connected to the memory so even if the 8088 microprocessor outputs a logic 1, the memory cannot t see this.

What if you want to read physical address 20023? to 1111 1111 1198 7654 3210 (HEX) 9876 5432 1000 20023 0010 0000 0000 0010 0011 For memory it is the same as previous For memory it is the same as previous one.

Interfacing two 512KB Memory to the 8088 Microprocessor CX BX AX 0000 0023 3F1C FCA1 DX A19 7FFFD 7FFFE 7FFFF 19 25 36 ES DS SS 2000 20020 20021 20022 20023 29 12 7D 13 MEMW BP SP 23 00000 00001 95 SI IP DI 20023 7FFFD 7FFFE 7FFFF 33 2C 98 12 00001 20020 20021 20022 A3 92 45 97 00000 00001 D4

Interfacing two 512KB Memory to the 8088 Microprocessor Problem Bus Conflict. The two memory chips will provide data at the same time when microprocessor performs a memory read. Solution Use address line A19 as an arbiter. If A19 outputs a logic 1 the upper memory is enabled (and the lower memory is disabled) and vice-versa.

What are the memory locations of two consecutive 512KB (2 19 bytes) Memory? A19 to 1111 1111 1198 7654 3210 (HEX) 9876 5432 1000 00000 0000 0000 0000 0000 0000 7FFFF 0111 1111 1111 1111 1111 80000 1000 0000 0000 0000 0000 FFFFF 1111 1111 1111 1111 1111

Interfacing two 512KB Memory to the 8088 Microprocessor AX BX CX DX SS DS ES BP SP SI DI IP 3F1C 0023 0000 FCA1 2000 A19 MEMW When the P outputs an address between 80000 00000 to FFFFF, 7FFFF, this memory is selected 7FFFF 36 7FFFE 25 7FFFD 19 20023 13 20022 7D 20021 12 20020 29 00001 95 00000 23 7FFFF 12 7FFFE 98 7FFFD 2C 20023 33 20022 45 20021 92 20020 A3 00001 D4 00000 97

Interfacing two 512KB Memory to the 8088 Microprocessor CX BX AX 0000 0023 3F1C FCA1 DX A19 7FFFD 7FFFE 7FFFF 19 25 36 ES DS SS 2000 20020 20021 20022 20023 29 12 7D 13 MEMW BP ES SP 23 00000 00001 95 SI IP DI 20023 7FFFD 7FFFE 7FFFF 33 2C 98 12 20020 20021 20022 20023 A3 92 45 33 97 00000 00001 D4

Interfacing two 512KB Memory to the 8088 Microprocessor CX BX AX 0000 0023 3F1C FCA1 DX A19 7FFFD 7FFFE 7FFFF 19 25 36 A19 ES DS SS 2000 20020 20021 20022 20023 29 12 7D 13 MEMW BP ES SP 23 00000 00001 95 SI IP DI 20023 7FFFD 7FFFE 7FFFF 33 2C 98 12 20020 20021 20022 20023 A3 92 45 33 97 00000 00001 D4

What if we remove the lower memory? CX BX AX 0000 0023 3F1C FCA1 DX A19 7FFFD 7FFFE 7FFFF 19 25 36 ES DS SS 2000 20020 20021 20022 20023 29 12 7D 13 MEMW BP SP 23 00000 00001 95 SI IP DI 20023 7FFFD 7FFFE 7FFFF 33 2C 98 12 20020 20021 20022 A3 92 45 97 00000 00001 D4

What if we remove the lower memory? AX BX CX DX SS DS ES BP SP SI DI IP 3F1C 0023 0000 FCA1 2000 A19 MEMW When the P outputs an address between 80000 00000 to FFFFF, 7FFFF, no memory this memory chip is is selected! 7FFFF 36 7FFFE 25 7FFFD 19 20023 13 20022 7D 20021 12 20020 29 00001 95 00000 23

Full and Partial Decoding Full Decoding When all of the useful address lines are connected the memory/device to perform selection Partial Decoding When some of the useful address lines are connected the memory/device to perform selection Using this type of decoding results into roll-over addresses

Full Decoding CX BX AX 0000 0023 3F1C FCA1 DX A19 7FFFD 7FFFE 7FFFF 19 25 36 ES DS SS 2000 20020 20021 20022 20023 29 12 7D 13 MEMW BP SP 23 00000 00001 95 SI IP DI

Full Decoding A19 to 1111 1111 1198 7654 3210 (HEX) 9876 5432 1000 80000 1000 0000 0000 0000 0000 FFFFF 1111 1111 1111 1111 1111 A19 should be a logic 1 for the A19 should be a logic 1 for the memory chip to be enabled

Full Decoding A19 to 1111 1111 1198 7654 3210 (HEX) 9876 5432 1000 00000 0000 0000 0000 0000 0000 7FFFF 0111 1111 1111 1111 1111 Therefore if the microprocessor outputs an address between 00000 to 7FFFF, whose A19 is a logic 0, the memory chip will not be selected

Partial Decoding CX BX AX 0000 0023 3F1C FCA1 DX 7FFFF 36 A19 ES DS SS 2000 7FFFD 7FFFE 19 25 BP SP 20020 20021 20022 20023 29 12 7D 13 MEMW SI IP DI 23 00000 00001 95

Partial Decoding A19 to 1111 1111 1198 7654 3210 (HEX) 9876 5432 1000 00000 0000 0000 0000 0000 0000 7FFFF 0111 1111 1111 1111 1111 80000 1000 0000 0000 0000 0000 FFFFF 1111 1111 1111 1111 1111 The value of A19 is INSIGNIFICANT to the The value of A19 is INSIGNIFICANT to the memory chip, therefore A19 has no bearing whether the memory chip will be enabled or not

Interfacing two 512K Memory Chips to the 8088 Microprocessor 8088 Minimum Mode A19 MEMW 512KB #2 512KB #1

Interfacing one 512K Memory Chips to the 8088 Microprocessor 8088 Minimum Mode A19 MEMW 512KB

Interfacing one 512K Memory Chips to the 8088 Microprocessor (version 2) 8088 Minimum Mode A19 MEMW 512KB

Interfacing one 512K Memory Chips to the 8088 Microprocessor (version 3) 8088 Minimum Mode A19 MEMW 512KB

Interfacing four 256K Memory Chips to the 8088 Microprocessor 256KB A19 256KB #4 256KB #3 8088 Minimum Mode MEMW 256KB #2 256KB #1 #1

Memory chip# is mapped to A19 to 1111 1111 1198 7654 3210 (HEX) 9876 5432 1000 ----- ---- ---- ---- ---- ---- ----- ---- ---- ---- ---- ----

Interfacing four 256K Memory Chips to the 8088 Microprocessor 256KB A19 256KB #4 256KB #3 8088 Minimum Mode MEMW 256KB #2 256KB #1 #1

Interfacing four 256K Memory Chips to the 8088 Microprocessor 256KB A19 256KB #4 256KB #3 8088 Minimum Mode MEMW 256KB #2 256KB #1

Interfacing four 256K Memory Chips to the 8088 Microprocessor 256KB A19 256KB #4 I1 I0 O3 256KB #3 8088 Minimum Mode MEMW O2 256KB #2 O1 256KB #1 O0

Interfacing several 8K Memory Chips to the 8088 P A19 A16 A15 A14 A13 A12 8KB #? 8088 Minimumi Mode A12 MEMW A12 8KB #2 A12 8KB #1

Interfacing 128 8K Memory Chips to the 8088 P A19 A16 A15 A14 A13 A12 8KB #128 8088 Minimumi Mode A12 MEMW A12 8KB #2 A12 8KB #1

Interfacing 128 8K Memory Chips to the 8088 P A19 A16 A15 A14 A13 A12 8KB #128 8088 Minimum Mode A12 MEMW A12 8KB #2 A12 8KB #1

Memory chip# is mapped to A19 to 1111 1111 1198 7654 3210 (HEX) 9876 5432 1000 ----- ---- ---- ---- ---- ---- ----- ---- ---- ---- ---- ----

Memory Terms Capacity Kbit, Mbit, Gbit Organization Address lines Data lines Speed / Timing Access time Write ability ROM RAM

ROM Variations Mask Rom PROM OTP EPROM UV_EPROM EEPROM Flash memory

RAM Variations SRAM DRAM NV-RAM SRAM CMOS Internal lithium battery Control circuitry to monitor Vcc

Memory Chip 8K SRAM to be specific 8Kx88 bits SRAM A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 6264 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 OE WE 1 2

6264 Block Diagram

6264 Function Table

Memory Chip 8K EPROM to be specific 8Kx88 bits EPROM A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 2764 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 G P C VPP

2764 Block Diagram Chip enable Output enable

Operating Modes

Programming 2764 after each erasure for UV-EPROM) all bits of the M2764A are in the 1" state. The only way to change a 0" to a 1" is by ultraviolet light erasure. Programming mode when VPP input is at 12.5V E and P are at TTL low. The data to the data output pins. The levels required for the address and data inputs are TTL.

Interfacing 128 8K Memory Chips to the 8088 P A19 A16 A15 A14 A13 A12 8KB #128 8088 Minimum Mode A12 MEMW A12 8KB #2 A12 8KB #1