IEEE 1588 Hardware Assist - PDF Free Download

Freescale Technology Forum, June 2007 IEEE 1588 Hardware Assist Session ID: AZ317 Satoshi Iida Applications Engineering Manager

Agenda IEEE 1588 Protocol Overview Synchronization Overview Why Create Another Protocol? Target Applications Hardware Assist Synchronization Using Hardware Assist Software-Only vs. Hardware Assisted Implementations Hardware Assist in PowerQUICC II Pro Family devices Expansion into Network Applications Synchronization vs. Syntonization Synchronizing Across a Network Boundary Clocks and Transparent Clocks Proposed IEEE 1588 Rev 2.0 Changes Conclusion 1

IEEE 1588 Overview IEEE 1588 Standard for a Precision Clock Synchronization Protocol for Networked Measurement and Control Systems The standard defines a Precision Time Protocol (PTP) designed to synchronize real-time clocks in a distributed system Intended for local area networks using multicast communications (including Ethernet) IEEE 1588 was designed to work within a building or factory Intended typically for industrial automation and test and measurement systems (e.g. synchronized printing presses) Targeted accuracy of microsecond to sub-microsecond with easy configuration and fast convergence between components Approved on September 2002 and published on November 2002 Available from the IEEE 1588 web site (http://ieee1588.nist.gov) NETWORK NETWORK Node A: Time = 9:04 Node B: Time = 9:29 Node C: Time = 9:28 Node A: Time = 9:04 Node B: Time = 9:04 Node C: Time = 9:04 2

IEEE 1588 Synchronization Overview Networked clocks organized in master-slave hierarchy Two-way time exchange between master and slaves Master clock sends messages to Slave clocks to initiate synchronization process Each Slave responds by synchronizing itself to corresponding Master This sequence is repeated throughout the network IEEE 1588 Message Types exchanged between Master and Slave: Sync Delay_Req Follow_Up Delay_Resp Management 3

100 102 104 106 108 110 IEEE 1588 Synchronization Overview (Message Sequence) Estimated Send Time (100) Precise Send Time (101) B Precise Receive Time (108) Master Clock PTP Appl. G/MII t 0 SYNC(100??) FOLLOW_UP(101!) DELAY_REQ t 3 t 2 DELAY_RESP(108) Slave Clock G/MII PTP Appl. t 1 A Precise Receive Time (106) Offset Computation Precise Send Time (111) 104 106 108 110 112 114 112 Key Equations: A = t 1 t 0 = Delay + Offset B = t 3 -t 2 = Delay Offset Delay = (A+B) / 2 Offset = (A-B) / 2 Example: A = 106 101 = 5 B = 108 111 = -3 Delay = (5-3) / 2 = 1 Offset = (5+3) / 2 = 4 116 UDP port 319: Sync and Delay_Req UDP port 320: Follow_up, Delay_Resp, and Mgmt 4

IEEE 1588: Why Create Another Protocol? Many protocols distribute time and synchronize network elements Most use moderate compute resources NTP Network Time Protocol, RFC 1305 Less accurate (milliseconds) and longer synch time (minutes to hours) GPS Satellite based Global Positioning System TTP www.ttpforum.org SERCOS IEC 61491 IEEE 1588 differentiates for target markets Small compute and network footprint (<1% CPU utilization) Highest accuracy (<1 microsecond) Fast network synch resolution time (<1 minute) Easy configuration and operation by non-expert users Low cost 5

IEEE 1588 Target Applications

Ethernet E Controller Adapter Motion Controller Master Time Master Time Ethernet E Controller Adapter Motion Controller Switch Switch Controller Motion Controller Servo E Drive Servo E Drive IEEE 1588 in Industrial Control Distributed Control Ethernet Adapter Issues due to mismatched cable lengths are minimized Servos can be Servo E added or deleted Drive without having to rewire other servos Peer Controlling Other Peers Industrial Control applications typically augment IEEE 1588 Ethernet hardware to provide E E Controller Adapter trigger inputs Motion Controller and outputs E Servo Drive E Servo Drive E Servo Drive 7

Spectrum Analyzer Trigger In IEEE 1588 in Test and Measurement Remote Test Controller IEEE 1588 allows coordination and control of Test and Measurement equipment over a distributed Ethernet network Test Board Test Point Pattern Generator Ethernet Network Precise timing delivery allows test equipment to deliver patterns and measure responses at specific times Enables accurate time stamping of measured data Allows coordination of input stimuli and any associated measured data Logic Analyzer Oscilloscope Trigger Out Trigger inputs and outputs enable coordination of other devices 8

IEEE 1588 in a Wireless Network Precision Time Source Primary Time Server Secondary Time Server Precision Time Source GPS GPS 1588 Grand Master 1588 Grand Master 1588 Slave Clock Packet Based Radio Access Network RNC E Base Station E Base Station E Base Station E Base Station * With proper changes to the current standard 9

Hardware Assist

What is Hardware Assist? An hardware that generates timestamps at the physical level of the protocol stack 11

Synchronization at Application Layer Assisted by Hardware at Physical Layer Master Clock Apply filtering and smoothing as necessary Slave Clock Milliseconds of delay and variation introduced by protocol stack L5 L4 L3 APPL: OTH. TCP/UDP IP APPL: SYNC Insert Timestamps into packet header Reconstruct clock from extracted timestamps and packet arrival times Extract Timestamps from packet header APPL: SYNC TCP/UDP IP APPL: OTH. L5 L4 L3 L2 L1 MAC PHY Timestamp generation / message detection Timestamp generation / message detection MAC PHY L2 L1 Packet Network 12

Software-only vs. Hardware Assisted Implementations Software-only Implementations Timestamps are generated at the application level Microsecond range synchronization is possible Hardware Assisted Implementations Timestamps are generated at the physical level Nanosecond range synchronization is possible 13

Hardware Assist in PowerQUICC II Pro Family Devices Freescale currently has IEEE 1588 drivers available for MPC8349E and MPC8360E PowerQUICC II Pro Families supporting 1588 with Hardware Assist MPC8360E (includes MPC8358E) MPC8313E 14

Expansion into Network Applications

Benefits: Eliminates need for extra equipment i.e. GPS receivers 1588 provides greater accuracy Time to synchronize Expansion into Network Applications Concerns: Synchronization Algorithm Factors Delay can be added by repeaters, switches, routers, and network topologies Boundary clocks and transparent switches (Version 2.0 only) can also help overcome this added delay 16

Synchronization Clocks are characterized by : Same Time of Day Same Frequency Frequency is locked Each clock has the same definition of a time unit (e.g., a second) Same Phase Phase is Locked Clock Signal Relationships: Synchronization vs. Syntonization Syntonization Clocks are characterized by: Same Frequency Frequency is locked Each clock has the same definition of a time unit (e.g., a second) Phase offset is constant but unbounded Time of Day may be different Source Clock 1 UI 2 UI Source Clock 1 UI 2 UI Clock 1 Clock 1 1 UI 2 UI 1 UI 2 UI Clock 2 Clock 2 Recovered Clock Note variation between signals within small specified limits (jitter) Recovered Clock Note constant but uncontrolled time/phase relationship between signals 17

IEEE 1588 : Synchronizing a Pair of Clocks Across a Network (General Method) Master Clock X 0 X 0 0 X X X 0 Local Counter Not in SYNC PTP Software Slave Clock PTP Software 0 0 X 0 X 0 X 0 X Local Counter 18

IEEE 1588 : Synchronizing a Pair of Clocks Across a Network (General Method) Master Clock X 0 X 0 0 X X X 0 2 8 3 1 5 2 7 3 0 Local Counter SYNC Slave Clock PTP Software PTP Software 2 8 3 1 5 9 3 3 0 0 0 X 0 X 0 X 0 X Local Counter 2 8 3 1 3 0 0 0 0 19

Addressing the Variable Network Delay Problem Master Clock PTP UDP IP MAC PHY Variable delay introduced by Network due to topology: Hundreds of nanoseconds to sub-microseconds for repeaters & switches Milliseconds for routers Network Slave Clock PTP UDP IP MAC PHY Impact of variable network delay minimized by using Boundary clocks 23

Boundary Clock Master Clock Switch / Router with Boundary Clock (Slave) (Master) Slave Clock PTP PTP PTP PTP UDP UDP UDP UDP IP IP IP IP MAC MAC MAC MAC PHY Network 1 PHY PHY Network 2 PHY Boundary Clocks provide the ability to synchronize clocks across multiple networks/subnets by serving as a slave at one port and a master on all other ports 24

Notes on Boundary Clocks Switch / Router with Boundary Clock (Slave) (Master) PTP UDP IP MAC PHY PTP UDP IP MAC PHY Boundary clocks define a parent-child hierarchy of master-slave clocks Boundary clocks do NOT pass SYNC, FOLLOW_UP, DELAY_REQ, or DELAY_RESP messages Boundary clocks segment the network in terms of IEEE 1588 synchronization Within a subnet, a boundary clock port acts just like an ordinary clock with respect to synchronization Each port terminates PTP as a master or a slave The boundary clock port that is receiving the master clock becomes the single slave port. All other ports of the boundary clock internally synchronize to this slave port, and become masters for their respective subnets 25

Transparent Clock Master Clock Switch with Transparent Clock Slave Clock PTP UDP IP MAC PHY Network 1 MAC PHY Time Correction Switching Function MAC PHY Network 2 PTP UDP IP MAC PHY Transparent Clocks syntonize to the Master Clock (i.e., have the same definition of a second), but do not synchronize to the Master Clock 26

Proposed IEEE 1588 Rev 2.0 Changes

***PROPOSED*** IEEE 1588 Rev 2.0 Changes/Clarifications Calls for SHA-1/2 authentication of PTP messages Critical for Telecom and other applications where messaging takes place over public networks Support for faster SYNC message rates (up to 1000 per second) Critical for Telecom, Residential Ethernet, and many control applications Support for PTP transport directly over Ethernet (via an Ethertype designation) Needed in applications where timestamping is required without using UDP transport typically control applications Support for Clocking Redundancy Critical for Telecom and many control application Support for shorter PTP messages, unicast messaging, as well as new messages (delay request) and message fields Critical for control, telecom, and Residential Ethernet applications where bandwidth allocated for this function is limited Support for phase-aligned output PPS Requirement for some applications where PPS output demonstrates synchronization Support for sub-nanosecond accuracy Critical for all high accuracy applications Support for Transparent Clocks Used in Residential Ethernet (and possibly Telecom) applications, these correct timestamps, sometimes on the fly 28

Conclusion Freescale supports software-based IEEE 1588 (PTP) implementations on both current and future PowerQUICC devices IEEE 1588 Hardware Assist features are available on both current and Future PowerQUICC devices Both etsec- based products and products built on QUICC Engine technology QE: 836x and future QE-based devices etsec: 831x, 837x, and future etsec-based devices Intended to address industrial automation, test, and other applications Implementation allows for multiple clock options, flexible support for PTP frame detection, and rich set of external signal interfaces 29