Microcontroller Systems ELET 3232 Topic 11: General Memory Interfacing 1
Objectives To become familiar with the concepts of memory expansion and the data and address bus To design embedded systems circuits that will include generic expanded memory systems External to the microcontroller 2
Memory Technology Memory chips are a major component in digital systems It is important to fully understand The electrical and timing characteristics How to interface memory to microprocessors and microcontrollers Semiconductor memories retain information in their memory cells for varying amounts of time volatile or non-volatile dynamic or static 3
Volatile Memory Volatile memory loses its stored information when power is removed Random access memory (RAM) is volatile memory RAM is sometimes referred to as read/write memory Data may be stored in (written to) memory as well as read from memory under normal circuit operation Flash Memory Non-volatile memory that can be electrically erased and reprogrammed A type of EEPROM Used as program memory on most embedded systems 4
Non-Volatile Memory ROM memory is non-volatile Masked ROM is a type of ROM whose data is stored into it during the manufacturing process These types of ROM chips are used in systems where: The data/program have been perfected and Will be used in many products (such as system or boot-up programs in computers PROMs are programmable read only memories. PROMs May be programmed once and then never erased or altered 5
EPROM Memory EPROMs are erasable programmable read only memories Characterized by a small window in the top of the chip Used to allow ultra violet light to fall onto the IC Erases the stored data or program Takes about 30 minutes Mostly used in test and experimental circuits or in circuits whose program and/or data may change periodically 6
EEPROM Memory EEPROMs are electrically erasable programmable read only memories Non-Volatile: Retain data and/or programs when power is removed May be erased and written to (programmed) while in the circuit Limited read/erase/write cycle About 10,000 times Slower than other types of memory Used to hold constant data in embedded systems 7
Memory Organization Data may be read from or written to memory one bit at a time or several bits at a time Depends on its organization Example: A memory IC with two addressable memory locations that could each store 8 bits of data a 2 x 8 organization (2 memory locations by 8 bits wide) 8
2 x 8 Memory Organization Data may be read from or written to memory one bit at a time or several bits at a time Depends on its organization Example: A memory IC with two addressable memory locations that could each store 8 bits of data a 2 x 8 organization (2 memory locations by 8 bits wide) A A = 0 A = 1 This chip would need only one address line to choose between the two addressable memory locations 9
4 x 4 Memory Organization Example: A chip that had four addressable memory locations, each capable of storing four bits simultaneously 4 x 4 organization Each addressable memory location (or the chip itself) would be said to be 4 bits wide. 10
4 x 4 Memory Organization This IC would require 2 address inputs to select one of the four addressable memory locations as shown. A1 A0 Example: A chip that had four addressable memory locations, each capable of storing four bits simultaneously 4 x 4 organization Each addressable memory location (or the chip itself) would be said to be 4 bits wide. 11
Memory Addressing All memory has external pins for selecting a particular addressable memory location: its address inputs Example: a 4 x 8 memory chip requires 2 address inputs 12
Memory Addressing All memory has external pins for selecting a particular addressable memory location: its address inputs Example: a 4 x 8 memory chip requires 2 address inputs The internal decoding logic will accept the address inputs and then decode and select the appropriate memory location. 13
Memory Addressing All memory has external pins for selecting a particular addressable memory location: its address inputs Example: a 4 x 8 memory chip requires 2 address inputs The internal decoding logic will accept the address inputs and then decode and select the appropriate memory location. The only thing that circuit designers must do in this case is to connect the proper pins from the microcontroller to the address inputs. 14
8 x 8 Memory System What if our circuit required an 8 x 8 memory system, but all we have available are the 4 x 8 memory chips. 15
2-4 x 8 Memory ICs What if our circuit required an 8 x 8 memory system, but all we have available are the 4 x 8 memory chips. We would then need two 4 x 8 memory chips 16
Simple Decoding Logic What if our circuit required an 8 x 8 memory system, but all we have available are the 4 x 8 memory chips. We would then need two 4 x 8 memory chips and the circuitry (external decoding logic) to choose between them. 17
A 0 and A 1 Address inputs A 0 and A 1 will choose the memory location on on each memory chip.. 18
RAM 0 and RAM 1 : A 2 Address inputs A 0 and A 1 will choose the memory location on on each memory chip.. A 2 will enable the proper memory chip (either RAM0 or RAM1) 19
Example Address If address 101 (A 2 =1, A 1 =0, A 0 =1) is placed on the address lines 1 0 1 20
RAM 1 Enabled If address 101 (A 2 =1, A 1 =0, A 0 =1) is placed on the address lines RAM1 is enabled 1 0 The output of the inverter is low and the enable input on the RAM chips are active low 1 0 21
Location 2 Selected (RAM 1 ) If address 101 (A 2 =1, A 1 =0, A 0 =1) is placed on the address lines RAM1 is enabled 1 0 The output of the inverter is low and the enable input on the RAM chips are active low 1 0 1 0 1 The second memory location on RAM1 is selected 22
Larger Capacity Memory Suppose we must design a memory system with 4k bytes (4k x 8) of external RAM using 1k x 8 RAM chips The first thing we should do is determine the number of address inputs on the RAM chips We could look on the data sheets or calculate it 2 10 =1024 (or 1k) So, the RAM chips will require 10 address inputs to choose between the 1024 addressable memory locations. 23
How many address lines? We could also determine this with the following formula: log 2 1024 = number of address inputs binary Number of addressable locations 24
Formula Most of our calculators do not have the log 2 (log base 2) function, so use this formula: 25
Back to the example We now know that each memory chip will have 10 address inputs and eight data I/O lines Each RAM chip is 8 bits wide Each (of 4) RAM ICs will be connected as shown 26
Alternate Drawings Same as previous circuit 27
Decoding Logic We now need to design the external decoding logic to choose between the four required memory ICs 28
Decoding Logic Two additional address lines are required to choose between 4 ICs. We will use A 10 and A 11 and a 74139 dual 2-to- 4 decoder chip A 11 A 10 One to each RAM IC 29
The 74139 The A0 and A1 (or B0 and B1) inputs are the select inputs If the enable input is active (low), the select inputs will cause the appropriate output line to become active (go low) If the enable input is not active (high), all of the outputs are high. 30
Almost Complete Circuit We will use A 10 and A 11 to select one of the four RAM chips. The remaining address lines (A 12 A 15 ) will be used to enable the 74139 The R/W, AS, and other control lines are not shown 31
4k X 8 using 1k x 4 RAM ICS When using 1k x 4 RAM ICs, 2 memory ICs (one bank) must be enabled simultaneously One will hold the upper four bits of data (D 4 D 7 ) and the other will hold the lower four bits of data (D 0 D 3 ) 32
More on Memory Organization Consider two memory organization: 128k x 8 bits SRAM = 128 kbytes = 1 Mbits 1 M x 1 bit DRAM = 1 Mbits 33
SRAM Consider the SRAM: 128k x 8 bits SRAM = 128 kbytes = 1 Mbits SRAM has 128k addressable locations, each 8 bits wide. It requires log 2 (128k) = 17 address lines, numbered A 0 A 16 (A 0 is the LSB) It requires 8 data lines numbered D 0 D 7 34
DRAM Consider the DRAM: 1 M x 1 bit DRAM = 1 Mbits DRAM has 1M addressable locations, each 1 bit wide. It requires log 2 (1M) = 20 address lines, numbered A 0 A 19 The addresses from the microcontroller will be multiplexed and so the DRAM will only see ½ the addresses for each half or full cycle. It requires 10 address lines and the Row Address Strobe (RAS) and Column Address Strobe (CAS). It requires 1 data line numbered D 0 on the IC but connected to whichever data line on the data bus 35
SRAM & DRAM Byte-wide memories are more common in embedded systems designs They are simpler A wide variety of memory technologies available in standard packages DRAMs are more common in PC design The refresh support circuitry makes them a little more complicated The address multiplexing also complicates matters They are less expensive than SRAM 36
Summary We became familiar with the concepts of memory expansion the data and address bus We designed a generic expanded memory circuit for an embedded system 37