Building hierarchical designs in Verilog Arhitectura Calculatoarelor/Computer Architecture October 15, 2017
Verilog hierarchies Objectives: Learn how to instantiate a module Construct a design hierarchy Hierarchical design - Facilitates design of complex architectures - Promote design reuse Instance: a module used as a component in a larger module. An instances has: A module: provides the definition of the instance. A container: the module in which the instance is created. Creating a new instance is referred to as instantiation.
Instantiation An instance is constructed by providing the following: the module to be instantiated, followed by an instance name (to differentiate from other instances of the same module), followed by a list of port connections List of port connections specifies to which signals from container are instance s ports linked. A port connection is specified like:.<module_port>(<container_signal>), in which module port is a port of the instantiated module container signal is an internal signal or a port from container
4-to-1 multiplexer Exercise: Build a 4-to-1 multiplexer out of 2-to-1 multiplexers. Solution: The architecture of the 4-to-1 multiplexer using three 2-to-1 multiplexer modules is depicted bellow. Data input, d, is on 4 lines and the 2-bit selection line, s, propagates one bit of the data input to the output, o. For example, if s = (1, 0), input line d[2] is propagated to o.
4-to-1 multiplexer (contd.) The Verilog code implementing the 4-to-1 multiplexer s architecture is presented bellow: 1 module mux 2s 1b ( 2 i n p u t [ 3 : 0 ] d, 3 i n p u t [ 1 : 0 ] s, 4 output o 5 ) ; 7 w i r e f ; 8 w i r e g ; 10 mux 1s 1b mux1 ( 11. d0 ( d [ 0 ] ), 12. d1 ( d [ 1 ] ), 13. s ( s [ 0 ] ), 14. o ( f ) 15 ) ; 17 mux 1s 1b mux2 ( 18. d0 ( d [ 2 ] ), 19. d1 ( d [ 3 ] ), 20. s ( s [ 0 ] ), 21. o ( g ) 22 ) ; 24 mux 1s 1b mux3 ( 25. d0 ( f ), 26. d1 ( g ), 27. s ( s [ 1 ] ), 28. o ( o ) 29 ) ; 30 endmodule
4-to-1 multiplexer (contd.) Analyzing the first instance created in the 4-to-1 multiplexer code above the components of an instantiation can observed: the module to be instantiated is mux 1s 1b (it must be the name of an existing Verilog module) the instance name is mux1 (it must be a valid Verilog ID) the list of port connections, within round parentheses (more details in the following slide) 10 mux 1s 1b mux1 ( 11.d0(d[0]), 12.d1(d[1]), 13.s(s[0]), 14.o(f) 15 ) ;
4-to-1 multiplexer (contd.) Detail of the mux_2s_1 emphasizing the mux1 instance and its connections: 10 mux 1s 1b mux1 11. d0 ( d[0] ), 12. d1 ( d [ 1 ] ), 13. s ( s [ 0 ] ), 14. o ( f ) 15 ) ; Elements of the first port connection: d0 - port of the mux_1s_1 module for the connection in line of code 11 is constructed d[0] - signal inside the mux_2s_1 container ( d[0] is a container s port, thus a signal in the container ) to which port d0 is connected
4-to-1 multiplexer (contd.) Internal wires link internal instances connect one instance s output to another instance s input must be declared inside the container module as wires Internal wire declaration for the mux_2s_1b architecture: 7 w i r e f ; 8 w i r e g ;
4-to-1 multiplexer (contd.) f Verilog code bellow connects mux1 s output, o, to wire f (left) connects mux3 s input, d0, to wire f (right) 10 mux 1s 1b mux1 ( 11. d0 ( d [ 0 ] ), 12. d1 ( d [ 1 ] ), 13. s ( s [ 0 ] ), 14.o(f) 15 ) ; 24 mux 1s 1b mux3 ( 25.d0(f), 26. d1 ( g ), 27. s ( s [ 1 ] ), 28. o ( o ) 29 ) ;
4-to-1 multiplexer (contd.) Important: When connecting a wire to a port, the widths must match! If the two ports to be connected have different widths, choose for the width of the connecting wire the width of one of them. For connecting the wire to the other port: if the wire has fewer lines and the other port is an output, some of the outputs line will remain unconnected if the wire has fewer lines and the other port to which it connects is an input, use concatenation to provide the needed extra input lines (eg..x({4 d0, data}),) if the wire has more lines and the other port to which it connects is an input, use part-select to provide only the needed input lines (eg..s(addr[15:14]),) if the wire has more lines and the other port to which it connects is an output, use part-select to provide only the needed output lines (eg..z(next_addr[7:0]),)
Three-to-eight-lines decoder with enable input Exercise: Build a decoder device with three selection lines, an enable input and active low outputs using decoder components with two selection lines, enable input and active low outputs. Solution: The architecture of the three-to-eight-lines decoder, dec_3x8, is depicted bellow.
Three-to-eight-lines decoder with enable input (contd.) Justification: Since the three-to-eight-lines decoder has 8 output lines it follows that 2 two-to-four-lines decoder components, dec_2x4 are needed for providing the required number of outputs. Input lines s[1 : 0] are used as selection lines for the 2 dec_2x4 units so that the units 4 output lines to be addressed by consecutive configurations. Selection line s[2] activates only one of the two dec_2x4 modules assuring proper sequencing of the two groups of 4 output lines generated at the dec_2x4 units outputs. The dedicated enable line activates selection of one of the two dec_2x4 decoders. The three-to-eight-lines decoder architecture uses: 2 two-to-four-lines decoders, dec_2x4 2 AND gates and, an inverter
Three-to-eight-lines decoder with enable input (contd.) Verilog code for the three-to-eight-lines decoder 1 module d e c 3 x 8 ( 2 i n p u t e, 3 i n p u t [ 2 : 0 ] s, 4 output [ 7 : 0 ] y 5 ) ; 7 d e c 2 x 4 i 1 ( 8. s ( s [ 1 : 0 ] ), 9. e ( e & s [ 2 ] ), 10. y ( y [ 7 : 4 ] ) 11 ) ; 13 d e c 2 x 4 i 2 ( 14. s ( s [ 1 : 0 ] ), 15. e ( e & ( s [ 2 ] ) ), 16. y ( y [ 3 : 0 ] ) 17 ) ; 18 endmodule