Assembly Language Programming. CPSC 252 Computer Organization Ellen Walker, Hiram College

Similar documents
Computer Science 324 Computer Architecture Mount Holyoke College Fall Topic Notes: MIPS Instruction Set Architecture

Instructions: MIPS ISA. Chapter 2 Instructions: Language of the Computer 1

Chapter 2. Instructions: Language of the Computer. Adapted by Paulo Lopes

Introduction to the MIPS. Lecture for CPSC 5155 Edward Bosworth, Ph.D. Computer Science Department Columbus State University

Topic Notes: MIPS Instruction Set Architecture

Unsigned Binary Integers

Unsigned Binary Integers

CS3350B Computer Architecture MIPS Instruction Representation

Computer Science 324 Computer Architecture Mount Holyoke College Fall Topic Notes: MIPS Instruction Set Architecture

COMPUTER ORGANIZATION AND DESIGN

MIPS R-format Instructions. Representing Instructions. Hexadecimal. R-format Example. MIPS I-format Example. MIPS I-format Instructions

Chapter 2A Instructions: Language of the Computer

Computer Organization MIPS ISA

Machine Language Instructions Introduction. Instructions Words of a language understood by machine. Instruction set Vocabulary of the machine

Chapter 2. Computer Abstractions and Technology. Lesson 4: MIPS (cont )

Computer Architecture

COMPSCI 313 S Computer Organization. 7 MIPS Instruction Set

Computer Organization and Structure. Bing-Yu Chen National Taiwan University

Chapter 3 MIPS Assembly Language. Ó1998 Morgan Kaufmann Publishers 1

Chapter 2. Instructions:

Computer Organization and Structure. Bing-Yu Chen National Taiwan University

Chapter 2: Instructions:

Computer Architecture

Instructions: MIPS arithmetic. MIPS arithmetic. Chapter 3 : MIPS Downloaded from:

Branch Addressing. Jump Addressing. Target Addressing Example. The University of Adelaide, School of Computer Science 28 September 2015

CISC 662 Graduate Computer Architecture. Lecture 4 - ISA MIPS ISA. In a CPU. (vonneumann) Processor Organization

CSCI 402: Computer Architectures. Instructions: Language of the Computer (3) Fengguang Song Department of Computer & Information Science IUPUI.

Chapter 2. Instructions: Language of the Computer

Stored Program Concept. Instructions: Characteristics of Instruction Set. Architecture Specification. Example of multiple operands

Lecture 2. Instructions: Language of the Computer (Chapter 2 of the textbook)

MIPS%Assembly% E155%

ECE232: Hardware Organization and Design. Computer Organization - Previously covered

CISC 662 Graduate Computer Architecture. Lecture 4 - ISA

Lecture 4: MIPS Instruction Set

Instructions: Language of the Computer

All instructions have 3 operands Operand order is fixed (destination first)

Computer Architecture. Chapter 2-2. Instructions: Language of the Computer

ELEC / Computer Architecture and Design Fall 2013 Instruction Set Architecture (Chapter 2)

Lecture 5: Procedure Calls

CS3350B Computer Architecture MIPS Introduction

CS/COE1541: Introduction to Computer Architecture

Instructions: Assembly Language

1 5. Addressing Modes COMP2611 Fall 2015 Instruction: Language of the Computer

MIPS Instruction Set Architecture (2)

Chapter 2. Instructions: Language of the Computer. HW#1: 1.3 all, 1.4 all, 1.6.1, , , , , and Due date: one week.

EEC 581 Computer Architecture Lecture 1 Review MIPS

ECE260: Fundamentals of Computer Engineering

MIPS (SPIM) Assembler Syntax

CS222: MIPS Instruction Set

ECE232: Hardware Organization and Design

Thomas Polzer Institut für Technische Informatik

EEM 486: Computer Architecture. Lecture 2. MIPS Instruction Set Architecture

Today s topics. MIPS operations and operands. MIPS arithmetic. CS/COE1541: Introduction to Computer Architecture. A Review of MIPS ISA.

comp 180 Lecture 10 Outline of Lecture Procedure calls Saving and restoring registers Summary of MIPS instructions

Lectures 3-4: MIPS instructions

ECE260: Fundamentals of Computer Engineering

CS31001 COMPUTER ORGANIZATION AND ARCHITECTURE. Debdeep Mukhopadhyay, CSE, IIT Kharagpur. Instructions and Addressing

Chapter 2. lw $s1,100($s2) $s1 = Memory[$s2+100] sw $s1,100($s2) Memory[$s2+100] = $s1

Architecture II. Computer Systems Laboratory Sungkyunkwan University

CS 61c: Great Ideas in Computer Architecture

Overview. Introduction to the MIPS ISA. MIPS ISA Overview. Overview (2)

Character Is a byte quantity (00~FF or 0~255) ASCII (American Standard Code for Information Interchange) Page 91, Fig. 2.21

Chapter 2. Instruction Set Architecture (ISA)

Control Instructions. Computer Organization Architectures for Embedded Computing. Thursday, 26 September Summary

Control Instructions

Instructions: Language of the Computer

Review. Lecture #9 MIPS Logical & Shift Ops, and Instruction Representation I Logical Operators (1/3) Bitwise Operations

Chapter 2. Instruction Set. The MIPS Instruction Set. Arithmetic Operations. Instructions: Language of the Computer

ENGN1640: Design of Computing Systems Topic 03: Instruction Set Architecture Design

Machine Instructions - II. Hwansoo Han

Communicating with People (2.8)

Instruction Set Architecture. "Speaking with the computer"

CENG3420 Lecture 03 Review

CS 61C: Great Ideas in Computer Architecture. MIPS Instruction Formats

Mark Redekopp, All rights reserved. EE 357 Unit 11 MIPS ISA

CS3350B Computer Architecture

MIPS Instruction Set

We will study the MIPS assembly language as an exemplar of the concept.

Instruction Set Architecture part 1 (Introduction) Mehran Rezaei

Chapter 1. Computer Abstractions and Technology. Lesson 3: Understanding Performance

Reduced Instruction Set Computer (RISC)

Systems Architecture I

Levels of Programming. Registers

Rui Wang, Assistant professor Dept. of Information and Communication Tongji University.

MIPS ISA. 1. Data and Address Size 8-, 16-, 32-, 64-bit 2. Which instructions does the processor support

5/17/2012. Recap from Last Time. CSE 2021: Computer Organization. The RISC Philosophy. Levels of Programming. Stored Program Computers

Recap from Last Time. CSE 2021: Computer Organization. Levels of Programming. The RISC Philosophy 5/19/2011

Chapter 3. Instructions:

Course Administration

Computer Science 61C Spring Friedland and Weaver. Instruction Encoding

Procedure Calling. Procedure Calling. Register Usage. 25 September CSE2021 Computer Organization

Computer Architecture. The Language of the Machine

Review of Last Lecture. CS 61C: Great Ideas in Computer Architecture. MIPS Instruction Representation II. Agenda. Dealing With Large Immediates

Computer Science 2500 Computer Organization Rensselaer Polytechnic Institute Spring Topic Notes: MIPS Programming

101 Assembly. ENGR 3410 Computer Architecture Mark L. Chang Fall 2009

CSE 141 Computer Architecture Spring Lecture 3 Instruction Set Architecute. Course Schedule. Announcements

CSSE 232 Computer Architecture I. I/O and Addressing

CS61C - Machine Structures. Lecture 6 - Instruction Representation. September 15, 2000 David Patterson.

EE 361 University of Hawaii Fall

CS 61C: Great Ideas in Computer Architecture MIPS Instruction Formats

Transcription:

Assembly Language Programming CPSC 252 Computer Organization Ellen Walker, Hiram College

Instruction Set Design Complex and powerful enough to enable any computation Simplicity of equipment

MIPS Microprocessor set (MIPS Technologies, Inc.) Used in digital consumer and business applications made by companies such as Cisco Nintendo Sony Typical of instruction sets designed since the 1980 s

MIPS Assembler 3-address instructions Example: add a,b,c #a = b+c How to compute d = a+b+c?

Why 3 addresses? For a binary operation it s natural: Two operands One result With fewer addresses: 2 address - fix result as one operand 1 address - fix one operand and result 0 address - fix locations of both operands and results (stack)

Recall: CPSC 171 Assembler To add A and B and store in C LOD A (into accumulator) ADD B (accumulator has A+B) STO C (now stored in memory) This is a one-address language - each operation refers to one (memory) address Advantage: relatively short instructions Disadvantage: longer programs Much simpler than real architectures today

0-address (Stack Machine) Push (load) and Pop (store) must take an address Push A (stack contains A) Push B (stack contains A, B) Add (stack contains A+B) Pop C (stack now empty, C = A+B) Even smaller instructions, even more of them

Another MIPS example d = (a-b) + (a-c) Sub d,a,b # d=a-b Sub e,a,c # e=a-c Add d,d,e # d=d+e Is this the best way?

Registers Special addresses where computation can take place Hardware separate from memory, connected directly to ALU MIPS registers are 32-bits, also called one word MIPS has 32 registers

Why Limit Number of Registers? Each adds specialized hardware Additional cost (area, power) More registers are slower Time for signal to travel More registers require bigger words More bits to represent register #

Registers in MIPS Assembler Each register has a name, beginning with $ Convention: $s0, $s1 variables $t0, $t1 temporary (intermediate values) We ll learn others later; all begin with $

Revised example d = (a-b) + (a-c) Assume $s0 = a, $s1 = b, $s2 = c, $s3 = d Sub $t0, $s0, $s1 Sub $t1, $s0, $s2 Add $s3, $t0, $t1

Try it! Assume: a in $s0, b in $s1 c in $s2 a = (a + b) (c + c) Use only add and sub instructions

Moving Data Between Memory and Registers Data (variables) stored in memory Move to/from registers for computation Load / Store word (lw, sw) instructions Three operands: Destination register Offset (fixed value) Register (base address)

Using Offset and Register Offset is a fixed value, measured in bytes Register s value added to offset to compute the final address Why? Register has more bits than offset Register contents can change during execution

Realistic uses of base & register A[j] lw $t0, j*4, $s0 offset = j*4 Base register contains address of A obj.field lw $t0, field, $s0 Offset = field (offset from beginning of obj) Base register contains address of obj

Example Given array A (address in $s0) Goal: load A[1] into $t0 Instruction Lw $t0, 4 ($s0) # note 1 word = 4 bytes

Another example Addresses of A, B, C are in $s0+a, $s0+b, $s0+c ($s0 is beginning of variable block ) Compile: C = A+B Lw $t0, A($s0) Lw $t1, B($s0) add $t0, $t0, $t1 #assume ok to reuse $t0 sw $t0, C($s0) #store value at C

Try it! Assume base of a is $s0, base of b is $s1, c is $s2 c = a[1]+b[1]

Try it! Class Point { int x; int y; void xdiff (Point p1, Point p2) { int ret = p2.x p1.x + p2.y p1.y } } Assume p1 is $s1, p2 is $s2, ret is $s3

Adding a constant To add a constant to a variable: A = A+4 Lw $t0, 0($s0) # assume $s0 contains address of A Lw $t1, 0($s1) # assume $s1 contains address of a 4 in memory Add $t0, $t0, $t1 Sw $t0, 0($s0)

Disadvantages All constants must be pre-stored in memory Extra register used for each constant Additional loads slow down the program

Immediate Values Use an operand slot for a small number rather than a register The non-register operand is called immediate Operations: Add immediate (addi)

Using Immediate Values To add a constant to a variable: A = A+4 Lw $t0, 0($s0) # assume $s0 contains A Addi $t0, $t0, 4 Sw $t0, 0($s0)

Binary Integers (Review) In the binary system, each bit refers to a power of two: 01011 (2) = 0*2 4+ 1*2 3 +0*2 2 +1*2 1 +1*2 0 = 11 (10) Negative numbers use two s complement: -01011 (2) = 10100 + 1 = 10101 (2) Negative numbers have leading 1 s, while positive numbers have leading 0 s.

Hexadecimal (review) Hex is base 16 Every hex digit represents 4 bits: 0 = 0000, 1 = 0001, 2 = 0010, 3 = 0011 4 = 0100, 5 = 0101, 6 = 0110, 7 = 0111 8 = 1000, 9 = 1001, A = 1010, B = 1011 C = 1100, D = 1101, E = 1110 F = 1111

MIPS machine language Portions of the instruction are represented by binary numbers Operation code (opcode) = 12 bits 6 at beginning (op); 6 at end (funct) Registers (32 possible) = 5 bits each $s0 = 16 $s7 = 23, $t0 = 8 $t7 = 15 Not yet used field = 5 bits

ADD $t0,$s1,$s2 instruction 000000 10001 10010 01000 00000 100000 000000 (operation = 0) op 10001 (register 17 = $s1) rs register source 1 10010 (register 18 = $s2) rt register source 2 01000 (register 8 = $t0) rd register destination 00000 (unused field) shamt shift amount 100000 (function = 32) funct Hex representation: 02324020

Format for Immediate Immediate operations also 32 bits Instead of 3 registers, we have 2 registers + an immediate field If we used only one register s bits, we could have only 32 immediate values Use all remaining 16 bits (rd,shamt,func) for immediate value How many values can we have now?

Summary of Instruction Formats (so far) R-type (register) Op(6), rs(5), rt(5), rd(5), shamt(5), funct(6) I-type (immediate) Op(6), rs(5), rt(5), constant or address (16) Used for immediate instructions and also load/ store Register rt is source for sw, dest for lw, addi, etc.

Logical Operations Shift Shifts bits to left or right, filling in with 0 s sll (shift left logical) srl (shift right logical) Bitwise logical And, andi rd = rs & rt Or, ori rd = rs rt Nor rd =! (rs rt)

Examples Sll $t2, $s0, 4 Shift $s0 left by 4 bits & put result in $t2 Effectively multiplies $s0 by 2^4 And $t2, $s0, $s1 $t2 has 1 only when both $s0 and $s1 have 1 in corresponding bit (otherwise 0) Ori $t2, $s0, 15 Copies $s0 into $t2 except sets the last 4 bits to 1 (because of OR with 000.1111) Nor $t2, $t1, $zero # $zero is a reg. fixed to 0 $t2 gets not $t1 (Why?)

Control Structures The only control structures are jumps (also called branch in MIPS) Conditional branches: Beq reg1, reg2, addr (branch on equal) Bne reg1, reg2, addr (branch not equal) Unconditional jump: J addr

IF Example #If (a == 0) a=a+c else a=a+b Lw $t0, A($s0) Bne $t0,$zero,else Lw $t1, C($s0) #we will add c J DONE ELSE: lw $t1, B($s0) #we will add b DONE: add $t0, $t0, $t1 #do the add here Sw $t0, A($s0) #save the result

Loops While loop (test at top) Conditional branch at beginning (to jump beyond the loop) Unconditional branch at end (to return to the top) Until loop (test at end) Conditional branch at bottom Loop body executes at least once

Try it! //Assume sum = sum($s0), val = val($s0), N = N($s0) int sum = 0; int val = 0; while (val!= N){ sum = sum + val; val++;}

Testing for inequality First set a register with a flag based on comparison Slt $t0, $s1, $s2 (t0=1 if s1<s2, else 0) Slti $t0, $s1, 1 (t0=1 if s1<1, else 0) Next, use beq or bne as appropriate Beq $t0, $zero (branch if s1>=s2) Bne $t0, $zero (branch if s1< s2)

Case / Switch statement First create an array of possible locations to jump to This is the jump address table Next, jump to the right value in the table

Switch example: Switch(x){ 0: a=b&c; break; 1: a=b+c; break; 2: a= b-c; break; } Jump table at jumptable: AND PLUS MINUS

Switch Example continued # Assume x in $s0, A in $s1, B in $s2, C in $s3 Sll $s0, 2 -- multiply s0 by 4 (bytes/word) Lw $t0, jumptable($s0) -- address from table Jr $t0 -- jump to address of $s1 -- jump register AND: and $s1,$s2,$s3 J done PLUS: add $s1, $s2, $s3 J done MINUS: sub $s1, $s2, $s3 DONE:

MIPS and Strings So far, we ve seen mostly instructions for manipulating integers Many programs also deal with strings Strings are tricky because they don t have a fixed length Ascii characters are 1 byte (really 7 bits) Java characters are 2 bytes (16 bits), also called halfword

Reading Characters You could do it with existing methods Load the right word, then shift right to get the right character at the end of the register Assume $s0 has address *of 8-bit character* Andi $t0, $s0, 0xfffffffc # make last 2 bits 0 Lw $t1, 0($t0) Andi $t0, $s0, 00000003 #get only last 2 bits #use $t0 as basis for a case statement!

Reading characters (cont d) Sll $t0, 2 # Now what is in $t0 Lw $t2, TAB($t0) Jr $t2 ONE: srl $t1, 4 J DONE TWO: srl $t1, 8 J DONE THREE: srl $t1, 12 DONE: andi $t1, 0x000000ff #TAB on next page

Data needed.data TAB:.word THREE.word TWO.word ONE.word DONE

3 Kinds of Load All load into end of register, pad with 0 s if necessary Load byte (8 bits) lb register, address (all possible) Load halfbyte (16 bits) Lh register, address (divisible by 2) Load word (32 bits) Lw register, address (divisible by 4)

3 Store Instructions sb register, address Stores last 8 bits of register into address Sh register, address Stores last 16 bits of register into address divisible by 2 Sw register, address Stores full register into address divisible by 4

Variable Length Strings C style strings (e.g. abc ) really end with a 0 character. abcdefg => 61626364 65666700 (note: 61 is Ascii for a )

Copying a String Array version void strcpy(char [] x, char[] y){ int i = 0; while (x[i]!= 0){ y[i] = x[i]; i++; }}

Copying a String C code pointer version //remember char* x means x is a pointer to a character void strcpy(char* x, char* y){ while (*x!= 0){ *y = *x; x++; y++ }}

Large Immediate Values Sometimes it s useful to be able to load a large value into a register, e.g. an address BUT, we can only have 16-bit immediate values Instruction lui (load upper immediate) loads 16 bits into the high bits of a word

Example Loading 0x1fff2cff into $s0 lui $s0, 0x1fff # load 1f into high bits (and zero out low bits) ori $s0, 0x2cff # fill low bits

Another Useful PseudoInstruction Load address (la) Allows you to copy an immediate address (e.g. label) into a register Example la $s1, myarray.data myarray:.word 25

MIPS Addressing Modes Register addressing Address is contained in register, e.g. jr or add Base or displacement addressing Address is sum of register and constant in instruction, e.g. lw PC-relative addressing Address is sum of PC and 16-bit constant (bne) Pseudo-direct addressing Address is top 6 bits of PC followed by 26 bits in instruction (j)

Addressing Examples Assume an instruction is in 0x10001004 If the instruction is: jr $s0 (and $s0 contains 16) jump to location 16 bne $t0, $t1, 16 jump to location 0x10001014 (current + 16) j 16 jump to location 0x10000010 (top 6 bits of current + 16)

Summary of Instruction R-type (register) Formats Op(6), rs(5), rt(5), rd(5), shamt(5), funct(6) I-type (immediate) Op(6), rs(5), rt(5), constant or address (16) Used for immediate instructions and also load/store Register rt is source for sw, dest for lw, addi, etc. I-type also used for be, bne. 16 bits of (+/-) immediate value added to PC J-type (jump) Op (6), address (24) Address concatenated with first 6 bits of PC to compute jump address

Supporting Procedures Make parameters accessible ($a0-$a3) Transfer control to the procedure (jal) Get resources needed for the procedure Perform the task Make the result accessible ($v0-$v1) Return to the calling program (jr $ra, where $ra = return address)

Calling and Returning To call a procedure: Place parameters in $a1 - $a3 jal (jump and link) Stores return address (PC + 4) in $ra (31) Push register values onto stack (if they will be used) To return: Place results in $v0 - $v1 Pop register values off stack Jr $ra (jump register)

Pushing onto Stack $sp is top of stack Stack grows upwards in memory (!) Therefore, to put registers $s1 and $s2 on stack: addi $sp, $sp, -8 sw $s1, 0($sp) sw $s2, 4($sp)

Popping Registers lw $s1, 0($sp) lw $s2, 4($sp) addi $sp, $sp, 8

Contents of an Object File Header Text segment (contains code) Static Data segment (contains global static data) Relocation information (internal labels) Symbol table (external labels) Debugging information

Simplified Object File in MIPS.text #start of text main: #use main as label to start code code goes here.data #beginning of data segment data goes here.end #use for SPIM, not for MARS

Specifying Data Pseudoinstructions make data layout easier.word 100 #(4 bytes).byte 25, 32, 41, 99 #(4 bytes).asciiz cat #(4 bytes, including \0 ).space 4 #(4 unspecified bytes)

Local vs. Global labels Local labels (with respect to the beginning of the text segment) label: (before instruction) Global labels (with respect to $gp).globl labelg (any time before label) labelg: (before instruction)

For More Information Green card in your textbook Chapter 2 SPIM web page http://www.cs.wisc.edu/~larus/spim.html