How to Integrate FPGAs into a Computer Organization Course

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How to Integrate FPGAs into a Computer Organization Course Michael J Jipping jipping@cs.hope.edu Sara Henry sara.henry@hope.edu Kathleen Ludewig kathleen.ludewig@hope.edu Leslie Tableman leslie.tableman@hope.edu ABSTRACT A crucial part of the Computer Organization course is the examination of and experimentation with digital logic circuits. In departments with limited budgets, however, this activity can be problematic. Due to historical roots and enrollment sizes, departments tend to focus on software aspects of computer science. This means that hardware concerns are often relegated to textbook and paper-and-pencil examination. This paper details how to use field programmable gate arrays hardware gates with a programming interconnection switch in the Computer Organization course. We will overview the reasons for using them, outline ways to use them effectively and cheaply, and demonstrate FEWD, our system for integrating visual design with FPGAs for student experimentation. Categories and Subject Descriptors K.3 [Computers & Education]: Computer and Information Science Education Computer Science Education. General Terms Experimentation, Design, Human Factors Keywords FPGA, computer organization, digital logic circuit, simulation 1 INTRODUCTION In the computer science curriculum, the Computer Organization course stands out by virtue of its requirements. The course is introductory by nature and needs to be approachable by most first-year students. It combines discrete mathematics with hardware design and assembly language programming. It requires that new and difficult subject matter be delivered to the student through hands-on experimentation-based activities. Active learning and experimentation in a Computer Organization course can be difficult because of the variety of material in the course and the speed with which it is delivered. In addition, the course focuses on hardware aspects of computer science and these aspects can be difficult to demonstrate. Breadboards are inexpensive, but limited in use; full-blown fabrication systems are too expensive and unnecessary for this type of use. This paper documents a system design that we are using to facilitate the use of inexpensive field programmable gate arrays (FPGAs) as hardware experimentation platforms in our Computer Organization course. We will begin with our motivation and how FPGAs fit into our Computer Organization course. We will then outline the methods we use to integrate FPGAs with visual design systems to minimize learning curves. We will conclude with some suggestions on pedagogical ways to include FPGAs using our methods. 2 BACKGROUND AND MOTIVATION The Computer Organization course is often a course with several, often separate, modules. This course is meant to allow students to apply discrete mathematics concepts to digital logic design, to briefly explore computer architecture, and to dabble in assembly language programming, often as a way to exemplify the circuit and architecture material. Along the way, students are asked to experiment in all of these areas. It is a fast-paced course with little time to spend learning development systems. Because of these constraints, the digital logic portion of the course is often taught using pencil-and-paper circuit design or by using simulation systems that require only a small learning

curve. Systems like the Iowa Logic Simulator [4], xlogiccircuits[2] or DLSim [1] all require little in the way of learning curve and provide an adequate simulation environment. However, these simulation systems do not provide the possibility of a real implementation. A real implementation environment would be able to give valuable experience as to the constraints of real systems, would allow a student to experiment with systems that he or she might actually design circuits for, and would support active learning and experimentation in ways that a simulation environment can not. Note that, if real hardware systems were to be injected into the Computer Organization course, the constraints of the course still remain the same. This means that the learning curve must be easy to ride over and the system used must integrate with existing tools that make the course move along quickly. We have developed FEWD (FPGAs in Education With DLSim) as a way to integrate a simulation environment with industry standard FPGA hardware. We use an off the shelf FPGA system that has many industrial uses and we integrate it with a visual simulation and development environment that is in use in many schools. The result is a real hardware system that shoehorns cleanly into the Computer Organization course, giving students an effective hardware experimentation platform. 3 CIRCUIT DESIGN AND DEPLOYMENT Our goal was to have students visually design a circuit and then test that design on hardware without having to spend much time learning to deal with how to use the hardware. To accomplish this task we have streamlined a transformation process so that the student has only three steps from visual design to hardware implementation. The student creates and saves a circuit in DLSim 2.2, invokes a Perl script, which translates the circuit design and downloads it to the FPGA, and then interacts with the circuit as it runs on the hardware. 3.1 Choosing the Design Platform Choosing the visual design tool for students to work with was the crucial first step. We reviewed technology used to teach logic circuit design as discussed in the literature [5]. These references directed us to many good simulators, including Digital Workshop [3], Multimedia Logic [5], DLSim, and xlogiccircuits. We developed a set of criteria that we applied to all simulators. We analyzed such features as the graphic user interface, ease of use, ability to debug, save and load functions, and the ability to make embedded circuits. Embedded circuits are particularly important. These are previously created circuits that are inserted into another circuit without displaying the inner workings of itself, thus adding it as an abstraction. The use of embedded circuits simplifies the visual display of a circuit, making it easier to manipulate and easier to debug. In addition, it fits with the student s understanding of object orientation and abstraction concepts. We included in our evaluation an analysis of a tool from Xilinx. Xilinx is one of the top distributors of FPGAs and they distribute free software that can be used to create circuits and download them onto a FPGA. The two applications provided by Xilinx are ModelSim and ISE Webpack [7]. We included these tools in our evaluation. We chose DLSim to be our design platform. It has a simple user interface that makes learning how to use the software easy. In addition, the implementation of embedded circuits in DLSim is easy and straightforward. To create an embedded circuit in DLSim, the user loads in a saved circuit, which differs from some of the other simulators that we had looked at. DLSim s method of inserting embedded circuits allows the user to create a simple circuit only once that can be imported into any future circuits. Other simulators that we evaluated allowed the users to turn a simple circuit within another circuit into an embedded circuit only for visual purposes, which meant that the simple circuit had to be recreated each time it was needed in a new circuit. DLSim's ease of use is what set it apart from all of the other simulators that we evaluated. It is a simple program that students will be able to understand and it provides visual output that we felt would increase a student s understanding of digital logic. DLSim allows its users to turn switches on and off, automatically displaying the effect that it has on the circuit. This allows the user to easily debug a circuit, plus it highlights the inner workings of the circuit. DLSim also has an option to save a circuit in XML. Having the circuit in XML presented a number of different possibilities for us and enabled the conversion process from design to FPGA. Figure 1: Diagram of the streamlined process to get a circuit in XML downloaded onto an FPGA

3.2 Moving the Circuit Design to an FPGA The most challenging part of this project was designing the process of transferring a circuit design from the visual representation in DLSim to the FPGA hardware that students can manipulate for hands-on interaction with their circuit. In order to make the process of downloading a circuit manageable for students, it is necessary to provide a way to hide the different programs that need to be used. We decided to streamline the process by using Perl. There are a total of eight steps involved in transferring a circuit designed in DLSim to the FPGA. Each of these steps, except the first, is executed by a Perl script. The individual scripts are controlled by an umbrella Perl script that the students execute from the command line. This whole process runs in a Windows environment. We have outlined the steps in the transformation system below and depicted them in Figure1. 1. Design a circuit The process begins as the student designs his or her circuit in DLSim. After designing the circuit, the student is required to save it in XML format, which is an option offered by DLSim. 2. Pre-process the circuit In order for the translation process to work correctly, there are certain guidelines that the students must follow. Most of the requirements can be easily checked in the XML code, so a Perl script checks the XML and makes sure the circuit is ready for translation. the limited nature of variables in XSLT. The script outputs a new VHDL file. 7. Translate VHDL and pin specification into a bit file The final step is to create a downloadable file in a format that can control the hardware. We developed a batch file that would successfully run Xilinx ISE to achieve this. 8. Transfer onto FPGA The last step is to transfer the circuit onto the FPGA. Xilinx s software package includes a program that does the transferring. It has command line capabilities, so we wrote a batch file that would take care of the process without opening the program s GUI. We use the Spartan 3 FPGA and starter kit from Xilinx for our FEWD system [8]. 3.3 An Example Consider an example to demonstrate the entire design process. First, a student will design a circuit in DLSim. Figure 2 depicts a simple circuit as drawn in DLSim. This circuit takes two fourbit inputs labeled A0 through A3 and B0 through B3 - - and produces their sum on outputs labeled Sum0 through Sum3. The boxes labeled fulladder2 are embedded circuits, quite probably circuits designed in class as examples and provided to students to use. (Many circuits designed in class are provided as embedded circuits for students to build their designs on.) 3. Generate individual XML files Any embedded circuits within the main circuit need to have their own XML files for the rest of the system to work properly. A Perl script pulls the necessary XML code from the main circuit and creates a new file with it. 4. Generate pin specification In order to manipulate the input and view output of a circuit on the FPGA, the switches, bulbs, and LEDs must be assigned to the corresponding places on the FPGA where the input and output are located. The process of assigning pins and knowing which ones to assign was one of the more confusing parts of the software, so we developed an XSLT script that would do this for the students. However, for the process to work correctly, the students do have to conform to guidelines, which they will receive with the specification on how to use the process we developed. The XSLT schema produces a file which Xilinx ISE references to create the final download format. 5. Translate circuit into VHDL We use Xilinx ISE software to download the circuit design to the FPGA hardware. ISE needs circuits described in VHSIC Hardware Design Language (VHDL), so we developed an XSLT script that translates DLSim s XML into VHDL. 6. Insert signals into the VHDL The VHDL file that is created by the XSLT program is then passed to another Perl script. This script checks for any open connections and inserts any needed signals, which are needed if one gate is connected to another gate. This step was necessary due to Figure 2: Four-bit Adder in DLSim After designing the four-bit adder circuit, the student must then save the circuit in the native.cct file format of DLSim. Once the.cct file has been saved, the user must also save the circuit as an XML file. The XML generated from the above diagram would look something like the fragment: <circuit name="fulladder8"> <circuit name="fulladder2">... </circuit> <switch id="fulladder8:switch0" label="a0">

<switch id="fulladder8:switch1" label="a1"> <switch id="fulladder8:switch2" label="a2"> <switch id="fulladder8:switch3" label="a3"> <switch id="fulladder8:switch4" label="b0"> <switch id="fulladder8:switch5" label="b1"> <switch id="fulladder8:switch6" label="b2"> <switch id="fulladder8:switch7" label="b3"> <bulb id="fulladder8:bulb8" label="sum0"> <bulb id="fulladder8:bulb9" label="sum0"> <bulb id="fulladder8:bulb10" label="sum1"> <bulb id="fulladder8:bulb11" label="sum2"> </circuit> The student then invokes a Perl script with the name of the circuit as input in this case fulladder8. This Perl script checks to make sure that a student has included their name, assignment, and date as labels in DLSim and followed the designated restrictions on the number of inputs and outputs. The Perl script prints out its progress every step of the way, letting the student know which files have been retrieved, created, and deleted during the transformation process. If the student followed the guidelines, the Perl script will invoke the XSLT files that will convert the circuit to VHDL and assign pins for the inputs and outputs. The resulting VHDL code will then be checked by the Perl script for loose connections and will insert any necessary signals for connections between gates and wires. One VHDL file is generated for each circuit tag, so there will be two VHDL files, circ_fulladder8.vhd and circ_fulladder2.vhd, created in this example. The file circ_fulladder8.vhd will appear as: entity circ_fulladder8 is port ( Switch0 : in Switch1 : in Switch2 : in Switch3 : in Switch4 : in Switch5 : in Switch6 : in Switch7 : in Bulb8 : out Bulb9 : out Bulb10 : out Bulb11 : out end circ_fulladder8; std_logic := '0'); architecture BEHAVIORAL of circ_simple is component Wire port ( I : in O0 : out O1 : out std_logic); end component; component circ_fulladder2 port (Switch0 : in Switch1 : in Switch2 : in Bulb3 : out Bulb4 : out std_logic); end component; begin end BEHAVIORAL; The Perl script will next invoke Xilinx ISE to translate the VHDL into a binary file that can be downloaded onto the FPGA. Once the circuit is on the FPGA, the student may interact with the input by using the switches and buttons on the FPGA. 3.4 Working With the FPGAs The Spartan-3 FPGAs that we used for this project have many possibilities for interactions with humans. We used a $99 Spartan-3 starter kit that came with everything we needed. Specifically, the board has the following features which were useful: eight slide switches for input four momentary-contact connection ports buttons also used for input eight individual LED outputs, corresponding to bulbs in the DLSim design four 7-segment LED digit displays, corresponding to an LED component built into DLSim These simple I/O devices match components built into DLSim and can be directly added to circuits. A 50 MHz clock is also available on the Spartan-3 board and is directly matched to the clock component built into DLSim. In addition, there are several, more complicated, I/O devices that are available for programming: 9-pin RS-232 serial port PS/2- style mouse/keyboard port 3-bit, 8-color VGA display port 4 Exercises and Assignments Using FPGAs Because DLSim is easy to use and the processes of translation and downloading is quick, in-class laboratory exercises are easy to do and more extensive, out-of-class assignments are possible. Here we outline some suggestions from our use of FPGAs. Time to get acquainted: The first experience with FPGAs can come from class/laboratory. Simple circuits that showcase basic components discussed in class are excellent candidates for demonstrating how FPGAs work. In our classes, this has included basic combinational circuits like shifters, decoders, and adders. We then demonstrate memory circuits and form registers. Finally, we put the circuits together in a simple counter that displays results on the digit LED outputs.

Build elemental CPU components: We then take these basic components and build a simple CPU. By using the input buttons, we can enter eight-bit instructions followed by optional eight-bit data operands. Our simple CPU includes ALU operations and memory circuits and uses the digit LED outputs. This assignment showcases the use of abstract components and takes about 1.5 weeks. The Little Man Computer: The final project involves implementing the Little Man Computer [9] in FPGA hardware. The Little Man Computer uses the basic elements of a von Neumann architecture and has a simple operation that can be seen on Web applets before implementation. Each component of the computer can be designed and implemented separately and put together as abstract components in DLSim. It is very well suited for Spartan-3 implementation because the input is limited to eight-bit instructions, which are input to memory before program execution, and because it uses digits LEDs as output. This assignment takes about 3 weeks. For our Computer Organization class, we introduce students to the FPGAs (the get acquainted part) with in-class experimentation through labs. We also experiment with the elemental CPU components through in-class labs. We allow the Little Man Computer project to overlap with the assembly language part of our course. 5 Conclusion This paper has presented a system that combines the visual design capabilities of DLSim with the hardware components of the Xlinix Spartan-3 FPGA platform. Our system is called FEWD: FPGAs in Education with DLSim. We described the various components and the stepwise transformations that comprise FEWD. We outlined the advantages of using FEWD and gave suggestions about how to use FEWD in class. This paper reflects our use of FEWD at. References [1] DLSim 2.2, available online: http://www.cs.hope.edu/fewd [2] Eck, D., The Most Complex Machine: A Survey of Computers and Computing, A.K. Peters, Ltd, 1995. [3] Fishwick, P. Digital Workshop, available online: http://www.cise.ufl.edu/~fishwick/dig/digsim.html [4] Jones, D.W., The Iowa Logic Specification Language, available online: http://www.cs.uiowa.edu/~jones/logicsim [5] Softronix, Inc, Welcome to Multimedia Logic, available online: http://www.softronix.com/logic.html [6] Wolfe, G., W. Yurcik, H. Osborne, M. Holliday. Teaching Computer Organization/Architecture With Limited Resources Using Simulators. Special Interest Group on Computer Science Education (SIGCSE), Association for Computing Machinery (ACM). [7] Xilinx ISE Webpack, available online: http://www.xilinx.com/ise/logic_design_prod/webpack.htm [8] Xilinx Spartan 3 Starter Kit, for more information go to: http://www.xilinx.com/products/silicon_solutions/ fpgas/spartan_series/spartan3_fpgas/index.htm [9] Yurick, W and Brunbaugh, L., A Web-based Little Man Computer Simulator, Proceedings of the 32nd SIGCSE Technical Symposium on Computer Science Education, March 2001. Currently, FEWD uses basic I/O abilities built into the Spartan-3 FPGA system. Future developments of FEWD will include the design of abstract components in DLSim that will allow more I/O devices to be used. In particular, the mouse port and the VGA port are two inviting I/O possibilities. Also, using this system in our Computer Architecture course is a possibility. This way of using FEWD would require the design of a more extensive CPU with multiple implementations of various components (for example, various sizes of L1 and L2 caches) to allow for experimentation. More information on FEWD can be found at http://www.cs.hope.edu/fewd Acknowledgement The work described in this paper was performed under a CCLI program award from the National Science Foundation, award number DUE-0310757.

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