What is an Addressing Mode?

Addressing Modes 1

2

What is an Addressing Mode? An addressing mode is a way in which an operand is specified in an instruction. There are different ways in which an operand may be specified in an instruction. An operand may be specified using the immediate, direct, extended, indexed, and inherent modes. Different addressing modes are required in programs for processing implied numbers, constants, variables, and arrays. 3

IMMEDIATE ADDRESSING MODE Example: ADDA IMM Example instruction: ADDA #$33 The addressing mode IMM is identified and distinguished from the other addressing modes by the # symbol. This instruction adds the 8-bit number $33 to ACCA. In RTL: A A + $33 The previous value of ACCA is overwritten by the result of the addition, on purpose. For example, if ACCA = $12 initially, then, after the instruction ADDA $33 executes, ACCA will have $45. ADDA #$33 Can also be written as: ADDA #51 # Signifies IMMediate addressing mode (IMM) $ Signifies Hexadecimal number Signifies Decimal number 4

PC MAR MEMORY OCR ADD 0100 1 0100 1 8B 1 8B ACCA IMM 0101 2 0101 2 33 2 A + 33 A 0102 The first mop fetches the opcode. The opcode 8B conveys the following information to the CCU, that: 1. It must do an ADD operation 2. The 1 st operand is ACCA 3. The 2 nd operand is specified using the IMM addressing mode. The 2 nd mop performs the addition It gets the 2 nd operand by reading the 2 nd byte of the instruction It adds this byte to the present contents of ACCA It stores the result in ACCA, thus overwriting the previous contents of ACCA. 5

φ1 φ2 PC MAR MEMORY OCR 0100 1 0100 1 8B 1 8B ADD ACCA IMM 0101 2 0101 2 33 2 A + 33 A 0102 6

GENERAL FORMAT (TEMPLATE) ADDA IMMEDIATE PC MAR MEMORY OCR 0100 1 0100 1 8B 1 8B ADD ACCA IMM 0101 2 0101 2 2 A + A 0102 Location Machine Code 0100 8B 0101 0102 Opcode of Next Instruction Note that for the general format, the actual number to be loaded into ACCA is not specified, but a symbol ( ) for it is specified. : 8-bit Immediate 2 nd Operand. Represents 2 Hex Symbols. Represents any 8-bit Data. represents one Hex symbol, i.e., 4-bits. : immediate, immediate 7

ADDA IMM 68HC11 Data Sheet Information (From course web site) ADDA IMM means Add memory (M) to ACCA, and store the result in ACCA: A + M A The memory term in Add memory to ACCA refers to the 2 nd byte (ii) of the instruction: 8B ii The 1 st operand is implied to be ACCA. The 2 nd operand is actually stored in the instruction, so when the μp fetches the specification of the 2 nd operand, the 2 nd operand is available immediately, hence the name IMM. 8

ADDA IMM 68HC11 Data Sheet Information (From course web site) The template of the complete instruction is encoded as: 8B ii Note that when you provide the machine code of an instruction, you will replace the with the actual value you want to load into ACCA. It takes 2 clock cycles to execute, and two bytes to store. The NZVC bits in the CCR are updated, as indicated by the delta symbol, which means that these bit will either be set or clear, depending on the result of the instruction. 9

IMM ADDRESSING MODE 2 nd OPERAND IS A CONSTANT A program (list of instructions) is stored in non-volatile memory (e.g., ROM, FLASH, or a hard disk). In the IMM addressing mode, the actual value of the 2 nd operand is stored in the instruction itself. Location Machine Code 0100 8B 0101 ii 0102 Next Opcode This means that the 2 nd operand cannot be changed once the program is written into ROM. This is very clear in the case when the program is stored and run from a ROM. FLASH memories are considered ROM from the point of view of non-volatililty. Typically programs are copied from non-volatile memory (e.g., ROM, FLASH, and hard disk) to RAM because RAM has faster access times and programs run faster when they run from RAM. But, programs are never copied back to non-volatile storage. Thus, the 2 nd operand must be treated as a constant, that cannot be changed in the program stored in ROM. 10

IMM Mode Summary IMM General Form: ADDA #$ii From: Instruction set Manual General Assembly Language Form: For any addressing Mode Example Assembly Language ADDA #$33 # Signifies IMMediate addressing mode (IMM), and # distinguishes IMM mode from other modes. A A + $33 = A + $33 Example Machine Code 8B 33 $ Signifies Hexadecimal number General Machine Code Memory Address Data 00FF 0100 8B 0101 33 0102 ii 11

The IMM addressing mode is used when we know the value of the number we want to operate on and the value will not change, i.e., the number is a constant. The IMM addressing mode cannot be used when we require to add, subtract, or generally process variables. If we need to process variables, then we can use the Direct, Extended, or Indexed addressing modes. These addressing mode permit processing of variables. 12

EXTENDED ADDRESSING MODE Example: ADDA EXT Example instruction: ADDA $0133 The addressing mode EXT is identified and distinguished from the other addressing modes by the presence of a 16-bit address of the 2 nd operand, and the absence of the # symbol to distinguish it from the IMM mode. This adds the contents of memory location $0133 to ACCA. In RTL: A A + ($0133) The previous value of ACCA is overwritten by the result of the addition, on purpose. For example, if ACCA = $12 initially, and ($0133) = $10, then, after the instruction ADDA $0133 executes, ACCA will have $22. ADDA $0133 The absence of the # symbol, together with a 16-bit address, signifies EXTended addressing mode (EXT) 13

ADDA EXTENDED ADDA EXT (Ex: ADDA $0133) PC 0100 0101 MAR 1 0100 MEMORY 1 BB 2 0101 2 01 2 OCR 1 BB ADD ACCA EXT Location Machine Code 0100 BB 0102 0103 3 0102 3 33 3 0133 4.. vv 4 A + vv Α ACC A 0101 01 0102 33 0103 Next Opcode 0133 Temporary holding register 4 14

TIMING: EXTENDED ADDRESSING MODE EXAMPLE: ADDA $0133 φ1 φ2 PC 0100 0101 0102 0103 MAR 1 0100 MEMORY 1 BB 2 0101 2 01 2 3 0102 3 33 3 0133 4.. OCR 1 BB ADD ACCA EXT vv 4 A + vv Α ACC A 0133 Temporary holding register 4 15

ADDA EXT Memory Access Since, the address of the 2 nd operand is specified by 16-bits, the EXT mode of addressing can access the entire memory space: 2 16 = 64K Central Processing Unit (CPU, i.e., μp) Memory: RAM, ROM, FLASH, etc, Input/Output (I/O) Controllers 16 8 16 8 16 8 ABUS CBUS DBUS 64K x 8 Memory Space 0000 0001 00FE 00FF 0100 0101 01FE 01FF 0200 0201 FEFF FF00 FF01 FFFE FFFF Entire Memory Space 16

ADDA EXT 68HC11 Data Sheet Information (From course web site) ADDA EXT is a general description. It means add memory to ACCA, and store the result in ACCA: A + M A memory refers to the contents of the address of the 2 nd operand. The address of the 2 nd operand is part of the instruction: BB hh ll The address of the 2 nd operand is specified by 16-bits. The complete instruction is encoded as: BB hh ll It takes 4 clock cycles to execute. The NZVC bits in the CCR are updated, as indicated by the delta symbol. 17

From: Instruction set Manual General Form: ADDA $hhll Assembly language Example Absence of # and presence of 16-bit address signifies EXTended addressing mode (EXT) ADDA $0133 $ Signifies Hexadecimal number A A + ($0133) = A + vv Machine code Example BB 01 33 Template Memory Address Data 00FF 0100 BB 0101 01 0102 33 0133 vv hh ll 18

EXTENDED ADDRESSING MODE The EXT addressing mode permits processing of variables in any location of the memory space, since the 2 nd operand is specified by a 16-bit address. Sometimes, variables are stored in the 1 st page of memory, which requires only an 8-bit address. The DIRect addressing mode is conceptually the same as the EXT mode, except that the address of the 2 nd operand is specified using only 8-bits. The DIRect addressing mode can be used to access variables in the 1 st page of memory, only. The DIR addressing is more efficient than the EXT mode because it requires less space to store, and it runs faster. 0000 0001 00FE 00FF 0100 0101 01FE 01FF 0200 0201 FEFF FF00 FF01 FFFE FFFF 1 st Page 2 nd Page 256 th Page 19

DIRECT ADDRESSING MODE Example: ADDA DIR Example instruction: ADDA $33 The addressing mode DIR is identified and distinguished from the other addressing modes by the presence of an 8-bit address of the 2 nd operand, and the absence of the # symbol to distinguish it from the IMM mode. This adds the contents of memory location $0033 to ACCA. In RTL: A A + ($0033) The previous value of ACCA is overwritten by the result of the addition. For example, if ACCA = $12 and ($0033) = $10 initially, then, after the instruction ADDA $33 executes, ACCA will have $22. ADDA $33 The absence of the # symbol, together with an 8-bit address, signifies DIRect addressing mode (DIR) 20

ADDA DIRECT CYCLES Example: ADDA $33 PC 0100 0101 MAR MEMORY 1 0100 1 9B 2 0101 2 33 OCR 1 9B ADD ACCA DIR 0102 2 3 0033 3 vv 3 A + vv Α ACC A 3 0033 Temporary holding register The 1 st mop fetches the opcode. The opcode 9B conveys the following information to the CCU, that: 1. It must do an ADD operation 2. The 1 st operand is ACCA 3. The 2 nd operand is specified by the DIR addressing mode. 21

ADDA DIRECT CYCLES Example: ADDA $33 PC 0100 0101 MAR MEMORY 1 0100 1 9B 2 0101 2 33 OCR 1 9B ADD ACCA DIR 0102 2 3 0033 3 vv 3 A + vv Α ACC A 3 0033 Temporary holding register The 2 nd mop reads the 8-bit address (of the 2 nd operand). The 8-bit address is placed into the low byte of the THR The high byte of the THR is set to zero. Thus, the THR has generated the address of the 2 nd operand. The 3 rd mop reads the 2 nd operand (vv) from memory using the THR as the address. The 2 nd operand is added to the current contents of ACCA. 22

ADDA DIRECT ADDA DIR PC 0100 0101 0102 MAR 1 0100 2 0101 2 MEMORY 1 9B dd 33 OCR 1 9B ADD ACCA DIR 2 3 0033 dd 3 vv 3 A + vv Α ACC A 3 0033 dd Temporary holding register Location Machine Code 0100 9B 0101 dd 0102 Opcode of Next Instruction dd: 8-bit Address of 2 nd Operand dd: Represents 2 Hex Symbols dd: direct direct dd: Any 8-bit direct address 23

TIMING: DIRECT ADDRESSING MODE EXAMPLE: ADDA $33 φ1 φ2 PC 0100 0101 MAR MEMORY 1 0100 1 9B 2 0101 2 33 OCR 1 9B ADD ACCA DIR 0102 2 3 0033 3 vv 3 A + vv Α ACC A 3 0033 Temporary holding register Fetch and execute steps for ADDA direct. Note that vv is an 8-bit variable. Note also that the address of vv is constant since it ($33) is stored in the instruction. 24

ADDA DIR 68HC11 Data Sheet Information (From course web site) ADDA DIR is a general description. It means add memory to ACCA, and store the result in ACCA: A + M A memory refers to the contents of the address of the 2 nd operand. The address of the 2 nd operand is stored in the instruction, as dd: 9B dd Unlike the default address size of 16-bits, the address of the 2 nd operand is specified by 8- bits. The CCU automatically converts the 8-bit address to 16-bits by prepending zeroes: 00dd. The complete instruction is encoded as: 9B dd It takes 3 clock cycles to execute. The NZVC bits in the CCR are updated, as indicated by the delta symbol. 25

DIRect Addressing Mode Limitation Memory Access Limitation Since, the address of the 2 nd operand is specified by 8-bits (dd); And, since the CCU automatically converts the 8- bit address to 16-bits by prepending zeroes, 00dd; The, the DIR addressing mode can access only the 1 st page of memory. 0000 0001 00FE 00FF 0100 0101 01FE 01FF 0200 0201 FEFF FF00 FF01 FFFE FFFF Memory Space 1 st Page 2 nd Page 256 th Page 26

From: Instruction set Manual General Form: ADDA $dd Assembly language Example Absence of # and 8- bit address signifies DIRect addressing mode (DIR). ADDA $33 $ Signifies Hexadecimal number. A A + ($0033) = A + vv Machine code Example 9B 33 Memory Address Data 0033 vv 0100 9B 0101 33 0102 dd 27

Location ADDA DIR & EXT ADDRESS OF 2 nd OPERAND IS A CONSTANT 0100 9B 0101 dd Machine Code 0102 Next Opcode A program is stored in non-volatile memory (e.g., FLASH). In the DIR and EXT addressing modes, the address of the 2 nd operand is stored in the instruction itself. This means that the address of the 2 nd operand cannot be changed once the program is written into ROM (Read Only Memory). Thus, the address of the 2 nd operand is a constant. Location Machine Code 0100 BB 0101 hh 0102 ll 0103 Next Opcode Note: programs are rarely executed in ROM. Typically, a program is copied from a ROM to RAM, and then run in RAM, because RAM memories are much faster than ROM memories. However, our assertion that instructions cannot be changed (and so the 2 nd operand address cannot be changed) still holds. 28

COMPARISON: ADDA DIR & EXT NUMBER OF STORAGE BYTES AND CLOCK CYCLES Location 0100 9B 0101 dd Machine Code 0102 Next Opcode ADDA DIR ADDA EXT Accumulator DIR instructions require 2 bytes to store 3 cycles to execute Can access only the 1 st page of the memory space. Location Machine Code 0100 BB 0101 hh 0102 ll 0103 Next Opcode Accumulator EXT instructions require 3 bytes to store 4 cycles to execute Can access the entire memory space. 29

PROCESSING LISTS OR ARRAYS The DIR and EXT addressing modes cannot be used when we require to change the address of variables. This is because the address of the variable is stored inside the instruction, and the instruction cannot be changed. For example, to process a list of numbers, stored in memory in sequential order, the address of the numbers needs to be incremented. In this case, we can use the INDexed addressing mode. This addressing mode permits changing the effective address of the 2 nd operand. 30

Indexed Addressing Mode General Form, Accumulator A Indexed X Addressing Mode: ADDA $ff,x ADDA $ff,x EA is formed by: X + 00ff $ Signifies offset is specified by a Hexadecimal number ff is the 8-bit unsigned offset $ff,x signifies INDexed addressing mode (IND). X Signifies using the Indexed X addressing mode (other is Y). The address of the 2 nd operand is also called the effective address. The effective address is computed (generated) by: Value of the index register X + the unsigned 16-bit extension of the offset. For example, if X=1000, (1080) =, then, the ADDA $80,X instruction: Effective Address 31

Indexed Addressing Mode Effective Address is a Variable The address of the 2 nd operand is a variable, since the value of index register X can be changed, through several different instructions. Examples of instructions that change the value of index register X: LDX #$BEEF //Load the number $BEEF into X. INX //Increment X by one. DEX //Decrement X by one. The ADDA $80,X instruction: Effective Address Note that the offset cannot be changed, since it is part of the instruction. 32

CYCLES of ADDA IND,X Example: ADDA $80,X PC 0100 0101 0102 MAR 1 0100 MEMORY 1 AB 2 0101 2 80 2 0180 4.. vv 4 Offset OCR 1 AB THR 0080 A + vv Α ACC A ADD ACCA INDEXED Location Machine Code 0100 AB 0101 80 0102 Next Opcode Index Register X 0100 + 3 Effective Address (EA) 0180 THR For the above assume X=$0100, currently. The animation software shows how the effective address may be computed in the hardware. When explaining the timing, instead of using a specific example offset (i.e., $80) as in the above, we typically replace the number with a symbol, which in this case we use the symbol to denote the offset. 33

PC 0100 0101 0102 MAR 1 0100 1 AB 2 0101 2 80 2 EFAD 0180 4.. Index Register X ADDA IND,X ADDA $ff,x MEMORY ff vv 4 Offset 0100 OCR 1 AB THR 0080 ff + 3 A + vv Α ACC A ADD ACCA INDEXED Effective Address (EA) EFAD 0180 THR Location Machine Code 0100 AB 0101 ff 0102 Next Opcode I am not specifying the contents of X, nor I am specifying the actual offset. ff: Symbol for 8-bit unsigned offset ff: Represents 2 Hex symbols ff: offset offset 00ff: 16-bit Unsigned Extension of ff EFAD: 16-bit Sum of THR + IX EFAD: Effective Address Note: EFAD means EFfective ADdress 34

TIMING: INDEXED ADDRESSING MODE EXAMPLE: ADDA $ff,x φ1 φ2 PC 0100 0101 0102 MAR 1 0100 MEMORY 1 AB ff 2 0101 2 80 2 EFAD 0180 4.. OCR 1 AB ADD ACCA INDEXED vv 4 Offset THR 0080 ff A + vv Α ACC A Index Register X 0100 + 3 Effective Address (EA) EFAD 0180 THR 35

ADDA IND 68HC11 Data Sheet Information (From course web site) ADDA IND is a general description. It means add memory to ACCA, and store result in ACCA: A+M A memory refers to the contents of the effective address of the 2 nd operand. The effective address of the 2 nd operand is formed by adding the unsigned extension of the offset to the current value of the index register. AB ff The offset is specified by 8-bits: it is interpreted as unsigned. The complete instruction is encoded as: AB ff It takes 4 clock cycles to execute. The NZVC bits in the CCR are updated accordingly, as indicated by the delta symbol. 36

From: Instruction set Manual General Form: ADDA $ff,x Assembly language Example $ff,x signifies INDex X addressing mode (IND X). ADDA $01,X $ Signifies offset represented as Hexadecimal number. A A + ($1001) = A + vv Machine code Offset Example AB 01 Index register X. Assume X = 1000 currently. Memory Address Data 00FF 0100 AB 0101 01 0102 1001 vv ff 37

NON-MEMORY ACCESS INSTRUCTIONS Sometimes, it is required to make a register zero, increment a register, decrement a register, complement a register, negate a register, or transfer one register to another. In these cases, there are special instructions to do just that. For example: to make ACCA=0, we can use: CLRA These types of instructions use the Inherent (or Implied) addressing mode. The name Inherent or Implied was chosen because the 2 nd operand is implied by the opcode, and the 2 nd operand does not need to be specified in the instruction. 38

INHERENT ADDRESSING MODE Example: CLRA INH (CLRA) PC 0100 0101 MAR 1 0100 MEMORY 1 4F OCR 1 4F CLEAR ACCA 00 2 $00 Α ACC A CLRA No Specification of operand means this instruction uses the INHerent addressing mode (INH) A 0 Location Machine Code 0100 4F 0101 Next Opcode 39

INH Mode Example: CLRA Manual Assembly CLRA No Specification of operand implies INHerent addressing mode (INH) Memory Address Data 00FF 0100 4F 0101 A 0 40

TIMING: INHERENT ADDRESSING MODE EXAMPLE: CLRA φ1 φ2 PC MAR MEMORY OCR 0100 1 0100 1 4F 1 4F LOAD ACCA 0 0101 2 00 A ACCA 41

CLRA INH 68HC11 μp Peculiarities Clearly, setting N=0 and Z=1 makes a lot of sense. But, why is the V set to zero? Moreover, why is the C set to zero? The CLRA instruction does not seem to be an arithmetic instruction. It is more like a load instruction: LDAA #$00. Sometimes, the reason for doing this is a Manufacturer s design choice. Another possible reason could be that when you clear A, you are clearing an accumulator, and so, it is like resetting the accumulation of arithmetic results; so, maybe we should reset the C and V bits as well. 42

EXAMPLES USES OF ADDRESSING MODES Now, let s look at some examples. 43

ACCUMULATOR LOAD INSTRUCTIONS INSTRUCTION COMMENT RTL LDAA #$94 This loads the number $94 into ACCA. ACCA $94 LDAA $94 This loads the data located at $0094 into ACCA. ACCA ($0094) = $13 LDAA $0094 This loads ACCA with the data located at $0094. ACCA ($0094) = $13 LDAA $01,X This loads ACCA with the data located at ($0001 + X). Assuming X = 03FF, then, this loads the data located at 0400 into ACCA. ACCA (0001+X). ACCA (03FF+0001). ACCA 01. ADDRESS CONTENTS 0093 AB 0094 13 0095 EF ADDRESS CONTENTS 0400 01 0401 02 0402 FE 44

LOAD INSTRUCTIONS QUESTIONS 1. Write down two different instructions that load accumulator B with the contents of memory location $1234. You may assume a value for X. 2. Write down three different instructions that load accumulator B with the data located at $0034. You may assume a value for X. 3. Write down four different instructions that load the number 34 into Accumulator B. You may assume a value for X and make assumptions regarding contents of memory. 4. Describe the main purpose of each one of the micro-instructions for each instruction listed above. 5. Examine each micro-instruction for each instruction above. Are there any duplicate micro-instructions? If so, what are they? 45

DUPLICATE MOPS OF LDAA IMM, DIR, EXT, IND MOP LDAA IMM LDAA DIR LDAA EXT LDAA IND 1 (PC) OCR (PC) OCR (PC) OCR (PC) OCR 2 (PC) A (PC) THR LB, 00 THR HB (PC) THR HB (PC) THR LB, 00 THR HB 3 (THR) A (PC) THR LB X+ THR THR 4 (THR) A (THR) A 46

STORE INSTRUCTION QUESTIONS 6. Write down two instructions, each of which stores the data in accumulator A to location $1234. You may assume a value for X. 7. Write down three different instructions, each of which stores the data in accumulator A to location $0012. You may assume a value for X. 8. Describe the main purpose of each one of the microinstructions for each instruction listed above. 9. Examine each micro-instruction for each instruction above. Are there any duplicate micro-instructions? If so, what are they? 47

ARITHMETIC AND LOGIC INSTRUCTION QUESTIONS 10.Write down an instruction that ADDs the data located at $0101 to Accumulator A. 11.Write down an instruction that ANDs the data located at $0101 to Accumulator A. 12.Describe the main purpose of each one of the microinstructions for each instruction listed above. 13.Examine each micro-instruction for each instruction above. Are there any duplicate micro-instructions? If so, what are they? How many micro-instructions are different? Which micro-instruction(s) is(are) different? 48

ADDRESSING MODE QUESTIONS 15.Identify all information in the following: XXXX #12 XXXX $12 XXXX $1234 XXXX $01,X XXX #1234 XXX #$1234 XXX $1234 XXX $00,X 49

Example: Writing a Simple Assembly Language Program Problem: count the number of occurrences of $42 in data memory from address $1000 to $2000, inclusive. Solution: Use ACCB to count the number. Use X as an memory address pointer clrb ldx #$1000 loop ldaa $0,X cmpa #$42 bne skip incb skip inx cpx #$2001 bne loop done bra done ACCA Address 1000 1001 1FFF 2000 2001 Memory Data 7F 01 34 42 00 42 50

14.Write down a sequence of instructions that store the multiple byte word $0123456789ABCDEF starting at location $0A00. Using the BIG ENDIAN format Using the LITTLE ENDIAN format 51