ARM Programmers Model Hi Hsiao-Lung Chan, Ph.D. Dept Electrical Engineering Chang Gung University, Taiwan chanhl@maili.cgu.edu.twcgu
Current program status register (CPSR) Prog Model 2
Data processing instruction format 31 28 27 26 25 24 21 20 19 16 15 12 11 0 Cond 00 L OpCode S Rn Rd Shifter_operand <OpCode>{<Cond>}{S} Rd, Rn, <Shifter_Operand> Cond: If the condition does not satisfied (N,C,Z,C), C) the instruction acts as a NOP. Always condition is specified if it is omitted. S: Specify CPSR is updated after the execution of instruction. CPSR is unchanged if S is omitted Rd, Rn: Destination register, and 1 st operand register Shifter_operand: Immediate value (L=1), or register (L=0) Prog Model 3
Move instructions MOV{<Cond>} Rd, <Shifter operand> MOV : move 32-bit value into a register MVN : move the NOT of the 32-bit register value (1 s complement) into a register <Pre-condition> r5 = 8 MOV r6, r5 MVN r7, r5 <Post-condition> r6 = r5 = 0x00000008 r7 = 0xffffffff r5 = 0xfffffff7 Prog Model 4
ADD instructions ADDS r4, r0, r2 ;r4= r0 + r2 ADC r5, r1, r3 ; r5 = r1 + r3 + carry R1 C R0 R3 R2 (+ R5 R4 64-bit Addition Prog Model 5
SUB instructions <Pre-condition> o CPSR = nzcvqift_user r1 = 0x00000001 SUBS r1, r1, #1 <Post-condition> CPSR = nzcvqift_user r1 = 0x00000000 #1 0x00000001 0xfffffffe +1 0xffffffff 1 s complement 2 s complement 64-bit subtraction SUBS r4, r0, r2 SBC r5, r1, r3 ; R5:R4 = R1:R0 R3:R2 Prog Model 6
RSB instruction <Pre-condition> r0 = 0x00000000 r1 = 0x00000077 RSB r0, r1, #0 <Post-condition> r0 = 0 - r1 = 0xffffff89 Prog Model 7
Thumb instruction Solutions to code-size problem Hand code in assembler Improve the compiler Use compressed code (require additional system sources) ARM Thumb is a recoded subset of ARM instruction Implements 16-bit instruction on 32-bit architecture Keep 32-bit performance and address space A 30% code density improvement Prog Model 8
ARM-Thumb interworking Fetch Decode stage Execute stage 32-bit data 16 16 A[1] 16 Thumb instruction decomposition ARM instruction decode Thumb state Decompress Thumb instruction during the used phase of the clock in decode stage Prog Model 9
Registers in ARM and Thumb states Thumb state R0-R7 ARM state R0-R7 R8-R12 Low register High register Stack pointer (SP) Stack pointer (R13) Link register (LR) Link register (R14) Program counter (PC) Program counter (R15) Current program Current program status register (CPSR) status register (CPSR) Saved PSR (SPSR) Saved PSR (SPSR) Prog Model 10
Thumb instruction decoding Thumb 16-bit instruction ARM 32-bit instruction ADD rd, #Constant Decoder ADDS rd, rd, #Constant CPSR = nzcvqift_svc Prog Model 11
Thumb instruction format Example: ADD Rd, #Constant 15 3 bits 0 Thumb Code 0 0 1 1 0 Rd 8-bit immediate Major op-code Minor op-code Destination & Source register Immediate value ARM Code 31 0 1110 00 1 0100 1 0 Rd 0 Rd 0000 8-bit immediate Always condition code S Prog Model 12
Branch instructions Prog Model 13
Condition code Prog Model 14
Pipeline stall due to branch instruction (control stall) BNE foo fetch decode ex bne SUB r2, r3, r6 fetch decode foo ADD r0, r1, r2 fetch decode ex add time Prog Model 15
Conditional execution Greatest common divisor while (a!=b) if (a>b) a -=b; else b -=a; Using branch gcd CMP r1, r2 BEQ complete BLT lessthan SUB r1, r1, r2 B gcd lessthan SUB r2, r2, r1 B gcd complete Using conditional execution gcd CMP r1, r2 SUBGT r1, r1, r2 SUBLT r2, r2, r1 BNE gcd Prog Model 16
Branch with link (subroutine call) BL fn1 ; branch to subroutine fn1, and next instruction ; address is copied to lr CMP r1, #8 ; compare with 8 MOVEQ r1, #2 ; if r1==8 then r1=2 fn1 <subroutine code> MOV pc, lr ; at the end of subroutine, return by moving pc = lr Prog Model 17
ARM vs. Thumb codes Prog Model 18
ARM code of binary to hexadecimal converter MOV r1,r0 ; r0 holds value to convert, r1=r0 MOV r2,#8 ; Load r2 with decimal 8 Loop: MOV r1,r1,ror #28 ; Rotate r1 right by 28 and put result in r1 AND r0,r1,#15 ; AND r1 with decimal 15 CMP r0,#10 ;Compare r0 with decimal 10 and ADDLTr0r0#'0' r0,r0,#0 ;ifit s it less than 10 then ADD ASCII 0 to r0 ADDGE r0,r0,#'a' ; otherwise ADD ASCII A to r0 SWI 0 ; routine to write char to screen SUBS r2,r2,#1 ; Subtract 1 from r2 BGT Loop ;and loop back to 1 if r2 is still greater than zero MOV pc,lr ;Load PC with Link reg (Return) Prog Model 19
Thumb code of binary to hexadecimal converter MOV r1,r0 ;Value to convert in r0, r1=r0 MOV r2,#8 ;Put 8 in r2 Loop1 LSR r0,r1,#28 ;Do logical shift right on r1 by 28 places and ; place in r0 LSL r1,r1,#4 ;Do logical shift left on r1 by 4 places CMP r0,#10 ;Compare r0 with 10 and BLT Loop2 ;if less than 10, branch to Loop2 ADD r0,# A - 0-10 ;ADD ASCII A-0-10 (7) to r0 Loop2 ADD r0,#'0' ;ADD ASCII 0 (48) to r0 SWI 0 ;routine to write char to screen SUBr2#1 r2,#1 ;subtract1fromr2 r2 BNE Loop1 ;if unfinished loop1 MOV pc,lr ;else,load PC with Link register Prog Model 20
Code size comparison ARM code 11 instructions 44 bytes Thumb code 12 instructions 24 bytes Prog Model 21
ARM-Thumb interworking instructions BX Rm Thumb version branch exchange pc = Rm & 0xfffffffe, T = Rm[0] BLX Rm Thumb version branch exchange with link pc = Rm & 0xfffffffe, T = Rm[0] lr = address of next instruction after BLX+1 Prog Model 22
ARM-Thumb interworking example ; ARM code CODE32 ; word aligned address(thumbcode)= 0x00009000 LDR r0, =thumbcode+1 r0 = 0x00009001 BLX r0 ; branch to Thumb code & mode... ; Thumb code CODE16 ; halfword aligned thumbcode ADD r1, #1 BX lr ; branch to ARM code & mode Prog Model 23
Thumb-2 instruction set Add 32-bit instructions (cover the functionality of the ARM instruction set) that can be freely intermixed with 16-bit instructions in a program. DSP algorithms using the 32-bit media instructions in Thumb-2 and use the smaller 16-bit Thumb instructions for the rest of the application. Does not require any mode change. The first halfword (hw1) determines the instruction length and functionality Prog Model 24
Thumb-2 instruction set (cont.) Most 32-bit Thumb instructions are unconditional, whereas most ARM instructions can be conditional. Thumb-2 introduces a conditional execution instruction, IT (if-then-else) that can make following instructions conditional. Prog Model 25
Load-store instructions Prog Model 26
Indexing methods Prog Model 27
Checksum example Programming 28
Argument passing in function call Prog Model 29
Thumb Execution Environment (Thumb-EE) instruction set Executed in the ThumbEE state (J=1 &T=1) In ThumbEE state, the processor executes almost the same instruction set as in Thumb state. However some are different, some are removed, and some ThumbEE instructions are added, such as New ThumbEE instructions to branch to handlers Null pointer checking on load/store instructions Additional instruction ti to check array bounds Some other modifications to load, store, and control flow instructions. Prog Model 30
Registers and operation modes Prog Model 31
Operation modes of ARM User mode ARM program execution state t System mode Privileged user mode for the OS Supervised (svc) mode Executing a SVC (supervisor call) instruction A processor enters supervisor mode on reset Fast interrupt mode handling fast interrupts Interrupt mode General-purpose interrupt handling Abort mode Data abort exception or instruction prefetch abort Undefined mode Attempt to execute an UNDEFINED instruction Secure monitor mode Executing a SMC (secure monitor call) instruction Prog Model 32
Reference A.N. Sloss, D. Symes, C. Wright, ARM System Developer s Guide, Elsevier Inc., 2004. Cortex -A8 Technical Reference Manual, ARM Limited. ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition, ARM Limited. Prog Model 33