Interrupt/Timer/DMA 1

Exception An exception is any condition that needs to halt normal execution of the instructions Examples - Reset - HWI - SWI 2

Interrupt Hardware interrupt Software interrupt Trap 3

Hardware devices sources of interrupts Hardware sources can be internal or external of ongoing routine and thereby diversion to corresponding ISR The internal sources from devices differ in different process or microcontroller or devices and their version and their families External sources and ports also differ in different processors or microcontrollers 4

Interrupt sources Each of the interrupt sources demands a temporary transfer of control from the presently executed routine to the ISR corresponding to the source 5

Internal Hardware Device Sources Parallel port UART port (receive and transmit) ADC (start and end conversion) Real-time clock time-outs Watch dog timer reset Pulse Accumulator overflow 6

Keyboard interrupt Take about 10ms to send the code for a key and maximum 10 keys per second Interval between two successive keys are not fixed Interrupt driven mode, when a key is pressed 7

Example of keyboard interrupt 8

Printer Interrupt Maximum 300 characters can be printed in 1 second When does a print operation completes is not fixed Intervals between two successive print are not fixed Interrupt driven mode when a print action is completed 9

Example of printer interrupt 10

Interrupt type Maskable interrupt To execute timing critical interrupt Non-maskable interrupt 11

Interrupt driven data transfer 12

Flow chart for interrupt service 13

Interrupt in a typical microcontroller 14

Example of Interrupt table 15

Bus arbitration To service more than one device Priority arbiter Daisy chain arbiter 16

Priority arbiter 1. The processor is executing its program 2. Peripheral1 needs servicing so asserts Ireq1. Peripheral2 also needs servicing so assert Ireq2. 3. Priority arbiter sees at least one Ireq input asserted, so asserted Int. 4. Processor stops executing its program and stores its state. 5. Processor asserts Inta 6. Priority arbiter asserts Iack1 to acknowledge Perpheral1 7. Peripheral1 puts its interrupt address vector on the system bus 8. Processor jumps to the address of ISR read from data bus, ISR executes, and return 17

Priority arbiter 18

Daisy chain arbiter 1. The processor is executing its program 2. Any Peripheral needs servicing asserts Req out goes to the Req in of the subsequent device in the chain 3. Thus, the peripheral nearest to the processor asserts Int 4. The processor stops executing its program and stores its state 5. Processor asserts Inta the nearest device 6. The Inta passes through the chain till it finds a flag which is set by the device which has generated the interrupt. 7. The interrupting device sends the Interrupt Address Vector to the processor for its interrupt service routine 8. The processor jumps to the address of ISR read from data bus, ISR executes and returns. 9. The flag is reset 19

Daisy chain arbiter 20

Sources of Software Interrupt Software sources of interrupt are related to software detecting computation error or exceptional condition during execution or execute a software interrupt instruction (SWI) 21

Software interrupt Example Division by Zero by hardware Over-flow detection by hardware Under-flow detection by hardware Illegal opcode detection by hardware Software Interrupt instruction 22

Trap Special case of Software Interrupt Used for trapping some run-time error conditions (called throwing exceptions) and execute exception handlers on catching the exceptions Also used in debugger 23

Question? An Embedded System has three periodic devices Service time: how long it takes to run interrupt handler for each device Interrupt latency: maxim elapse time between an interrupt request and the start of interrupt handler routine If program P takes 100 seconds with interrupt disabled,how long will it takes with interrupt enabled, assuming no interrupt overlapped? 24

Solution Device 1 shall take (150+50)/800 = 0.25 Device 2 shall take (50+50)/1000 = 0.10 Device 3 shall take (100+100)/800 = 0.25 In one unit real time, it will take 0.6 unit time to service interrupt For a program with 100 seconds, it will take 250 seconds to finish the entire program with interrupt enabled 25

ARM Interrupt ARM has 7 modes of operation Switching between modes can be done by modifying CPSR register Most applications execute in user mode Non-user modes are entered to serve interrupts or exceptions 26

Modes of operation 27

Exceptions and modes Each exception causes ARM to enter to different modes 28

Vector Tables It is a table address of ARM core branches to when exception is raised and there is always branching instructions that direct the core to ISR 29

Exception Priority Newer ARM, Primask,Faultmask, and Basepri are used instead 30

Link Register Used to return the PC to the appropriate place in the interrupt task since this is not always the old PC value. It is modified depending on the type of execution. 31

Exception Handler Entering exception handler 1) Save the address of the next instruction in the appropriate LR 2) Save CPSR 3) Modify CPSR for the new mode 4) Fetch next instruction from the vector table Leaving exception handler 1) Return CPSR before calling the handler 2) Clear the interrupt disable flag (if set) 3) Move LR to the PC 32

Interrupts Assigning interrupts It is up to the system designer who can decide which HW peripheral can produce with interrupt Standard design: SWI are used to called privilege OS routines IRQ are designed to call general purpose interrupts FIQ is reserved for one single interrupt source that require fast response time 33

Interrupt latency It is the interval of time from an internal interrupt signal being raised to the first fetch of an instruction of ISR of the raised interrupt signal System architect tries to achieve two main goals: To handle multiple interrupt simultaneously To minimize the interrupt latency It can be done by 2 methods Allow nested interrupt handling Give priorities to different interrupt sources 34

Enable/Disable Interrupt This can be done by modifying CPSR using 4 ARM instructions: MRS to read CPSR MRS to store CPSR BIC Bit clear instruction ORR Or instruction 35

Interrupt Stack Stacks are needed extensively for context switching between different modes when interrupt are raised The design of stack depends on OS requirements Target hardware 36

Interrupt stack Two design decision are needed to be made Location Size 37

Non-nested Interrupt Handle Simple interrupt Handler Interrupt is disabled until the control is returned back to the interrupted task One interrupted can be served at a time Not suited for complex embedded system Scheme 38

Interrupt latency Device 1 : interrupt latency 50 s, ISR time 150 s Device 2 : interrupt latency 50 s, ISR time 50 s Device 3 : interrupt latency 100 s, ISR time 200 s What s the average interrupt latency if all interrupt happens at the same time? 39

Nested Interrupt Handler Handling more than one interrupt at a time Latency is improved System is more complex Normal interrupt can block critical interrupt 40

Nested Interrupt Handler Scheme Handler tests the flag that is updated by ISR Re-enabling interrupt requires switching out of current interrupt mode to either SVC or system mode Context switching involving emptying IRQ stack into reserved block 41

Prioritize Interrupt Handler Associate a priority level with a particular interrupt source Handling prioritization can be done either by software or hardware When an interrupt is raised, a fixed amount of comparison is done 43

Other Schemes Re-entrant interrupt handler: re-enable interrupts earlier Priority standard interrupt handler: arranges priorities in a special way to decide which interrupt get higher priorities Prioritized group interrupt handler: group some interrupts into subset 45

Advantages/Drawback Non-Nested Interrupt handler Easy to implement and debug High interrupt latency Sequential service Not suitable for complex system Nested Interrupt handler Handle multiple interrupts No prioritization Medium interrupt latency Prioritize Interrupt handler Low latency Handle multiple interrupts Deterministic interrupt latency More complex Need time for priority comparison 46

Timer Timer is a device, which count the input at a regular interval T using clock pulse at its input The counts increment on each pulse and store in a register called count register 47

Evaluation of the time The count multiplies with the interval T gives the time The (present counts initial count ) * T gives the time interval between initial time and current time 48

Timer Has an input pin or a control bit in a control register for resetting the count bits Has an output pin or a status bit in a control register for the output value 49

Counter A device, which count the input due to the events at regular or irregular intervals The counts give the number of input events or pulses since it was last read. Has a register to enable read of present counts Functions as timer when counting regular interval clock pulses 50

Timer or Counter Interrupt When a timer or counter becomes 0x00 or 0x0000 after 0xFF or 0xFFFF(Maximum value), it can generate an Interrupt or output Time-Out signal or setting a status bit Timer Overflow (TOV) 51

Basic Hardware Timer 52

More complex timer 53

Timer with a terminal count 54

The timer count and its output 55

Block diagram of an Embedded System 56

Hardware Timer 57

Real-time clock Real-time clock ticks (System Heart Beats) Real-time clock is a clock which once the system starts, does not stop and can t be reset and its count value can t be reloaded Real-time clock is set for ticks using prescale bit in control register to control tick rate 58

Usage of a timer device To issue some service routing every some pre-set counter interval Count some special events within some timing interval Finding the time interval between two events Waiting for synchronization for other tasks such as from mutex, message queue 59

Usage of timer device Watchdog timer Bit-rate control for data communication Input-pulse counting for non-periodic inputs Context switch for multi-tasking OS Schedule tasks for RTOS Time division multiplexing (TDM) 60

Timer state 61

Timer state 62

Software Timer A software which executes and increases or decreases a count-variable on an interrupt from a system timer or from a real-time clock interrupt The software timer also generates interrupt on overflow of count-value or on finishing value of the count-variable 63

System clock An hardware-timing device is programmed to tick at constant intervals At each tick, there is an interrupt The interrupts are called system clock interrupts, when use to control the schedule and timings of the system 64

Software Timer (SWT) 65

SWT Actions are analogous to that of a hardware timer. While there is a physical limit of hardware timer, SWTs can be limited by the number of entry in the interrupt vector 66

Watchdog timer A timing device such that after preset time interval is set, an event must occur during the interval else the device will generate the timeout signal on failure If the event occurs, the watchdog timer is disabled Timeout may result in a service routine call, or even a processor reset 67

Example Assume that we anticipate that a set of tasks must finish in 100ms interval If the program finishes before 100ms, the watchdog timer is disabled and stopped If the program does not finish within 100ms, watchdog timers will generate an interrupt to reset the system 68

Watchdog timer application An application in mobile is that display is off in case that there is no user interaction takes place within watched time interval (e.g, 20 second) This can help save power of the mobile phone 69

Watchdog timer application An application in temperature control system: if the controller takes no action to switch off the boiler within preset watched time interval, a service routine is called to switch off the boiler Failure to switch off, may burst a boiler in which water is heated 70

Provision of watchdog timer A software interrupt can be programmed as a watchdog timer Microcontroller may provide hardware support for a watchdog timer 71

ARM SYSTICK Timer TICKINT to generate interrupt CLKSOURCE external or core clock COUNTFLAG timer history (1 means overflow) Reload value when timer reaches zero TENMS Calibration value for 10ms NoREF No external reference clock 72

Direct Memory Access (DMA) A DMA is required when multi-data set or burst of data or a block is to be transferred between the external device and system or two systems A device facilitates DMA transfer with a processor element and that device is called DMAC (DMA Controller) 73

Using a DMA controller DMA based method is useful when a block of bytes are transferred. E.g, disk to RAM or RAM to disk System performance improves by separate the processing of the transfer to the peripherals 74

An example of DMA architecture 75

DMA controller architecture 76

DMAC hold request After an ISR from CPU initializes and programs DMAC, the DMAC sends the hold request to the CPU CPU acknowledges and gives the control of the bus to DMAC 77

Three modes of data transfer Single transfer at a time and then release the control of the system bus Burst transfer at a time and then release the control of the system bus, a burst can be a few kb Bulk transfer and the release the control of the system bus after the transfer is complete 78

CPU and DMAC interaction At the start for DMAC programming and initializing At the end to return control back to CPU ISRs of the CPU is called only at the beginning and at the end of DMA transfer 79

Programming the DMAC registers The ISR from CPU will program the DMA registers for : Transfer command Data count Memory block address I/O bus address 80

Multiple channels DMAC Provides DMA action from system with two I/O devices or more Separate set of registers for programming each channels Separate interrupt signals in the case of multi-channel DMAC 81

Question? 82

Fly-by DMA transfer Single cycle, single address transfer Efficient data transfer First a device or CPU issues DMA request DMAC gains control of the bus from CPU DMAC sends acknowledge back to the device 83

Fly-by DMA transfer 84

Fetch-and-Deposit transfer Dual-cycle, dual address, flow-through Involves two memories or I/O cycles Data first transfer from I/O into a temporary register inside DMAC The data is written to memory or I/O in the next cycle Inefficient, but useful for interfacing devices with different bus sizes, e.g., read two 16 bits read and write one 32-bit data 85

Fetch-and-deposit DMA transfer 86