MICROPROCESSOR TECHNOLOGY Assis. Prof. Hossam El-Din Moustafa Lecture 12 Ch.5 8086/8088 Hardware Specifications 22-Mar-15 1
The Buffered System If more than 10 unit loads are attached to any bus pin, the entire system must be buffered. The Fully Buffered 8088: Requires two 74LS373, two 74LS244, and one 74LS245 See Fig. (5-7) page 113 The Fully Buffered 8086: Requires three 74LS373, one 74LS244, and two 74LS245 See Fig. (5.8) page 114 22-Mar-15 2
M / IO Basic Bus Operation If data are written to the memory, the microprocessor performs the following operations: 1. Outputs the memory address on the address bus 2. Outputs the data to be written into memory to the data bus 3. Issues a write WR to memory 4. IO/M=0 for the 8088 and M/IO=1 for 8086 22-Mar-15 3
Basic Bus Operation If data are read from memory, the microprocessor performs the following operations: 1. Outputs the memory address on the address bus 2. Issues a read RD memory signal 3. Accepts the data via the data bus 22-Mar-15 4
Timing in General The 8086/8088 use memory and I/O in periods called bus cycles. Each bus cycle equals four system clocking periods. If the clock is operated at 5MHz, one 8086/8088 bus cycle is complete in 800 ns. This rate corresponds to 1.25*10 6 reads/writes per second. 22-Mar-15 5
Timing in General During T1, the address of memory or I/O location is sent out via the address bus and the address/data bus connections, signals ALE, DT/R, and IO/M or M/IO, are also output. During T2, the 8086/8088 issues the RD or WR signal, DEN, and in the write case, the data to be written appear on the data bus. READY is sampled at the end of T2 22-Mar-15 6
Timing in General If READY=low at this time, T3 becomes a wait state. This period is provided to allow the memory time to access data In T4, all bus signals are deactivated in preparation for the next bus cycle. At this point, the trailing edge of the WR signal transfers data to the memory or I/O which activates and writes when the WR signal returns to logic 1 level. 22-Mar-15 7
READY and The Wait State The READY input causes wait states for slower memory and I/O components. A wait state T w is an extra clock period inserted between T2 and T3 to lengthen the bus cycle. The READY input is sampled at the end of T2 If READY=0 at the end of T2, T3 is delayed and T w is inserted between T2 and T3 READY is next sampled at the middle of T w to determine whether the next state is T w or T3. 22-Mar-15 8
READY and The Wait State It is tested for a logic 0 on the 1 to 0 transition of the clock at the end of T2, and for a logic 1 on the 0 to 1 transition of the clock in the middle of T w See Fig. 5-14 page 120 The timing requirements are met by the internal READY synchronization circuitry of the 8284A clock generator. The RDY input occurs at the end of each T state See Fig. 5-15 page 120 22-Mar-15 9
Minimum Mode Vs. Maximum Mode Minimum mode is obtained by connecting the mode selection pin MN/MX to 5V Maximum mode is obtained by grounding the mode selection pin. The minimum mode is similar to the 8085A, the most recent Intel 8-bit microprocessor. The maximum mode is designed to be used whenever a coprocessor exists in the system. Note: The maximum mode was dropped beginning with the 80286 family. 22-Mar-15 10
Minimum Mode Operation Minimum mode operation is the least expensive way to operate the 8086/8088 All control signals for the memory and I/O are generated by the microprocessor. Control signals are like the 8-bit Intel 8085A. The minimum mode allows the 8085A peripherals to be used with the 8086/8088 without any special considerations. 22-Mar-15 11
Maximum Mode Operation In Maximum-mode operation, some control signals must be externally generated. This requires the addition of an external bus controller (The 8288 bus controller) Maximum mode is used only when the system contains external coprocessor such as the 8087 arithmetic coprocessor (Why?) 22-Mar-15 12
The 8288 Bus Controller It contains separate signals for I/O (IORC and IOWC) and memory (MRDC and MWTC) It advanced I/O contains advanced memory (AMWC) and (AIOWC) write strobes and the INTA signal. These signals replace the minimum mode ALE, WR, IO/M, DT/R, DEN, INTA which are lost when the microprocessor is operated in the maximum mode. See Fig. (5.21) page 124 22-Mar-15 13
The 8288 Bus Controller (Pin Functions) S0, S1, S2 Status inputs are connected to the status output pins of the 8086/8088 processors. These signals are decoded to generate the timing signals for the system. CLK provides internal timing and must be connected to the CLK output pin of the 8284A ALE Address Latch Enable is used to demultiplex the address/data bus. DEN (active high) Data Bus Enable controls the bidirectional data bus buffers in the system. 22-Mar-15 14
The 8288 Bus Controller (Pin Functions) DT/R The Data Transmit/Receive signal is output by the 8288 to control the direction of the bidirectional data bus buffers. AEN The Address Enable input causes the 8288 to enable the memory control signals. CEN The Control Enable input enables the command output pins on the 8288 IOB The I/O Bus mode input selects either the I/O bus mode or system bus mode operation. 22-Mar-15 15
The 8288 Bus Controller (Pin Functions) AIOWC The Advanced I/O Write is a command output used to provide I/O with an advanced I/O write control signal. IOWC The I/O Write command output provides I/O with its main write control signal. IORC The I/O Read command output provides I/O with its read control signal. AMWC The Advanced Memory Write control pin provides memory with an advanced write control signal. 22-Mar-15 16
The 8288 Bus Controller (Pin Functions) MWTC The Memory Write control pin provides memory with its normal write control signal. MRDC The Memory read control pin provides memory with its normal read control signal. INTA The Interrupt acknowledge output acknowledges an interrupt request input applied to the INTR pin. MCE/PDEN The Master Cascade/Peripheral Data output selects cascade operation for interrupt controller if IOB=0 and enables the I/O bus transceivers if IOB=1 22-Mar-15 17
Thank You With all best wishes!! 22-Mar-15 18