4.1 Introduction Chapter 4 Combinational Logic Logic circuit for digital systems may be broadly classified as combinational or sequential. Combinational logic circuits are made by logic gates whose output at any time is determined from the present combinations of inputs. Combinational logic circuits are designed without feedback or memory elements. Figure 4.1 In this chapter we are going to design some basic combinational logic circuits. The foundations for the design of combinational circuits are provided in the preceding chapters. In chapter 1, we have discussed about number systems and different codes used in the digital systems. Chapter 2 defines the Boolean algebra (switching algebra) and how to obtain truth table for a Boolean function. Also we have learned to draw the circuit using Boolean functions. In chapter 3, the simplifications of Boolean functions were illustrated. As we are going to deal with maximum of 4 or 5 variable inputs, K-map is used to simplify the Boolean function. We will use these tools to design combinational logic circuit in this chapter. At the end of this chapter, we will be able to design half adder, full adder, binary adder and BCD adder circuits. designsubtarctor, multiplier circuits. convert one digital code to other code. 4.2 Analysis Procedure Analyzing a circuit means identifying the function of the circuit. Given a circuit in our hand, after analyzing the circuit we have to define the function of the circuit. The procedure to analyze the circuit may be given as follows. Find corresponding logic expression from the given circuit. Create truth table by applying all possible input combinations. From the truth table canonical form of Boolean function can be obtained.
Using the truth table and Boolean functions, we can determine the function of the circuit. Example: Analyze the following circuit and find the function of the circuit. Figure 4.2 Let us redraw the circuit by labeling each and every gate output.
Figure 4.3 After labeling every logic gate output, write Boolean function for every label. T1 = ABC F1 = T1+T7 T2 = A+B+C F1 = ABC+(A+B+C)(AB+BC+AC) T3 = AB F2 = T3+T4+T5 T4 = AC F2 = AB+BC+AC T5 = BC T6 = F2 T7 = T2.T6 T7 = (A+B+C)(F2 ) T7 = (A+B+C)(AB+BC+AC) Using Boolean laws and theorems, simplify the F1. F1 = ABC+(A+B+C)(AB+BC+AC) = ABC+(A+B+C)(AB) (BC) (AC) using DeMorgan s theorem = ABC+(A+B+C)(A +B )(B +C )(A +C ) using DeMorgan s theorem again = ABC+(AA +AB +A B+BB +A C+B C)(A B +B C +A C +C C )
= ABC+(0+AB +A B+0+A C+B C)(A B +B C +A C +C ) = ABC+(AB +A B+A C+B C)(A B +B C +A C +C ) = ABC+(AB +A B+A C+B C)(A B +B C +C (1+A )) = ABC+(AB +A B+A C+B C)(A B +B C +C ) because 1+A = 1 = ABC+(AB +A B+A C+B C)(A B +C (1+B )) = ABC+(AB +A B+A C+B C)(A B +C ) because 1+B = 1 = ABC+(AB A B +A BA B +A CA B +B CA B +AB C +A BC +A CC +B CC = ABC+(0+0+A B C+AB C +A BC +0+0) = ABC+A B C+AB C +A BC = m7+m1+m4+m2 F2 = (1, 2, 4, 7) Using F1 and F2 draw the truth table for the given circuit. Table 4.1 By looking the truth table, we can find that F1 output is equal to sum of full adder and F2 output is equal to carry of full adder output. So the given circuit functions as full adder.
Example: Analyze the following circuit and find the function of circuit. Figure 4.4 Let us redraw the circuit by labeling each and every gate output. Figure 4.5 After labeling every logic gate output, write Boolean function for every label. T1 = x T2 = y T3 = T1.y = x.y T4 = T2.x = xy T5 = w.z T6 = T5.x.y = wxyz F1 = T3+T4+T5 F1 = x y+xy +wz F2 = (F1+T6) F2 = (x y+xy +wz+wxyz)
Simplify the Boolean functions using basic theorems. F2 = (x y+xy +wz+wxyz) = (x y) (xy ) (wz) (wxyz) = (x+y )(x +y)(w +z )(w +x +y +z ) = (ww +x+y )(ww +x +y)(w +xx +z )(w +x +y +z ) = (w+x+y )(w +x+y )(w+x +y)(w +x +y)(w +x+z)(w +x +z )(w +x +y +z ) = (w+x+y +zz )(w +x+y +zz )(w+x +y+zz )(w +x +y+zz )(w +x+yy +z)(w +x +yy +z )(w +x + y +z ) =(w+x+y +z)(w+x+y +z )(w +x+y +z)(w +x+y +z ) (w+x +y+z)(w+x +y+z )(w +x +y+z)(w +x +y+z )(w +x+y+z)(w +x+y +z)(w +x +y+z)(w +x +y +z )(w +x +y +z ) =(w+x+y +z)(w+x+y +z )(w +x+y +z)(w +x+y +z ) (w+x +y+z)(w+x +y+z )(w +x +y+z)(w +x +y+z )(w +x+y+z))(w +x +y +z ) = M2.M3.M10.M11.M4.M5.M12.M13.M8.M15 = (2, 3, 4, 5, 8, 10, 11, 12, 13, 15) = (0, 1, 6, 7, 9, 14) Using F1 and F2 draw the truth table for the given circuit.
Table 4.2
4.3 Design Procedure The design of combinational circuit starts from a specification of the problem and ends in a logic diagram. The procedure involves the following steps: 1. From the specifications of the circuit, determine the required number of inputs and outputs, and assign a letter symbol to each. 2. Derive the truth table that defines the required relationship between inputs and outputs. 3. Obtain the simplified Boolean functions of each output as function of the input variables. 4. Draw the logic diagram. 5. Verify the correctness of the design. 4.4 Adders Half adder Half adder adds two one bit numbers. Suppose if we label the inputs as x and y (where x and y are one bit numbers), we will get maximum of two bit output. Remember that while adding two numbers of n bits the output will have (n+1) bits. So while adding two one bit numbers we get two bit output. One bit is sum and another bit is carry occurred while addition. So give the label name as s (sum) and c (carry). Figure 4.6 Let us form a truth table for the half adder.
Table 4.3 Obtain the canonical form of Boolean function from the truth table for each output. The sum output (s) is 1 for inputs 1 & 2. The carry output (c) is 1 for input 3. S = (1,2) = m1+m2 = x y+xy C = (3) = m3 = xy We will try to simplify this Boolean function using Karnaugh map. Figure 4.7 From the K-map we find that the Boolean function cannot be simplified further. So the logical expression for the half adder circuit is S = (1,2) = m1+m2 = x y+xy C = (3) = m3 = xy Using these logical expression draw the logical circuit for half adder.
Figure 3.8 As S = x y+xy, which is function of XOR gate, we can replace NOT, AND, OR gate by XOR gate and simplify the circuit. Full adder Figure 3.9 The full adder circuit adds three one-bit binary numbers (x, y, z) and outputs two one-bit binary numbers a sum (S) and a carry (C). Figure 3.10
Let us form a truth table for the full adder. Table 4.3 Obtain the canonical form of Boolean function from the truth table for each output. S = (1, 2, 4, 7) = m1+m2+m4+m7 = x y z+x yz +xy z +xyz C = (3, 5, 6, 7) = m3+m5+m6+m7 = x yz+xy z+xyz +xyz Simplify this Boolean function using Karnaugh map. Figure 4.11 From the K-map, simplified Boolean function is S = x y z+x yz +xy z +xyz C = xy+yz+xz Using these logical expression draw the logical circuit for full adder.
Figure 4.12 Full adder using two Half adders: We can design a full adder using two half adders also. In a half adder we can add two one-bit numbers and get two one-bit output sum and carry. By adding output of sum with third input we can make it as full adder. Full adder carry output present if any one half adder produces carry. This can be done by using OR gate. Figure 4.13
By replacing half adder by its logic circuit we can obtain the full adder circuit using two half adders and one OR gate. Binary adder Figure 4.14 An n-bit adderis a circuit which adds two n-bits numbers, say, A and B. In addition, an n- bit adder will have another single-bit input which is added to the two numbers called the carry-in (Cin). The output of the n-bit adder is an n-bit sum(s) and a carry-out (Cout) bit. The block diagramof the n-bit adder is shown. Figure 4.15 Ifall input bits ofthe two numbers (A& B)are applied simultaneously in parallel, theadder is termed a Parallel Adder. Consider the problemof designing a 4-bit binary parallel adder. The total number of inputs is 9, since the two numbers have 4-bits each in addition tothe Cinbit. Using conventional techniques for design would require a truth table of 2 9 =512 rows. This causes the conventional design procedure tobe unacceptable in this case. Alternatively, the 4-bit binary parallel adder can be designed using 4 full adders connected in-cascade asshown in the figure. B3 A3 B2 A2 B1 A1 B0 A0 C out Full Adder Full Adder Full Adder Full Adder C in S3 S2 S1 S0
That is the carry-outbit of one full adder stage is used as carry-ininput tothe next stage. In general, ann-bit binaryparallel adder can be built out ofnfull adders connected in cascade. Since a carry of 1 may appear near the least significant bit ofthe adder and yet propagate through many full adders to the mostsignificant bit, justas a wave ripples outward from a stone hit in a pond. That is why this parallel adder is also called as ripple carry adder. BCD adder Iftwo BCD digits are added then their sumresult will not always be in BCD. Consider the given examples. 0110 = 6 + 0010 = 2 1000 = 8 Correct Result: Result is BCD 0110 = 6 + 0100 = 4 1010 = 10 Wrong Result: Result is not BCD number In the first example, result is in BCD while in the second example it is not in BCD. Four bits are needed torepresent all BCD digits (0 9). But with four bits we canrepresent up to 16 values(0000 through 1111). The extra six values (1010 through 1111) are not valid BCD digits. Whenever the sumresult is >9, it will not be in BCD and will requirecorrection to get a valid BCD result.
Table 4 Correction is done through the addition of 6 to the resultto skip the six invalid valuesas shown in the truth table by shaded area. Consider the given examples of non-bcdsumresultanditscorrection.. 0101 = 5 +0111 = 7 1100 = 12 +0110 = 6 Non BCD number BCD Correction 1 0010 = 12 BCD Number
A BCD adder is a circuit that adds two BCD digits in parallel and produces a sumbcd digitand a carry out bit. Themaximum sum resultofabcd inputadder can be 19. As maximumnumber in BCD is 9 and may be there will be a carry fromprevious stage also, so 9 + 9 + 1 = 19. The following truth table shows allthe possible sumresultswhen two BCD digits are added.
Table 4.5 The logic circuit that checks the necessarybcd correction can be derived by detecting the condition where the resulting binary sum is 01010 through 10011 (decimal 10 through 19). It can be done by considering the shown truth table, in which the function Fis true when the digit is not a valid BCD digit. It canbe simplified using a 5-variable K-map. But detecting values 1010 through 1111 (decimal 10 through 15)can also be done by using a 4-variable K-map as shown in the figure.
Figure 4.16 F = z 3 z 2 +z 1 z 0 Values greater than 1111, i.e., from10000 through 10011(decimal 16 through 19)can be detected by the carry out (CO) which equals 1 only for these output values. So, F = CO = 1 for these values. Hence, Fis truewhen COis true OR when (Z3Z2+ Z3 Z1) is true. Thus, the correction step (adding 0110) is performed if the following function equals 1: F = CO + Z3Z2+ Z3 Z1 The circuit ofthe BCD adder willbe as shown in the figure. Figure 4.17
The two BCD digits, together with the input carry, are first added in the top 4-bit binaryadder to produce the binary sum.the bottom4-bit binary adder is used to add the correction factor to the binary result of the top binary adder. 4.5 Subtractors Half subtractor A half subtractoris an arithmetic circuit that subtracts two bits and produces their difference. The circuit has two inputs minuend (X) and subtrahend (Y) and two output bits, one is the difference bit (D) and the other is the borrow bit (B). Figure 4.18 Let us form a truth table for the half adder. Table 4.6 Obtain the canonical form of Boolean function from the truth table for each output. D = (1,2) = m1+m2 = x y+xy B = (1) = m1 = x y We will simplify this Boolean function using Karnaugh map.
Figure 4.19 From the K-map we find that the Boolean function cannot be simplified further. So the logical expression for the half subtractor circuit is D = (1,2) = m1+m2 = x y+xy B = (3) = m3 = xy Using these logical expression draw the logical circuit for half subtractor. Figure 4.20 As S = x y+xy, which is function of XOR gate, we can replacenot, AND, OR gate by XOR gate and simplify the circuit.
Figure 4.21 Full subtractor A full subtractoris a combinational circuit that performsa subtraction between two bits,taking into account that a 1 may have been borrowed by a lower significant bit. Figure 4.22 Let us form a truth table for the full subtractor. Table 4.7
Obtain the canonical form of Boolean function from the truth table for each output. D = (1, 2, 4, 7) = m1+m2+m4+m7 = x y z+x yz +xy z +xyz B = (1, 2, 3, 7) = m1+m2+m3+m7 = x y z+x yz +x yz+xyz Simplify this Boolean function using Karnaugh map. Figure 4.23 From the K-map, simplified Boolean function is D = x y z+x yz +xy z +xyz B = x y+yz+x z Using these logical expression draw the logical circuit for full subtractor. Figure 4.24
Binary subtractor An n-bit subtractoris a circuit which subtracts two n-bits numbers, say, X and Y. An n-bit subtractor will have another single-bit input which is borrow from previous subtraction process called borrow-in (Bin). The output of the n-bit subtractor is an n-bit difference (D) and a borrow-out (Bout) bit. The block diagramof the n-bit subtractor is shown. Figure 4.25 Consider the problemof designing a 4-bit binary subtractor. The total number of inputs is 9, since the two numbers have 4-bits each in addition tothe Binbit. Using conventional techniques for design would require a truth table of 2 9 =512 rows. This causes the conventional design procedure tobe unacceptable in this case. Alternatively, the 4-bit binary adder can be used as 4-bit binary subtractor by using 2 s complement procedure. As we have discussed in chapter1, 2 s complement subtraction process is accomplished by 2 s complementing the subtrahend and adding it to the minuend. Figure 4.26 Carry-outbit of most significant full adder stage can be ignored as we have done in 2 s complement subtraction procedure. In general, ann-bit binarysubtractor can be built out ofnfull adders connected in cascade.
4.6 Multipliers Multiplication ofbinary numbers is performed in the sameway as with decimal numbers. The multiplicand is multipliedby each bit ofthe multiplier, startingfromthe leastsignificant bit. The result ofeach suchmultiplication forms a partial product. Successive partial productsare shifted one bit to the left. The product is obtained by adding these shifted partial products. Example: Consider an example of multiplication of two numbers, say A and B (2 bitseach),c = AxB. The first partial product isformed by multiplying theb1b0bya0. The multiplication oftwo bits suchasa0andb0produces a 1 if both bits are 1;otherwise it produces a 0 like an AND operation. So the partial products can be implemented with AND gates. The second partial product is formed by multiplying the B1B0byA1and is shifted one position to the left. B1 B0 X A1 A0 A0B1 A0B0 A1B1 A1B0 C3 C2 C1 C0 The two partial products are added with two half adders (HA). Usually there are more bits in the partial products, and thenit will benecessary to use FAs. Figure 4.27 The least significant bit of the product does nothave to go through anadder, since it isformed by the output of the first AND gate as shown in the Figure. A binary multiplier with more bits canbe constructed in a similar manner.
Example: Consider the example of multiplying two numbers; say A (3-bit number) and B (4- bitnumber). Each bit of A (the multiplier) is ANDed with each bit of B (the multipcand) as shown inthe Figure. B3 B2 X A2 A1 B1 B0 A0 A0B3 A0B2 A0B1 A0B0 A1B3 A1B2 A1B1 A1B0 A2B3 A2B2 A2B1 A2B0 C6 C5 C4 C3 C2 C1 C0 The binary output in each level of AND gates areadded in parallel withthe partialproduct of the previous level to forma new partial product. The last level produces the finalproduct. Figure 4.28
4.7 Code convertors Code converters are circuits which translate information from one binary code to another code. Consider, for example, a Binary to gray code converter. Binary to gray code converter: In binary to gray code converter, the input is 4-bit binary code (0000 to 1111) and the output is equivalent gray code. So assign labelto each of the input and output. To mention binary input, B 3, B 2, B 1, B 0 are given as label name and to mention gray code output G 3, G 2, G 1, G 0 are given as label. Let us first develop the truth table for this code converter. Table 4.8 Next stage is to obtain the Boolean function for each output from the truth table. G3 = (8, 9, 10, 11, 12, 13, 14, 15) G2 = (4, 5, 6, 7, 8, 9, 10, 11) G1 = (2, 3, 4, 5, 10, 11, 12, 13) G0 = (1, 2, 5, 6, 9, 10, 13, 14) Simplify these Boolean functions using Karnaugh map.
Figure 4.29 Simplified Boolean expressionsare G3 = B3 G2 = B3 B2+B3B2 G1 = B2B1 +B2 B1 G0 = B1B0 +B1 B0 By looking the Boolean expressions for G2, G1 and G0, we know that they are exclusive- OR functions. So we can replace XOR function instead of basic logic functions and circuit can be simplified further. G3 = B3 G2 = B3 B2 G1 = B2 B1 G0 = B1 B0 Draw the logic diagram for binary to gray converter from these Boolean expressions.
Figure 4.30 Example: BCD to excess-3 Code Converter In this problem, the input is a BCD codeword. Since this is a 4-bit code that represents a decimal digit (0-to-9), there will be 4 input bits which will be represented by four input variables A,B,C, and D. Output is a 4-bit excess-3 code (W, X, Y,Z). Having defined the inputs andoutputs, we proceed to build the truth table for this code converter. The truth table, lists the values of the output (that is the excess-3 code) for all possible combinations of the binary code. Note that, these codes are for decimal digits 0-9. In other words, even though the 4 bits of the input can represent up to 16 different combinations, ONLY 10 combinations are used torepresent the 10 decimal digits. Thus, a total of 6 input combinations are not likely to occur. Since these inputs will never occur, we use don t cares for the corresponding output codes.
Table 4.9 Decimal Input Output digits A B C D W X Y Z 0 0 0 0 0 0 0 1 1 1 0 0 0 1 0 1 0 0 2 0 0 1 0 0 1 0 1 3 0 0 1 1 0 1 1 0 4 0 1 0 0 0 1 1 1 5 0 1 0 1 1 0 0 0 6 0 1 1 0 1 0 0 1 7 0 1 1 1 1 0 1 0 8 1 0 0 0 1 0 1 1 9 1 0 0 1 1 1 0 0 10 x x x x 11 x x x x 12 x x x x Invalid Inputs 13 x x x x 14 x x x x 15 x x x x Boolean expressions for the outputs are W = (5, 6, 7, 8, 9)+d(10, 11, 12, 13, 14, 15) X = (1, 2, 3, 4, 9) + d (10, 11, 12, 13, 14, 15) Y = (0, 3, 4, 7, 8) + d (10, 11, 12, 13, 14, 15) Z = (0, 2, 4, 6, 8) + d (10, 11, 12, 13, 14, 15) As the procedure, we will minimize thefour output functions using K-maps. Thus we will be having four K-maps, one for each outputfunction. Each of these K-maps are given below
Figure 4.31 BCD to Excess-3 code converter circuit diagram is given below.
Figure 4.32 4.8 Introduction to hardware description language The hardware description language is a programming language to describe the hardware and its initial purpose was to simulate the logic circuit and design of logic circuit could be verified before implementing the logic circuit in hardware. Now logic synthesis tools are available to directly implement the hardware from Hardware Description Language (HDL). HDL allows the user to describe the logic circuit in writing programming language and run the program to simulate the logic circuit. If the desired output is not obtained then debug the program to correct the mistake. After getting the desired simulation output, we can implement the logic circuit in hardware. HDL allows the user to implement the logic circuit in hardware much faster than the conventional method and reduces the cost of the circuit. The conventional method was to design the circuit and implement it in hardware. If the desired output is not obtained then debug the design then once again implement it. The disadvantage of this conventional method is overcome by using HDL. HDL combined with Field Programmable Gate Array (FPGA) chips we can implement large complex circuits (millions of logic gates) easily. Types of HDL There are many different types of Hardware Description Language (HDL). Some of HDLs are given below. Verilog HDL ABEL VHDL
VHDL means Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (HDL). VHDL is the large standard HDL developed by US DoD. VHDL is mostly used in industrial standards. Verilog HDL is the second large standard HDL. Verilog programs are mostly used for teaching and simple applications. Verilog HDL is easier to use as it used C like syntaxes. Verilog was developed as proprietary language in 1985 and then it was opened as public domain in 1990. Verilog became IEEE standard HDL in 1995. Verilog HDL Verilog constructs use defined keywords like and, or, not, wire, input, output etc. module is one important construct which has inputs and outputs. Modules can be built up using Verilog primitives or user defined primitives. All the keywords must be in lowercase letters as Verilog is case sensitive language. Variable name can be defined as like in C language. Example 1: Figure 4.33 Now we are going to describe this circuit using Verilog HDL. As first step we have to assign label for each and every gate and interconnections. After labeling the AND gate, NOT gate, OR gate by g1, g2, g3 respectively and interconnection as e, the circuit can be redrawn as follows. Figure 4.34 module example_circuit1 (A, B, C, x, y); input A, B, C; output x, y; wire e; and g1 (e, A, B); not g2 (y, C);
or g3 (x, e, y); endmodule The program starts with the keyword module and ends with the keyword endmodule. Interconnections are named with wire. There are three inputs named with input keyword and two outputs named with the keyword output. All the lines must be terminated by semicolon except endmodule. Test bench In order to simulate the circuit, we have to give some inputs to obtain the output from the circuit. The inputs given to the circuits are often called as circuit stimulus. An HDL module can be written to provide the circuit stimulus. The module written for circuit stimulus is known as test bench. Test bench module includes the module to be tested. There are no keyword input and output for test bench module. The inputs to test the circuit are defined with the keyword reg and the outputs with the keyword wire. The input binary values are specified with the keyword initial. If more than one inputs need to be given to test the circuit, we can use the keyword begin and end. The notation A = 1 b0; is used to give the binary input. Here A is the input variable name which is one bit value and A = 0. The end of simulation is specified with $finish. module stimcircuit; reg A, B, C; wire x, y; example_circuit1 ec (A, B, C, x, y); initial begin #100 #100 A = 1 b0; B = 1 b0; C = 1 b0; A = 1 b1; B = 1 b0; C = 1 b1; $finish; end endmodule #100 is used to create 100ns delay to execute the next line. So initially the inputs A= 0, B= 0, C = 0 will be applied as inputs to the circuit. After 100ns the inputs will be changed to A = 1, B = 0, C = 1. Again after 100ns the simulation will be end with the line $finish.
Example 2: Let us consider the same circuit as in example1. But now the propagation delay of the logic gates is taken into account. What is meant by propagation delay? Propagation delay Propagation delay of a logic gate is the time required to produce the output after applying the inputs to the logic gate. Generally the propagation delay will be in nanoseconds. Figure 4.35 To simulate a circuit in a real world environment it is important to include propagation delay. Let us assume the logic gates shown in the circuit have some propagation delay. Component delays are denoted by the symbol # (hash) in the programs. The circuit with delays is shown below. Figure 4.36 module circuit_with_delay (A,B,C,x,y); input A,B,C; output x,y; wire e; and #(30) g1(e,a,b); or #(20) g3(x,e,y); not #(10) g2(y,c); endmodule In this example AND gate is having 30ns propagation delay, OR gate with 20ns propagation delay and NOT gate with 10ns propagation delay. Now we will see the effect of delay in the output of the circuit. Assume that the input to the circuit is initially 000 and then changed to 111.
Table 4.10 Time (ns) Input Output A B C y e x <0 0 0 0 1 0 1 0 1 1 1 1 0 1 10 1 1 1 0 0 1 20 1 1 1 0 0 1 30 1 1 1 0 1 0 40 1 1 1 0 1 0 50 1 1 1 0 1 1 When the inputs are 000, the output x and y are 11. If the inputs are changed to 111, then the expected output x and y are 1 and 0 respectively. But because of effect of propagation delay the output is switched from 11 to 10 to 00 to 10. The output goes to unstable state before getting the final output which is unwanted thing happened due to the propagation delay. Primitive The standard logic gates are defined in Verilog systems which are called as system primitives. For example, the keyword and, or, not are called as system primitives. Apart from these system primitives, user also can define their own primitives which are called as User Defined Primitive (UDP). UDP must have only one output. UDPs are defined by truth table. primitive crctp (x,a,b,c); output x; input A,B,C; //Truth table for x(a,b,c) table // A B C : x (Note -comment) 0 0 0 : 1; 0 0 1 : 0; endtable endprimitive 0 1 0 : 1; 0 1 1 : 0; 1 0 0 : 1; 1 0 1 : 0; 1 1 0 : 1; 1 1 1 : 1;
After defining Primitive, UDP can be used in the module by its name. Note that primitive is not a module. 4.8 Summary The combinational circuit is a circuit which produces the output depends upon the present combinations of inputs only. The combinational circuit is not having any feedback or memory elements in it. The combinational circuit analysis procedure is explained with example. The analysis of the circuit is that given a circuit in hand, we have to say the function of the circuit. The design of the circuit is reverse process of analysis. Given the requirement specifications of the circuit, we have to obtain the circuit using logic gates. We have designed arithmetic circuits like half adder, full adder, binary adder, BCD adder, half subtractor, full subtractor, binary subtractor and multiplier in detail. Half adder is the circuit which adds two bits (say x and y) and produces the sum and carry. Full adder is the circuit which adds three bits (say x, y and z) and produces the sum and carry. Binary adder which adds two binary numbers each having n bits. Then we have designed circuit to convert one binary code to other code. We have considered the examples of converting binary to gray code converter, BCD to Excess3 code converter. In the similar manner we can design any code converter circuit. Finally we have introduced the Hardware Description Language (HDL). In HDL, Verilog is the most used HDL for simple circuit design. HDL is used to design the logic circuit in fast and cost efficient way by simulating the design before implementing the circuit in hardware. We have taken a simple circuit and written the Verilog programs. Review Questions 1. Design a combinational circuit with three inputs and one output. The output is equal to logic-l when the binary value of the input is less than 3. The output is logic-o otherwise. 2. A majority function is generated in a combinational circuit when the output is equal to I if the input variables have more 1 's than a's. The output is a otherwise. Design a 3-input majority function. 3. A combinational circuit produces the binary sum of two 2-bit numbers, XtXO and y,yo. The outputs are C, St, and So. Provide a truth table of the combinational circuit. 4. Show that a full-subtractor can be constructed with two half-subtractors and an OR gate. 5. Design a combinational circuit with three inputs and six outputs. The output binary number should be the square of the input binary number. 6. Design a code converter that converts a decimal digit from the 8 4-2 -1 code to BCD. 7. Design a combinational circuit that converts a decimal digit from the 2 4 2 1 code to the 84-2 -1 code.
8. Derive the truth table of the circuit shown in Fig. Figure 4.37 9. Determine the Boolean functions for outputs F and G as a function of four inputs, A, B, Cand D. Figure 4.38 10. Design a combinational circuit that converts a 4-bit Gray code number to a 4-bit straight binary number. Implement the circuit with exclusive-or gates.