Chapter 7. Digital Arithmetic and Arithmetic Circuits. Signed/Unsigned Binary Numbers

Chapter 7 Digital Arithmetic and Arithmetic Circuits Signed/Unsigned Binary Numbers Signed Binary Number: A binary number of fixed length whose sign (+/ ) is represented by one bit (usually MSB) and its magnitude by the remaining bits. Unsigned Binary Number: A binary number of fixed length whose sign is not specified by a bit. All bits are magnitude and the sign is assumed +. 2

Unsigned Binary Arithmetic Sum: Result of an Addition Operation of two (or more) binary numbers (operands). Carry: A digit (or bit) that is carried over to the next most significant bit during an n-bit addition operation. The carry bit is a if the result was too large to be expressed in n bits. 3 Basic Rules (Unsigned) One-Bit Unsigned Addition C A B C in + + = out + + = + + = + + = 4 2

Binary Addition Examples carry to next + + Carry out bit 5 Basic Subtraction Basic Subtraction of x = a b, with a = minuend( 被減數 ), b = subtrahend ( 減數 ), and x = difference or result. Requires a Borrow Bit if a < b. There are other forms of subtraction such as 2 s Complement Addition used by microprocessors (such as in a PC). 6 3

Basic Subtraction Rules B in A - - - - B Borrow = = = = Diff 此處應該為 7 Binary Subtraction with Borrow Examples - - () () Borrow Stage Borrow ripples to LSB 8 4

Signed Binary Numbers Sign Bit: A bit (usually the MSB) that indicates whether a number is positive (= ) or negative (= ). Magnitude Bits: The bits of a signed binary number that tell how large it is in value. 9 Signed Binary Numbers 2 True-Magnitude Form: A form of signed binary whose magnitude bits are the TRUE binary form (not complements). Also called sign-magnitude format 5

Signed Binary Numbers 3 s Complement: A form of signed binary in which negative numbers are created by complementing all bits. 2 s Complement: A form of signed binary in which the negative numbers are created by complementing all the bits and adding a ( s Complement + ). True-Magnitude Form 5-Bit Numbers Negative Sign (S = ) +25 = (Note sign bit (MSB) Sign = ) 25 = (Same as +25 with sign = ) +2 = 2 = 2 6

s Complement Form 8-Bit s Complement Negative (S = ) +57 = 57 = (All Bits Inverted) +72 = 72 = 3 2 s Complement Form Used in MPU (PC) Arithmetic 原講義錯誤 57-57 - 72 = = + + +72= 4 7

Signed Binary Addition (8-Bit) Signed Addition Positive (S = ) + 3 = + 75 = Similar to binary addition with a sign bit. 5 Subtraction with s Complement Add the s Complement and then Carry. + 8-65 = ( + 8) = = ( + 65) = + (' s Comp 65) Uses an End around carry addition method. 6 8

2 s Complement Subtraction Add 2 s Complement to Minuend. + 8 = + 65 = + 65 = + Discard Carry Bit from Result 只要記住以 2 s complement 來運算,Carry 一律捨棄即可 7 Negative Results If the True-Magnitude Form is used for subtraction, the results are incorrect. If the result is from s or 2 s Complement and the result is negative (S = ), the magnitude is found by taking the complement of the result.( 當運算結果的 Sign bit 為 時表示結果為 Negative number, 此時僅需再轉換為該數值之 Complement 即知是負多少 ; 至於要轉換為 s complement 或是 2 s complement 就看原來是使用哪一種負數表示法而定 ) 8 9

Negative Result Example 2 s Complement Negative Result (65 8) + 65 = - 8 = (2' s C.) Final Result + Invert Add + =(-5 ) = (5 ) = (+5 ) 9 Range of Signed Numbers Range of Positive Numbers is to 2 (n-) for a number with n bits. Range of Negative Numbers is to 2 (n-) for a number with n bits. 8-Bit Example: 8-Bit Number Range is 2 (n-) x +2 (n-) or 28 to +27 2

Sign Bit Overflow Overflow: An erroneous carry into the sign bit of a signed binary number Results from a sum or difference that is larger than can be represented by the magnitude bits. Results in a False Positive or False Negative Number. 只有相同符號運算時才會有 Overflow 發生的可能 ( 例如 :+A+B;-A-B) 檢查 Sign bit 是否改變即知是否發生 Overflow 2 False Negative Overflow Addition of two 8-Bit Positive Numbers: + 75 = + 96 = + Result is Negative (False) Two positive numbers added with a result greater than the range of +27 for 8-bit numbers causes an overflow. 22

False Positive Overflow Addition of two 8-Bit Negative Numbers: 8 65 = = + Both in 2 s complement form! Result is Positive (False) Two Negative numbers were added to produce a False Positive Result due to overflowing the negative range of 8-bit numbers ( to 28). 23 Hexadecimal Addition Similar to decimal addition with a range of digits of to 9 and A to F. Examples: F + = F + F = E F + F + = F 24 2

Hexadecimal Addition Hex 26B3H + A9CH For sums greater than 5, subtract 6 and carry to the next position. Carry Hex = Decimal Equivalent ( 2)( 6) ()( 3) ( )()( 9)(2) (3) (6)(2)(5) ( 2)( 6) ()(3) ( )()( 9)(2) ( 4)( ) ( 4)(5) 44FH 先轉成十進位 25 Hexadecimal Subtraction Hex 26B3H A9CH from the previous position. Borrow Hex = Decimal Equivalent (2)(6)()(3) ()()(9)(2) To subtract the least significant digit, borrow H (6 ()(6 + 6) ()(6 + 3) - () () ()(2) C7H (9) (2) () ( 7) ) 26 3

BCD Codes BCD Code (Binary-Coded Decimal): A code used to represent each decimal digit of a number by a 4-Bit Binary Value. Valid Digits for to 9 are to. The binary codes to are invalid Called an 842 Code due to the decimal weight of each bit position. 27 BCD Examples Each digit is a 4-Bit Binary group: (84) = (4987) = BCD 28 4

Excess-3 Code A BCD Code formed by adding 3 () to its true 4-bit binary value. Excess-3 is a self-complementing code: A negative code equivalent can be found by inverting the binary bits of the positive code Inverting the bits of the Excess-3 digit yields 9 s Complement of the decimal equivalent. See next page for reference. 29 Excess-3 Code Decimal Digit 842 Excess-3 2 3 4 5 6 7 8 9 3 5

Excess-3 Examples 3 = + = = 6 in E3. = + = = 4 in E3. If we complement = in E3, this is the code for an 8. 9 s Complement of = (9 ) = 8 (Self- Complement) 3 Gray Code A binary code that progresses so that only one bit changes between two successive codes. 32 6

Gray Code and Binary Binary: b 3 b 2 b b Gray: g 3 g 2 g g Gray code bits can be defined as follows: g 3 = b 3 g 2 = b 3 b 2 g = b 2 b g = b b 33 ASCII Code American Standard Code for Information Interchange. A seven-bit alphanumeric code used to represent text letters, numerals, punctuation ( 標點符號 ), and special controls. An expanded 8-bit form is becoming more widespread. 34 7

Binary Adders Half Adder (HA): A circuit that will add two bits and produce a sum bit and a carry bit. Full Adder (FA): A circuit that will add a carry bit from another HA or FA and two operand bits to produce a sum bit and a carry bit. 35 Basic HA Addition Binary Two-Bit Addition Rules: + = + = + = 36 8

HA Circuit Basic Equations: S = A XOR B, C = A and B where S = Sum and C = Carry. Truth Table for HA Block: A B Σ C OUT 原講義錯誤 Σ = AB + AB = A B C OUT = AB 37 HA Circuit 38 9

Full Adder Basics Adds a C IN input to the HA block. Equations are modified as follows: C Σ OUT = ( A B) C = ( A B) C IN IN + A B A FA can be made from two HA blocks and an OR Gate. 39 Full Adder Basics 4 2

Full Adder Basics 4 Full Adder Basics 42 2

Parallel Adders A circuit, consisting of n full adders, that will add n-bit binary numbers. The output consists of n sum bits and a carry bit. C OUT of one full adder is connected to C IN of the next full adder. 43 Parallel Adders 44 22

Ripple Carry In the n-bit Parallel Adder (FA Stages) the Carryout is generated by the last stage (FAN). This is called a Ripple Carry Adder because the final carryout (Last Stage) is based on a ripple through each stage by C IN at the LSB Stage. 45 Ripple Carry 2 Each Stage will have a propagation delay on the C IN to C OUT of one AND Gate and one OR Gate.(See P.4;A B 必定先產生結果然後等待 Cin 的到來, 再做 AND, 最後經由 OR 輸出 ) A 4-Bit Ripple Carry Adder will then have a propagation delay on the final C OUT of 4 2 = 8 Gates. A 32-Bit adder such as in an MPU in a PC could have a delay of 64 Gates. 46 23

Ripple Carry - 3 47 Look-Ahead Carry Fast Carry or Look-Ahead Carry: A combinational network that generates the final C OUT directly from the operand bits (A to A n, B to B n ). It is independent of the operations of each FA Stage (as the ripple carry is). 48 24

Look Ahead Carry 2 Fast Carry has a small propagation delay compared to the ripple carry. The fast carry delay is 3 Gates for a 4- Bit Adder compared to 8 for the Ripple Carry. 49 Look Ahead Carry 3 5 25

Look Ahead Carry 4 P i =A i B i G i =A i B i 5 Using carry look-ahead to reduce the propagation delay Carry propagate: P i = A i B i Carry generate: G i = A i B i Sum: S i = P i C i Carry: C i+ = G i +P i C i C = Input carry C = P C +G C 2 = P C +G = P (G + P C ) + G = P G + P P C +G C 3 = P 2 C 2 +G 2 = P 2 P G + P 2 P P C + P 2 G + G 2 52 26

Look Ahead Carry 6 P i 與 G i 需一個 Gate 的 Delay 再加上此處的兩級, 因此共有三個 Gate 的 Delay time 53 Parallel Adder Created in VHDL by using multiple instances of a full adder component in the top-level file of a VHDL design hierarchy. 54 27

Parallel Adder 55 VHDL Full Adder ENTITY full_add IS PORT( a, b, c_in : IN STD_LOGIC; c_out, sum : OUT STD_LOGIC; END full_add; ARCHITECTURE adder OF full_add IS BEGIN c_out <= ((a xor b) and c_in) or (a and b); sum <= (a xor b) xor c_ini; END adder; 這是最基本 / 底層的 Component, 只有 Single bit! 56 28

Parallel Adder VHDL Requires a separate component file for a full adder, saved in a folder where the compiler can find it(i.e., in the Library path). A component declaration statement is required in the top-level file of the design hierarchy( 要使用 Component 的上層電路必須要在 Architecture 中加以宣告 ; 宣告 Component name 以及 I/O Port). A component instantiation statement for each instance of the full adder component( 在 Architecture 中還需要 Make Instances; 亦即建立 Component 實體 ). 57 Parallel Adder VHDL Code ENTITY add4par IS PORT( c : IN STD_LOGIC; a,b : IN STD_LOGIC_VECTOR (4 downto ); c4 : OUT STD_LOGIC; sum : OUT STD_LOGIC_VECTOR (4 downto )); END add4par; 這是 4 bit 的全加法器 ; 使用 Full_add 作為 Component! 58 29

Parallel Adder VHDL Code 2 ARCHITECTURE adder OF add4par IS -- Component declaration. COMPONENT full_add PORT( a, b, c_in : IN STD_LOGIC; c_out, sum : OUT STD_LOGIC); END COMPONENT; Full_add 的所有 I/O Port 都需要再宣告一遍 -- Define a signal for the internal carry bits SIGNAL c : STD_LOGIC_VECTOR (3 downto ); 宣告一個 Signal c 用以串接內部訊號 59 Instance Name Parallel Adder VHDL Code 3 BEGIN -- four component instantiation statements. adder : full_add Component Name PORT MAP (a => a(), b => b(), c_in => c, c_out => c() -- connects to c_in of adder 2. sum => sum()); END adder; Instance I/O 6 3

VHDL Generate Statement ENTITY add4gen IS PORT( c : IN STD_LOGIC; a,b : IN STD_LOGIC_VECTOR (4 downto ); c4 : OUT STD_LOGIC; sum : OUT STD_LOGIC_VECTOR (4 downto )); END add4gen; 這是 4 bit 的全加法器 ; 但使用 For Generate 敘述來簡化程式! 6 VHDL Generate Statement 2 ARCHITECTURE adder OF add4gen IS -- Component declaration COMPONENT full_add PORT( a, b, c_in :IN STD_LOGIC; c_out, sum : OUT STD_LOGIC); END COMPONENT; - - Defining a signal for internal carry bits. SIGNAL c : STD_LOGIC_VECTOR (4 downto ); 62 3

VHDL Generate Statement 3 BEGIN c() <= c; -- Input port c mapped to internal signal (c) adders: FOR i IN to 4 GENERATE -- Implicit port mapping. Mapping 的順序必須與 Component 的 I/O Port 宣告順序相同 adder : full_add PORT MAP (a(i), b(i), c(i-), c(i), sum (i)); END GENERATE; c4 <= c(4); -- Output port c4 mapped to internal signal c(4) END adder; 63 Subtractor (2 s Complement) The concept of Subtraction using 2 s Complement addition allows a Parallel FA to be used. This could be used in a MPU ALU (Arithmetic Logic Unit) for Subtraction. The subtract operation involves adding the inverse( 就是取 的補數 )of the subtrahend( 減數 )to the minuend( 被減數 )and then adding a. The adding of a in the last step is equivalent to convert the subtrahend to its 2 s complement( 最後的加 等同於取減數 2 的補數與被減數相加 ). 64 32

Subtractor (2 s Complement) 2 Difference = A B = A + B + This operation can be done in a parallel n-bit FA by inverting (B to B n ) and connecting C IN at the LSB Stage to +5 V( 接 5V 就是最後要加 的意思 ). The circuit can be modified to allow either the ADD or SUBTRACT operation to be performed. 65 Subtractor (2 s Complement) 2 66 33

Parallel Binary Adder/Subtractor XOR gates are used as programmable inverters to pass binary numbers (e.g., B B 2 B 3 B 4 ) to the parallel adder in true or complemented form. When ADD/SUB =, B is complement ed. When ADD/SUB =, B is in its true form. 67 Parallel Binary Adder/Subtractor 這隻腳為 表示做減法用為 表示做加法用 68 34

Parallel Binary Adder/Subtractor 69 VHDL Parallel Binary Adder/Subtractor ENTITY addsub4g IS PORT( Sub 為 表示做減法用 Sub 為 表示做加法用 sub : IN BIT; a,b : IN BIT_VECTOR (4 downto ); c4 : OUT BIT; sum : OUT BIT_VECTOR (4 downto )); END addsub4g; 7 35

VHDL Parallel Binary Adder/Subtractor 2 ARCHITECTURE adder OF addsub4g IS COMPONENT full_add PORT( a, b, c_in : IN BIT; c_out : OUT BIT); END COMPONENT; - - Define a signal for internal carry bits SIGNAL c : BIT_VECTOR (4 downto ); SIGNAL b_comp : BIT_VECTOR (4 downto ); BEGIN 7 VHDL Parallel Binary Adder/Subtractor 3 - - add/subtract select to carry input (sub = for subtract) c() <= sub; adders: FOR i IN to 4 GENERATE --invert b for subtract function (b(i) xor,) --do not invert b for add function (b(i) xor ) b_comp(i) <= b(i) xor sub; adder: full_add PORT MAP (a(i), b_comp(i), c(i -), c(i), sum (i)); END GENERATE; C4 <= C(4); END adder; 72 36

Overflow If the sign bits of both operands are the same and the sign bit of the sum is different from the operand sign bits, an overflow has occurred. Overflow is not possible if the sign bits of the operands are different from each other. 73 Overflow Examples Adding two 8-bit negative numbers( 因為 MSB=): 8H + 8H H + (Sign overflow; Adding two 8-bit positive numbers( 因為 MSB=): 7FH + H 8H bit V = ) (Sign bit overflow; V = ) 74 37

38 75 Overflow 8-bit Parallel Adder sum) of Sign bit ( S S S ) of Sign bit ( B B S ) of Sign bit ( A A S 2 3 4 5 6 7 B 2 3 4 5 6 7 B A 2 3 4 5 6 7 A = = = S S S S S S B S B B B B B A S A A A A A 76 Overflow Detector Truth Table V S S B S A Σ Σ + = S S S S S S V B A B A Sign bit 相異之兩數相加絕對不會 Overflow

Overflow Detector Truth Table S A S B S Y 77 BCD Adder A Parallel Adder whose output sum is in groups of 4 bits, each representing a BCD (842) Digit. Basic design is a 4-Bit Binary Parallel Adder to generate a 4-Bit Sum of A + B. Sum is input to the four-bit input of a Binary-to-BCD Code Converter. 78 39

BCD Adder 79 4