A Step Ahead in Phase Change Memory Technology Roberto Bez Process R&D Agrate Brianza (Milan), Italy 2010 Micron Technology, Inc. 1
Outline Non Volatile Memories Status The Phase Change Memories An Outlook to the Next Steps 2010 Micron Technology, Inc. 2
Non Volatile Memory Market 100 1000 In the last years volume of NVM increased exponentially (with a clear cost reduction..) Total Volume (Eb) 10 1 0.1 100 10 1 Price ($/Gb) 0.01 2000 2002 2004 2006 2008 2010 Year 0.1 NAND Eb DRAM Eb NAND $/Gb DRAM $/Gb This triggered the use of NVM in a wide spectrum of applications Intel-Micron 64Gbit NAND 20nm NAND MLC technology 2010 Micron Technology, Inc. 3
Flash Cell Scaling Challenges Cell basic structure unchanged through the different generations Cell area scaling through: 1. Active device scaling (W/L) 2. Passive elements scaling Main scaling issues: Number of stored electrons Cell proximity interference Tunnel and interpoly dielectric thickness Isolation spacing and WL voltage increase Random Telegraph Noise Trapping/detrapping, SILC Retention after cycling y-pitch NAND L W x-pitch CG C ONO C FG FG C TUN C TUN 2010 Micron Technology, Inc. 4
Key Requirements of an Alternative NVM Readiness for beyond leading edge technology node Scalability Cost structure MLC capable 3D stackable Performance High Program and Read Throughput Low power Flexibility Reliability Non-volatility with long retention (e.g. > 10 years) Extended number of read cycles High program endurance 2010 Micron Technology, Inc. 5
Outline Non Volatile Memories Status The Phase Change Memories An Outlook to the Next Steps 2010 Micron Technology, Inc. 6
Key Messages Significant Innovation Takes Time 2010 Micron Technology, Inc. 7
NVM Technology Development Storage Element Memory Cell Memory Cell Array (Test Chip) 1 st Product Concept Demonstration Technology Validation Manufacturability Product Reliability 2010 Micron Technology, Inc. 8
Non-Volatile Memory History 1967 First Floating Gate Structure 1971 FAMOS 1977 EPROM 1980 EEPROM 1985 1T EEPROM (Flash) 1988 NOR Flash 1989 NAND Flash 1995 MLC NOR 2005 MLC NAND 2010 Intel-Micron 64Gb MLC NAND in 25nm technology 2010 Micron Technology, Inc. 9
History of PCM Development S. Lai and T. Lowrey, IEDM 2001 180nm F. Pellizzer et al., VLSI 2004 180nm F. Pellizzer et al., VLSI 2006 90nm G. Servalli, IEDM 2009 45nm PCM cell M. Gill et al., ISSCC 2002 180nm G. Casagrande et al., VLSI 2004 180nm Bedeschi et al., ISSCC 2008 90nm 128Mb (256Mb MLC) C. Villa et al., ISSCC 2010 45nm 1Gb PCM array & chip 2001 2003 2005 2007 2009 2011 Concept Demonstration Technology Validation Product Reliability Manufacturing 2010 Micron Technology, Inc. 10
Key Messages Significant Innovation Takes Time A NVM Concept/Technology Must Have a Wide Spectrum of Application 2010 Micron Technology, Inc. 11
Phase Change Memory Key Attributes Non Volatility Flexibility No Erase, Bit alterable, Continuous Attributes Non-Volatile Scaling PCM Yes sub-2x nm EEPROM Yes n.a. NOR Yes 3x nm NAND Yes 2x nm DRAM No 3x nm Writing Lower power consumption than RAM Granularity Erase Software Power Small/Byte No Easy ~Flash Small/Byte No Easy ~Flash Large Yes Moderate ~Flash Large Yes Hard ~Flash Small/Byte No Easy High Fast Writes Write Bandwidth 1-15+ MB/s 13-30 KB/s 0.5-2 MB/s 10+ MB/s 100+ MB/s Read bandwidth and writing throughput Read Latency Endurance 50-100 ns 10 6+ 200-200 ns 10 5-10 6 70-100 ns 10 5 15-50 us 10 4-5 20-80 ns Unlimited execution in Place Extended endurance PCM provides an new set of features combining components of NVM with DRAM 2010 Micron Technology, Inc. 12
Selectors and PCM Array Architectures MOSFET BJT/Diode OTS Process Complexity No mask overhead for the selector Dedicated steps for the p-n-p junction integration Dedicated steps in the BEOL Cell Size Larger (~20F 2 ) Smaller (~5F 2 ) 3D cross-point (~4F 2 /n) Memory Array Organization Conventional Innovative Ground-breaking Application Embedded memory High density/ High Performance Very high density BL WL Schematic Cell Structure Cross-section GND WL n+ p-substrate n+ STI BL p+ n+ n-well p-substrate BL OTS OUM WL 2010 Micron Technology, Inc. 13
Embedded PCM (epcm) IMW 2010 IEDM 2009 2010 Micron Technology, Inc. 14
Stand-Alone NVM TAM Expansion ($K) Wireless SSD }Cost, Reliability, & Performance Bulk NAND Industrial / CE } Cost, Cost & Cost!!! Source: isuppli Application Market Forecast Tool, June 2010 2010 Micron Technology, Inc. 15
PCM Application Opportunities PCM feature can be exploited by all the memory system, especially the ones resulting from the convergence of consumer, computer and communication electronics Wireless System to store of XiP, semi-static data and files Bit alterability allows direct-write memory Solid State Storage Subsystem to store frequently accessed pages and elements easily managed when manipulated in place Caching with PCM will improve performance and reliability Computing Platforms taking advantage of non-volatility to reduce the power PCM offers endurance and write latency that are compelling for a number of novel solutions S.Eilert et al., PCM: a new memory enables new memory usage models, IMW, 2009 2010 Micron Technology, Inc. 16
MLC Capability Write Strategies for 2 and 4-bit Multi-Level Phase-Change Memory IBM/Macronix, IEDM 2007 A Multi-Level-Cell Bipolar Selected Phase Change Memory Numonyx, ISSCC 2008 Drift-Tolerant Multileve Phase Change Memory IBM, IMW 2011 2010 Micron Technology, Inc. 17
Key Messages Significant Innovation Takes Time A NVM Concept Must Have a Wide Spectrum of Application A New NVM Must Be Scalable 2010 Micron Technology, Inc. 18
Ultimate Scalability of PCM Y. C. Chen et al., IEDM 2006 P.Wong, EPCOS 2010 Device functionality demonstrated on 60 nm 2 active area Reset current <10uA Phase change mechanism appears scalable to at least ~5nm C. Lam, SRC NVM Forum 2004 2010 Micron Technology, Inc. 19
Outline Non Volatile Memories Status The Phase Change Memories An Outlook to the Next Steps 2010 Micron Technology, Inc. 20
An Outlook to the Future Scaling the existing architecture, providing the smallest cell size, following the lithography roadmap Exploring new chalcogenide alloys which may open new application fields GeTe 40 DVD+RAM 50 60 70 80 90 100 0 10 Te (at %) 20 30 Ge or M (at %) 0 100 10 90 GeSbTe(GST) 20 80 30 147 225 Doped SbTe 70 60 DVD+RW 50 40 30 20 124 M-Sb 2 Te 10 0 40 50 60 70 80 90 100 Sb 2 Te 3 Sb 2 Te Sb (at %) Exploiting a true cross-point array which will allow vertical stacking of more than one memory layer DerChang Kau et al., IEDM 2009 2010 Micron Technology, Inc. 21
PCM Active Material Despite Ge 2 Sb 2 Te 5 has been demonstrated a good material for PCM fabrication, many other chalcogenide materials are available for use in solid state memories, exploiting the experience of optical disk research But other requirements must be satisfied: Ge or M (at %) 0 100 10 90 GeSbTe(GST) 20 30 80 70 Doped SbTe GeTe 40 60 DVD+RAM 50 50 DVD+RW 60 40 70 225 30 80 20 90 124 10 100 147 M-Sb 2 Te 0 0 10 20 30 40 50 60 70 80 90 100 Te (at %) Sb 2 Te 3 Sb 2 Te Sb (at %) Electronic switching capability with reasonable switching voltage Sufficiently low set resistance for reading performances Sufficiently low melting temperature for program performances Stability under million of cycles Higher crystallization temperature for better retention From optical disk experience Ge, Sb, Te, In, Si compounds are most suitable materials for employment in solid state devices 2010 Micron Technology, Inc. 22
GST Ternary Diagram Goal: improve the cell performances GeSbTe ternary compound system GeTe Sb 2 Te 3 pseudo-binary line M. Boniardi et al., IMW 2010 Sb rich region exploration is done to electrically study new compounds in the fast growth Sb 69 Te 31 direction 2010 Micron Technology, Inc. 23
Electrical Characteristics Decrease of the reset resistance with the increase in the Sb concentration Convergence of the set level to the minimum set 2010 Micron Technology, Inc. 24
Higher-Temperature Chalcogenide N-doped GeTe as Performance Booster for Embedded Phase-Change Memories CEA-LETI/ST, IEDM 2010 On Carbon doping to improve GeTe-based Phase-Change Memory data retention at high temperature CEA-LETI/ST, IMW 2010 Electrical Performances of Tellurium-rich Ge x -Te 1-x Phase Change Memory CEA-LETI/ST, IMW 2011 2010 Micron Technology, Inc. 25
Further Key Materials Other key issue of the PCM cell engineering are: Role of thermal environment: thermal conductivity of the surrounding dielectrics Role of thermal interfaces between materials Role of electrical interface between materials 2010 Micron Technology, Inc. 26
PCM Self-Heating Cell Structure Planar structures Vertical self-heating structure with fully confined GST very conformal chalcogenide deposition required (e.g. ALD) 2010 Symp. On VLSI Tech. Samsung 2010 Micron Technology, Inc. 27
3D Integration Cross-Point Memory Crossbar memory attracts great interests simple structure and minimum cell size (4F 2 ) low cost suitable for 3D stacking cell size (4/n)F 2 array over circuitry better array efficiency The basic cell architecture requires a selector structure to be integrated in the BEOL Parasitic paths exist through neighbouring cells Programming (and also reading) can perturb the array V prog V prog /2 V prog /2 V prog /2 0 V V prog /2 2010 Micron Technology, Inc. 28
A Wide Range of Material Choices Selector device Homojunctions polysi p/n junctions Heterojunctions p-cuo/n-inzno Schottky diode Ag/n-ZnO Chalcogenide Ovonic Threshold Switching (OTS) materials Mixed Ionic Electronic Conduction (MIEC) materials Storing device STTRAM RRAM or CBRAM PCM For the selector structure few concepts have been proposed so far, all in the path finding phase 2010 Micron Technology, Inc. 29
Cross-Point Switch Requirements Very high forward bias current greater than the switching current Low reverse bias current Prevent loss of signal by cross talk Leakage may set the block size Composition compatible with memory material Low temperature process Bipolar operation 2010 Micron Technology, Inc. 30
PCMS Memory Cell Cross-Bar Architecture Ovonic Threshold Switch, OTS, is a two-terminal switch Column Row Metal 1 Metal 2 Poly Si-Substrate Intel-Numonyx, IEDM 2009 Chalcogenide materials can be used both for the memory and for the selector (OTS) to form stackable cross point PCM (PCMS) True high density cross-bar Possible multilayer vertical stacking 2010 Micron Technology, Inc. 31
Conclusions The mainstream Non-Volatile Memory (Flash) is today approaching its scaling limitation Several other alternative concepts have been proposed but few of them are really appealing from a cost stand point Among those technology, PCM is today in a privileged position, having already demonstrated functionality and reliability at 90 nm and 45 nm nodes on large products Large room for chalcogenide material and cell engineering Crossbar 3D approach has been identified as a viable way to further reduce the cost/bit 2010 Micron Technology, Inc. 32
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