DESIGN AND IMPLEMENTATION OF A MUSIC BOX USING FPGA TAN KIAN YIAK

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DESIGN AND IMPLEMENTATION OF A MUSIC BOX USING FPGA TAN KIAN YIAK SCHOOL OF MICROELECTRONIC ENGINEERING UNIVERSITY MALAYSIA PERLIS MALAYSIA 2007

DESIGN AND IMPLEMENTATION OF A MUSIC BOX USING FPGA by TAN KIAN YIAK Report submitted in partial fulfillment of the requirements for the degree of Bachelor of Engineering MARCH 2007

ACKNOWLEDGEMENT First and foremost, I would like to extend my highest gratitude to my project supervisor, Pn Siti Zarina bt Md. Naziri as willingly to spend her time giving guidance all the while along the project period. She is really an expertise in FPGA that always shares her precious experience with me. Besides that, her encouragement does boost up my confident to face the challenges. Apart from that, my gratitude goes to my lecturer En. Nazri for allowing me to used the laboratory. He sacrifices time teaching me how to setting the FPGA board when the experiment is carried out. Finally, a special thanks to those people who directly and indirectly giving a helping hands to me. Their kindness are much appreciated and welcomed. Last but not least, this is a wonderful project for me; I enjoy every stage and appreciate everything I gained. I

APPROVAL AND DECLARATION SHEET This project report titled Design and Implementation of A Music Box Using FPGA was prepared and submitted by Tan Kian Yiak (Matrix Number: 031010561) and has been found satisfactory in terms of scope, quality and presentation as partial fulfillment of the requirement for the Bachelor of Engineering (Microelectronic Engineering) in University Malaysia Perlis (UniMAP). Checked and Approved by (PN SITI ZARINA BT MD. NAZIRI) Project Supervisor School of Microelectronic Engineering University Malaysia Perlis March 2007 II

REKACIPTA DAN PERLAKSANAAN KOTAK MUZIK DENGAN PENGGUNAAN FPGA ABSTRAK Suatu rekacipta dan perlaksanaan kotak muzik dengan menggunakan FPGA telah dipersembahkan dalam laporan ini. FPGA merupakan satu cip digital logik yang boleh diprogramkan kepada pelbagai penggunaan digital. Usaha telah diberikan untuk menjadikan FPGA berfungsi sebagai kotak muzik. Altera Education Board yang mengandungi FPGA pelbagai fungsi telah digunakan. Program ditulis menggunakan kod Verilog HDL. Perisian Quartus II digunakan untuk simulasi dan memindahkan program ke dalam FPGA Board. Halangan-halangan wujud dalam FPGA Board mengehadkan saiz program. Sungguhpun, kotak muzik berfungsi dengan baik secara amnya. III

ABSTRACT A design and implementation of music box using FPGA is presented in this report. FPGA is a digital logic chip that can be programmed to do almost any digital function. An effort has been carried out to make the FPGA to perform like a music box. An Altera Education board which contains variety function FPGA is used. The program is written in Verilog HDL coding. Quartus II software is used to simulate the program and downloaded it into the FPGA board. Some limitations exist in the FPGA board which limits the size of the program. However, the music box functions well in general. IV

TABLES OF CONTENTS ACKNOWLEDGEMENT APPROVAL AND DECLARATION SHEET ABSTRAK ABSTRACT TABLE OF CONTENTS LIST OF TABLES LIST OF FIGURES Page I II III IV V IX X CHAPTER 1 INTRODUCTION 1.1 Scope 1 1.2 Motivation 1 1.3 Objectives 2 1.4 Report Outline 3 CHAPTER 2 LITERATURE REVIEW 2.1 Introduction of FPGA 4 2.1.1 Function of a logic cell 5 2.1.2 Field Programmable 5 2.1.3 Creation of FPGA Programs 5 2.2 Introduction of UP2 Education Kit 6 2.2.1 UP2 Education Board 6 V

2.2.1.1 EPF10K70 Device 7 2.2.1.2 EPM7128S Device 7 2.2.1.3 ByteBlaster II Parallel Port Download Cable 8 2.2.2 UP2 Education Board Description 8 2.2.2.1 DC_IN & RAW Power Input 9 2.2.2.2 Oscillator 9 2.2.2.3 JTAG_IN Header 9 2.2.2.4 Jumpers 10 2.2.2.5 EPM7128S Device 11 2.2.2.6 EPM7128S Prototyping Headers 12 2.2.2.7 MAX_PB1 & MAX_PB2 Push-Buttons 13 2.2.2.8 MAX_SW1 & MAX_SW2 Switches 13 2.2.2.9 FLEX10K Device 14 2.2.2.10 FLEX_PB1 & FLEX_PB2 Push Buttons 14 2.2.2.11 FLEX_SW1 Switches 15 2.2.2.12 FLEX_EXPAN_A, FLEX_EXPAN_B & 15 FLEX_EXPAN_C 2.3 Introduction of Verilog HDL 16 2.3.1 Major Capabilities 17 2.4 Introduction to Quartus II 18 2.4.1 Graphical User Interface Design Flow 19 CHAPTER 3 EXPERIMENTAL SETUP 3.1 Software 22 3.1.1 Design Flow for Using Quartus II Graphical User Interface 22 3.2 Hardware 30 3.2.1 Hardware Setup 30 3.2.2 UP2 Education Board Programming or Configuring Devices 31 VI

3.2.2.1 EPM7128S Programming 31 3.2.2.2 EPF10K70 Configuration 33 3.3 Summary 35 CHAPTER 4 RESULTS AND DISCUSSION 4.1 Simple beep 36 4.2 Ambulance siren 37 4.3 Police siren 37 4.3.1 High-speed pursuit 38 4.4 Playing notes 39 4.4.1 Step 1 39 4.4.2 Step 2 39 4.4.3 Step 3 40 4.4.4 Step 4 41 4.5 Summary 42 CHAPTER 5 CONCLUSION 5.1 Summary 43 5.2 Recommendation for Future Work 44 REFERENCES 45 APPENDICES APPENDIX A 48 APPENDIX B 49 APPENDIX C 50 APPENDIX D 51 VII

APPENDIX E 52 APPENDIX F 54 VIII

LIST OF TABLES Tables No. Page 2.0 JTAG_IN 10-Pin Header Pin-Outs 10 2.1 JTAG Jumper Settings 11 2.2 Pin umbers for Each Prototyping Header 13 2.3 FLEX_SW1 Pin Assignments 15 2.4 Commands for Common Compiler Flows 21 IX

LIST OF FIGURES Figures No. Page 2.0 UP2 Educational Board Block Diagram. 8 2.1 Position of C1, C2 & C3 Connectors. 10 2.2 FLEX_EXPAN_A, FLEX_EXPAN_B & FLEX_EXPAN_C Numbering Convention. 15 2.3 Quartus II Design Flow. 19 2.4 Quartus II Graphical User Interface. 20 2.5 Compiler Tool Window. 21 3.0 Quartus II Software. 22 3.1 New Project Wizard popup window. 23 3.2 Directory, Name, Top-level Entity. 24 3.3 Family and device settings. 24 3.4 Summary. 25 3.5 Device design files. 25 3.6 Save as popup window. 26 3.7 Full compilation popup window message. 27 3.8 Simulator Tool popup window. 27 3.9 Simulator Tool window. 28 3.10 Top view of device pins. 29 X

3.11 Pin location. 29 3.12 Programmer setting. 30 3.13 Speaker, ByteBlaster II, Pluto Board and Capacitor. 30 3.14 Altera Education Board (UP2 Board). 31 3.15 Jumper Settings for Programming Only the EPM7128S Device. 3.16 Jumper Settings for Configuring Only the FLEX 10K Device. 32 34 4.0 Simulation waveform for 4-bits counter. 37 XI