Systems I. Optimizing for the Memory Hierarchy. Topics Impact of caches on performance Memory hierarchy considerations

Similar documents
CISC 360. Cache Memories Nov 25, 2008

Giving credit where credit is due

Cache Memories. EL2010 Organisasi dan Arsitektur Sistem Komputer Sekolah Teknik Elektro dan Informatika ITB 2010

Cache Memories October 8, 2007

Cache Memories. Cache Memories Oct. 10, Inserting an L1 Cache Between the CPU and Main Memory. General Org of a Cache Memory

Cache memories The course that gives CMU its Zip! Cache Memories Oct 11, General organization of a cache memory

ν Hold frequently accessed blocks of main memory 2 CISC 360, Fa09 Cache is an array of sets. Each set contains one or more lines.

Last class. Caches. Direct mapped

The course that gives CMU its Zip! Memory System Performance. March 22, 2001

Cache memories are small, fast SRAM based memories managed automatically in hardware.

Today Cache memory organization and operation Performance impact of caches

Cache Memories. Topics. Next time. Generic cache memory organization Direct mapped caches Set associative caches Impact of caches on performance

211: Computer Architecture Summer 2016

Memory Hierarchy. Announcement. Computer system model. Reference

Example. How are these parameters decided?

CS 33. Caches. CS33 Intro to Computer Systems XVIII 1 Copyright 2017 Thomas W. Doeppner. All rights reserved.

Denison University. Cache Memories. CS-281: Introduction to Computer Systems. Instructor: Thomas C. Bressoud

Computer Organization: A Programmer's Perspective

Agenda Cache memory organization and operation Chapter 6 Performance impact of caches Cache Memories

Carnegie Mellon. Cache Memories. Computer Architecture. Instructor: Norbert Lu1enberger. based on the book by Randy Bryant and Dave O Hallaron

Today. Cache Memories. General Cache Concept. General Cache Organization (S, E, B) Cache Memories. Example Memory Hierarchy Smaller, faster,

Memory Hierarchy. Jin-Soo Kim Computer Systems Laboratory Sungkyunkwan University

Cache Memories /18-213/15-513: Introduction to Computer Systems 12 th Lecture, October 5, Today s Instructor: Phil Gibbons

Carnegie Mellon. Cache Memories

Memory Hierarchy. Computer Systems Organization (Spring 2017) CSCI-UA 201, Section 3. Instructor: Joanna Klukowska

Memory Hierarchy. Cache Memory Organization and Access. General Cache Concept. Example Memory Hierarchy Smaller, faster,

Cache Memories. Andrew Case. Slides adapted from Jinyang Li, Randy Bryant and Dave O Hallaron

High-Performance Parallel Computing

Memory Hierarchy. Instructor: Adam C. Champion, Ph.D. CSE 2431: Introduction to Operating Systems Reading: Chap. 6, [CSAPP]

Lecture 12. Memory Design & Caches, part 2. Christos Kozyrakis Stanford University

Cache Memories : Introduc on to Computer Systems 12 th Lecture, October 6th, Instructor: Randy Bryant.

Cache Memories. Lecture, Oct. 30, Bryant and O Hallaron, Computer Systems: A Programmer s Perspective, Third Edition

Cache Memories. From Bryant and O Hallaron, Computer Systems. A Programmer s Perspective. Chapter 6.

CSCI-UA.0201 Computer Systems Organization Memory Hierarchy

211: Computer Architecture Summer 2016

Cache memories are small, fast SRAM-based memories managed automatically in hardware. Hold frequently accessed blocks of main memory

CSCI 402: Computer Architectures. Performance of Multilevel Cache

Roadmap. Java: Assembly language: OS: Machine code: Computer system:

Measurement tools and techniques

Memory Hierarchy & Caching. CS 351: Systems Programming Michael Saelee

EE108B Lecture 13. Caches Wrap Up Processes, Interrupts, and Exceptions. Christos Kozyrakis Stanford University

Lecture 15: Caches and Optimization Computer Architecture and Systems Programming ( )

Cache Performance II 1

Announcements. EE108B Lecture 13. Caches Wrap Up Processes, Interrupts, and Exceptions. Measuring Performance. Memory Performance

Systems Programming and Computer Architecture ( ) Timothy Roscoe

write-through v. write-back write-through v. write-back write-through v. write-back option 1: write-through write 10 to 0xABCD CPU RAM Cache ABCD: FF

A Crash Course in Compilers for Parallel Computing. Mary Hall Fall, L2: Transforms, Reuse, Locality

CS 261 Fall Caching. Mike Lam, Professor. (get it??)

Cache Memory and Performance

Introduction to Computer Systems: Semester 1 Computer Architecture

Computer Organization - Overview

Caches III. CSE 351 Spring Instructor: Ruth Anderson

Lecture 17: Memory Hierarchy and Cache Coherence Concurrent and Mul7core Programming

CS 240 Stage 3 Abstractions for Practical Systems

Cache Impact on Program Performance. T. Yang. UCSB CS240A. 2017

SE-292 High Performance Computing. Memory Hierarchy. R. Govindarajan Memory Hierarchy

CS3350B Computer Architecture

Kathryn Chan, Kevin Bi, Ryan Wong, Waylon Huang, Xinyu Sui

CS429: Computer Organization and Architecture

Caches III. CSE 351 Winter Instructor: Mark Wyse

Introduction to Computer Systems

Introduction to Computer Systems

Memories. CPE480/CS480/EE480, Spring Hank Dietz.

Lecture 16 Optimizing for the memory hierarchy

Advanced Caching Techniques

Advanced Caching Techniques

Caches Concepts Review

Problem: Processor Memory BoJleneck

CS377P Programming for Performance Single Thread Performance Caches I

Lecture 18. Optimizing for the memory hierarchy

Performance Optimization Tutorial. Labs

Parallel Processing. Parallel Processing. 4 Optimization Techniques WS 2018/19

CS241 Computer Organization Spring Principle of Locality

Matrix Multiplication

L2 cache provides additional on-chip caching space. L2 cache captures misses from L1 cache. Summary

Advanced Architecture

CS429: Computer Organization and Architecture

Cache Memory: Instruction Cache, HW/SW Interaction. Admin

Lecture 2. Memory locality optimizations Address space organization

Problem: Processor- Memory Bo<leneck

DECstation 5000 Miss Rates. Cache Performance Measures. Example. Cache Performance Improvements. Types of Cache Misses. Cache Performance Equations

Caches Spring 2016 May 4: Caches 1

Copyright 2012, Elsevier Inc. All rights reserved.

Types of Cache Misses. The Hardware/So<ware Interface CSE351 Winter Cache Read. General Cache OrganizaJon (S, E, B) Memory and Caches II

The Hardware/So<ware Interface CSE351 Winter 2013

Essential constraints: Data Dependences. S1: a = b + c S2: d = a * 2 S3: a = c + 2 S4: e = d + c + 2

The Memory Hierarchy. Fall Instructors: Aykut & Erkut Erdem

CS/ECE 250 Computer Architecture

Parallelizing The Matrix Multiplication. 6/10/2013 LONI Parallel Programming Workshop

Random-Access Memory (RAM) CISC 360. The Memory Hierarchy Nov 24, Conventional DRAM Organization. SRAM vs DRAM Summary.

CS422 Computer Architecture

Matrix Multiplication

Announcements. ! Previous lecture. Caches. Inf3 Computer Architecture

Program Transformations for the Memory Hierarchy

Question 13 1: (Solution, p 4) Describe the inputs and outputs of a (1-way) demultiplexer, and how they relate.

How to Write Fast Numerical Code

+ Random-Access Memory (RAM)

Memory Cache. Memory Locality. Cache Organization -- Overview L1 Data Cache

Agenda. Cache-Memory Consistency? (1/2) 7/14/2011. New-School Machine Structures (It s a bit more complicated!)

Cache Performance! ! Memory system and processor performance:! ! Improving memory hierarchy performance:! CPU time = IC x CPI x Clock time

Transcription:

Systems I Optimizing for the Memory Hierarchy Topics Impact of caches on performance Memory hierarchy considerations

Cache Performance Metrics Miss Rate Fraction of memory references not found in cache (misses/references) Typical numbers: 3-10% for L1 can be quite small (e.g., < 1%) for L2, depending on size, etc. Hit Time Time to deliver a line in the cache to the processor (includes time to determine whether the line is in the cache) Typical numbers: 1-3 clock cycle for L1 5-12 clock cycles for L2 Miss Penalty Additional time required because of a miss Typically 100-300 cycles for main memory 2

Writing Cache Friendly Code Repeated references to variables are good (temporal locality) Stride-1 reference patterns are good (spatial locality) Examples: cold cache, 4-byte words, 4-word cache blocks int sumarrayrows(int a[m][n]) { int i, j, sum = 0; int sumarraycols(int a[m][n]) { int i, j, sum = 0; for (i = 0; i < M; i++) for (j = 0; j < N; j++) sum += a[i][j]; return sum; for (j = 0; j < N; j++) for (i = 0; i < M; i++) sum += a[i][j]; return sum; Miss rate = 1/4 = 25% Miss rate = 100% 3

The Memory Mountain Empirical studies of memory system behavior Read throughput (read bandwidth) Number of bytes read from memory per second (MB/s) Memory mountain Measured read throughput as a function of spatial and temporal locality. Compact way to characterize memory system performance. 4

Memory Mountain Test Function /* The test function */ void test(int elems, int stride) { int i, result = 0; volatile int sink; for (i = 0; i < elems; i += stride) result += data[i]; sink = result; /* So compiler doesn't optimize away the loop */ /* Run test(elems, stride) and return read throughput (MB/s) */ double run(int size, int stride, double Mhz) { double cycles; int elems = size / sizeof(int); test(elems, stride); /* warm up the cache */ cycles = fcyc2(test, elems, stride, 0); /* call test(elems,stride) */ return (size / stride) / (cycles / Mhz); /* convert cycles to MB/s */ 5

Memory Mountain Main Routine /* mountain.c - Generate the memory mountain. */ #define MINBYTES (1 << 10) /* Working set size ranges from 1 KB */ #define MAXBYTES (1 << 23) /*... up to 8 MB */ #define MAXSTRIDE 16 /* Strides range from 1 to 16 */ #define MAXELEMS MAXBYTES/sizeof(int) int data[maxelems]; /* The array we'll be traversing */ int main() { int size; /* Working set size (in bytes) */ int stride; /* Stride (in array elements) */ double Mhz; /* Clock frequency */ init_data(data, MAXELEMS); /* Initialize each element in data to 1 */ Mhz = mhz(0); /* Estimate the clock frequency */ for (size = MAXBYTES; size >= MINBYTES; size >>= 1) { for (stride = 1; stride <= MAXSTRIDE; stride++) printf("%.1f\t", run(size, stride, Mhz)); printf("\n"); exit(0); 6

The Memory Mountain read throughput (MB/s) Slopes of Spatial Locality 1200 1000 800 600 400 200 xe L2 L1 Pentium III Xeon 550 MHz 16 KB on-chip L1 d-cache 16 KB on-chip L1 i-cache 512 KB off-chip unified L2 cache Ridges of Temporal Locality 0 s1 s3 s5 mem 8k 2k stride (words) s7 s9 s11 s13 s15 8m 2m 512k 128k 32k working set size (bytes) 7

Ridges of Temporal Locality Slice through the memory mountain with stride=1 illuminates read throughputs of different caches and memory 1200 1000 main memory region L2 cache region L1 cache region 800 600 400 200 0 8m 4m 2m 1024k 512k 256k 128k 64k 32k 16k 8k 4k 2k 1k read througput (MB/s) working set size (bytes) 8

A Slope of Spatial Locality Slice through memory mountain with size=256kb shows cache block size. 800 700 600 read throughput (MB/s) 500 400 300 200 one access per cache line 100 0 s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 s12 s13 s14 s15 s16 stride (words) 9

Matrix Multiplication Example Major Cache Effects to Consider Total cache size Exploit temporal locality and keep the working set small (e.g., by using blocking) /* ijk */ Variable sum Block size for (i=0; i<n; i++) { held in register Exploit spatial locality for (j=0; j<n; j++) { sum = 0.0; for (k=0; k<n; k++) sum += a[i][k] * b[k][j]; Multiply N x N matrices c[i][j] = sum; Description: O(N 3 ) total operations Accesses N reads per source element N values summed per destination» but may be able to hold in register 10

Miss Rate Analysis for Matrix Multiply Assume: Line size = 32B (big enough for 4 64-bit words) Matrix dimension (N) is very large Approximate 1/N as 0.0 Cache is not even big enough to hold multiple rows Analysis Method: Look at access pattern of inner loop k j j i k i A B C 11

Layout of C Arrays in Memory (review) C arrays allocated in row-major order each row in contiguous memory locations Stepping through columns in one row: for (i = 0; i < N; i++) sum += a[0][i]; accesses successive elements if block size (B) > 4 bytes, exploit spatial locality compulsory miss rate = 4 bytes / B Stepping through rows in one column: for (i = 0; i < n; i++) sum += a[i][0]; accesses distant elements no spatial locality! compulsory miss rate = 1 (i.e. 100%) 12

Matrix Multiplication (ijk) /* ijk */ for (i=0; i<n; i++) { for (j=0; j<n; j++) { sum = 0.0; for (k=0; k<n; k++) sum += a[i][k] * b[k][j]; c[i][j] = sum; Inner loop: (i,*) (*,j) (i,j) Row-wise Columnwise Fixed Misses per Inner Loop Iteration: 0.25 1.0 0.0 13

Matrix Multiplication (jik) /* jik */ for (j=0; j<n; j++) { for (i=0; i<n; i++) { sum = 0.0; for (k=0; k<n; k++) sum += a[i][k] * b[k][j]; c[i][j] = sum Misses per Inner Loop Iteration: 0.25 1.0 0.0 Inner loop: (i,*) (*,j) (i,j) Row-wise Columnwise Fixed 14

Matrix Multiplication (kij) /* kij */ for (k=0; k<n; k++) { for (i=0; i<n; i++) { r = a[i][k]; for (j=0; j<n; j++) c[i][j] += r * b[k][j]; Inner loop: (i,k) (k,*) (i,*) Fixed Row-wise Row-wise Misses per Inner Loop Iteration: 0.0 0.25 0.25 15

Matrix Multiplication (ikj) /* ikj */ for (i=0; i<n; i++) { for (k=0; k<n; k++) { r = a[i][k]; for (j=0; j<n; j++) c[i][j] += r * b[k][j]; Inner loop: (i,k) (k,*) (i,*) Fixed Row-wise Row-wise Misses per Inner Loop Iteration: 0.0 0.25 0.25 16

Matrix Multiplication (jki) /* jki */ for (j=0; j<n; j++) { for (k=0; k<n; k++) { r = b[k][j]; for (i=0; i<n; i++) c[i][j] += a[i][k] * r; Inner loop: (*,k) (*,j) (k,j) Misses per Inner Loop Iteration: 1.0 0.0 1.0 Column - wise Fixed Columnwise 17

Matrix Multiplication (kji) /* kji */ for (k=0; k<n; k++) { for (j=0; j<n; j++) { r = b[k][j]; for (i=0; i<n; i++) c[i][j] += a[i][k] * r; Misses per Inner Loop Iteration: 1.0 0.0 1.0 Inner loop: (*,k) (k,j) (*,j) Fixed Columnwise Columnwise 18

Summary of Matrix Multiplication ijk (& jik): 2 loads, 0 stores misses/iter = 1.25 kij (& ikj): 2 loads, 1 store misses/iter = 0.5 jki (& kji): 2 loads, 1 store misses/iter = 2.0 for (i=0; i<n; i++) { for (j=0; j<n; j++) { sum = 0.0; for (k=0; k<n; k++) sum += a[i][k] * b[k][j]; c[i][j] = sum; for (k=0; k<n; k++) { for (i=0; i<n; i++) { r = a[i][k]; for (j=0; j<n; j++) c[i][j] += r * b[k][j]; for (j=0; j<n; j++) { for (k=0; k<n; k++) { r = b[k][j]; for (i=0; i<n; i++) c[i][j] += a[i][k] * r; 19

Pentium Matrix Multiply Performance Miss rates are helpful but not perfect predictors. Code scheduling matters, too. 60 50 Cycles/iteration 40 30 20 kji jki kij ikj jik ijk 10 0 25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400 Array size (n) 20

Improving Temporal Locality by Blocking Example: Blocked matrix multiplication block (in this context) does not mean cache block. Instead, it mean a sub-block within the matrix. Example: N = 8; sub-block size = 4 A 11 A 12 A 21 A 22 X B 11 B 12 B 21 B 22 = C 11 C 12 C 21 C 22 Key idea: Sub-blocks (i.e., A xy ) can be treated just like scalars. C 11 = A 11 B 11 + A 12 B 21 C 12 = A 11 B 12 + A 12 B 22 C 21 = A 21 B 11 + A 22 B 21 C 22 = A 21 B 12 + A 22 B 22 21

Blocked Matrix Multiply (bijk) for (jj=0; jj<n; jj+=bsize) { for (i=0; i<n; i++) for (j=jj; j < min(jj+bsize,n); j++) c[i][j] = 0.0; for (kk=0; kk<n; kk+=bsize) { for (i=0; i<n; i++) { for (j=jj; j < min(jj+bsize,n); j++) { sum = 0.0 for (k=kk; k < min(kk+bsize,n); k++) { sum += a[i][k] * b[k][j]; c[i][j] += sum; 22

Blocked Matrix Multiply Analysis Innermost loop pair multiplies a 1 X bsize sliver of A by a bsize X bsize block of B and accumulates into 1 X bsize sliver of C Loop over i steps through n row slivers of A & C, using same B for (i=0; i<n; i++) { for (j=jj; j < min(jj+bsize,n); j++) { sum = 0.0 for (k=kk; k < min(kk+bsize,n); k++) { sum += a[i][k] * b[k][j]; Innermost c[i][j] += sum; Loop Pair kk jj jj i kk i row sliver accessed bsize times block reused n times in succession Update successive elements of sliver 23

Pentium Blocked Matrix Multiply Performance Blocking (bijk( and bikj) ) improves performance by a factor of two over unblocked versions (ijk( and jik) relatively insensitive to array size. 60 50 Cycles/iteration 40 30 20 10 0 25 50 75 100 125 150 175 200 Array size (n) 225 250 275 300 325 350 375 400 kji jki kij ikj jik ijk bijk (bsize = 25) bikj (bsize = 25) 24

Concluding Observations Programmer can optimize for cache performance How data structures are organized How data are accessed Nested loop structure Blocking is a general technique All systems favor cache friendly code Getting absolute optimum performance is very platform specific Cache sizes, line sizes, associativities, etc. Can get most of the advantage with generic code Keep working set reasonably small (temporal locality) Use small strides (spatial locality) 25