DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING QUESTION BANK SUBJECT : CS6303 / COMPUTER ARCHITECTURE SEM / YEAR : VI / III year B.E. Unit I OVERVIEW AND INSTRUCTIONS Part A Q.No Questions BT Level Domain 1. Define Amdahl s law. BTL 1 Remembering 2. Identify general characteristics of Relative addressing mode with an example. 3. Discuss the eight great ideas in computer architecture. BTL 2 Understanding 4. List the five classic components of a computer. BTL 1 Remembering 5. How would you summarize the function of data path and control BTL 2 Understanding path? 6. How do you interpret the instruction set Architecture? BTL 2 Understanding 7. Differentiate DRAM and SRAM. 8. Compare and contrast volatile and nonvolatile memory. BTL 2 Understanding 9. Define VLSI. BTL 1 Remembering 10. What facts would you select to show throughput and response time? BTL 3 Applying 11. Can you elaborate the CPU performance equation? BTL 5 Evaluating 12. If computer A runs a program in 10 seconds, and computer B runs BTL 5 Evaluating the same program in 15 seconds, how much faster is A over B? Justify your answer. 13. Construct the formula for CPU execution time for a program. BTL 6 Creating 14. List the data transfer instructions. BTL 1 Remembering 15. Build the formula for CPU clock cycles required for a program. BTL 3 Applying 16. Define Stored Program Concept. BTL 1 Remembering 17. What are the fields in an MIPS instruction? BTL 1 Remembering
18. Can you make a distinction between multiprocessor over uniprocessor? 19. What examples can you give to relative and indirect addressing mode? 20. Consider the following performance measurements for a program Measurement Computer A Computer B Instruction 10 billion 8 billion Count Clock rate 4GHz 4GHz CPI 1.0 1.1 Which computer has the higher MIPS rating? BTL 3 BTL 6 Applying Creating Part B 1.(i) Summarize the eight great ideas of computer Architecture.(8) BTL 5 Evaluating (ii) Describe the technologies for Building Processors and Memory. (8) BTL 2 Understanding 2. List the various components of computer system with neat diagram. BTL 1 Remembering 3. Define addressing mode. Describe the basic addressing modes with an BTL 1 Remembering example for each. 4. What are the operations and operands of computer Hardware? Explain BTL 1 Remembering in detail. 5. Discuss the logical operations and control operations of computer.(8) Explain the concept of Powerwall processor. (8) BTL 2 BTL 5 Understanding Evaluating 6. Consider three different processors P1, P2, and P3 executing the same instruction set. P1 has a 3 GHz clock rate and a CPI of 1.5. P2 has a 2.5 GHz clock rate and a CPI of 1.0. P3 has a 4.0 GHz clock rate and has a CPI of 2.2. a) Which processor has the highest performance expressed in instructions per second? b) If the processors each execute a program in 10 seconds, find the number of cycles and the number of instructions? c) We are trying to reduce the execution time by 30% but this leads to an increase of 20% in the CPI. What clock rate should we have to get this time reduction? 7. Assume a program requires the execution of 50 106 FP BTL 3 Applying istructions,110 106 INT instructions, 80 106 L/S instructions, and 16 106 branch instructions The CPI for each type of instruction is 1, 1, 4, and 2, respectively. Assume that the processor has a 2 GHz clock rate. a) By how much must we improve the CPI of FP instructions if we want the program to run two times faster? b) By how much must we improve the CPI of L/S instructions if we want the program to run two times faster? c) By how much is the execution time of the program improved if the CPI of INT and FP Instructions are reduced by 40% and the CPI of L/S and Branch is reduced by 30%? 8. Describe the branching operations with suitable example. BTL 2 Understanding 9. How would you formulate the performance of CPU and compose the BTL 6 Creating
10.(i) factors that affect performance? Assume a two address format specified as source, destination. Examine the following sequence of instructions and identy the addressing modes used and the operation done in every instruction (1) Move (R5)+, R0 (2) Add(R5)+, R0 (3) Move R0, (R5) (4) Move 16(R5),R3 (5) Add #40, R5 BTL 3 Applying (ii) Consider the computer with three instruction classes and CPI measurements as given below and instruction counts for each instruction class for the same program from two different compilers are given. Assume that the computer s clock rate is 1GHZ which code sequence will execute faster according to execution time? Code from CPI for the instruction class A B C CPI 1 2 3 Code from CPI for the instruction class A B C Compiler1 2 1 2 Compiler2 2 1 1 UNIT II ARITHMETIC OPERATIONS PART A Q.No Questions BT Level Competence 1. Add 510 to 610 in binary and Subtract -610 from 710 in binary ) 2. How would you examine the overflow conditions for addition and BTL 3 Applying subtraction? 3. Construct the Multiplication hardware diagram. BTL 3 Applying 4. List the steps of multiplication algorithm. BTL 1 Remembering 5. What is fast multiplication? BTL 1 Remembering 6. List the steps of division algorithm. BTL 1 Remembering 7. Illustrate scientific notation and normalization with example. BTL 3 Applying 8. What approach would you use to interpret single precision floating point number? BTL 2 Understanding 9. Contrast overflow and underflow with examples. BTL 2 Understanding 10. Give the representation of double precision floating point number. BTL 2 Understanding 11. What are the floating point instructions in MIPS? BTL 1 Remembering 12. Can you formulate the steps of floating point addition? BTL 6 Creating 13. Evaluate the sequence of floating point multiplication. BTL 5 Evaluating
14. Define Guard and Round bit. BTL 1 Remembering 15. Write the IEEE 754 floating point format. BTL 2 Understanding 16. What is meant by sub-word parallelism? BTL 1 Remembering 17. Multiply 100011 * 100010. 18. Divide 1,001,010 by 1000. 19. For the following C statement, what is the corresponding MIPS BTL 6 Creating assembly code? f = g + (h 5) 20. For the following MIPS assembly instructions above, what is a BTL 5 Evaluating corresponding C statement? add f, g, h add f, i, f PART B 1. Discuss the multiplication algorithm in detail with diagram and BTL 2 Understanding examples. 2. How would you describ the division algorithm with diagram? BTL 1 Remembering 3. How floating point addition is carried out in a computer system? Give BTL 1 Remembering an example for a binary floating point addition. 4. Summarize in detail the floating point multiplication algorithm. BTL 2 Understanding 5. How would you solve the multiplication of signed 2 s complement numbers? Give algorithm and example BTL 3 Applying 6. Assume A and B for a pair of signed 2 s complement numbers with values : A = 010111, B = 101100. Develop algorithm to implement A*B. 7. 8. 9. How would you estimate the result of the numbers 0.5 10 +( - 0.4375 10) using binary Floating point Addition algorithm? Multiply 1.10 10 X 10 10 and 9.200X10-5 using binary Floating point multiplication. Calculate the division of A and B A=3.264 X 10 3 and B= 6.52 X 10 2 10. Tabulate the IEEE 754 binary representation of the number - 0.75 10 in single and double precision. BTL 6 BTL 5 BTL 1 Creating Evaluating Remembering UNIT III PROCESSOR AND CONTROL UNIT PART A Q.No Questions BT Competence Level 1. What is meant by data path element? BTL 2 Understanding 2. Summarize the use of PC register. BTL 2 Understanding 3. Define register file. BTL 1 Remembering
4. List the state elements needed to store and access an instruction. BTL 1 Remembering 5. Draw the diagram of portion of datapath used for fetching instruction. BTL 2 Understanding 6. Compare Sign Extend and Vector interupts. BTL 2 Understanding 7. What is meant by branch target address? BTL 1 Remembering 8. How would you evaluate branch taken and branch not taken in BTL 5 Evaluating instruction execution? 9. How would you examine delayed branching? BTL 1 Remembering 10. Design the instruction format for the jump instruction. BTL 6 Creating 11. Classify the different types of hazards with examples. 12. How would you apply data forwarding to avoid data hazards? BTL 3 Applying 13. How could you determine the pipeline stall? BTL 5 Evaluating 14. What is meant by branch prediction? BTL 1 Remembering 15. Construct the 5 stages pipeline. BTL 3 Applying 16. What motive is there in using exceptions and interrupts? 17. What is pipelining? BTL 1 Remembering 18. Illustrate the five steps used in MIPS instruction execution. BTL 3 Applying 19. Classify the types of instruction classes and their instruction formats. 20. Formulate the calculating time between instructions in a pipelined processor. BTL6 Creating PART B 1. Discuss the basic MIPS implementation of instruction set. BTL 2 Understanding 2. Describe MIPS implementation with necessary multiplexers and BTL 1 Remembering control lines. 3. What are control hazards? Describe the methods for dealing with the BTL 1 Remembering control hazards. 4. Design and develop an instruction pipeline working under various situations of pipeline stall. BTL 6 Creating 5. What is data hazard? How do you overcome it? What are its side BTL 1 Remembering effects? 6. Compare the data and control path methods in pipelining. BTL 2 Understanding 7. (i)can you make the distinction between sequential execution and BTL pipelining?(8) 4&3 Applying (ii)construct the model for building a datapath. (8) 8. Recommend the techniques for dynamic branch prediction. BTL 5 Evaluating 9. Examine the approaches would you use to handle exceptions in MIPS. BTL 3 Applying 10. What motive is there in using control path implementation in pipelining? UNIT IV PARALLELISM PART A Q.No Questions BT Competence Level 1. What is the main idea of ILP? BTL 2 Understanding
2. What approach would you use to organize a multiple issue processor? BTL 3 Applying 3. Can you list the three important properties of vector instructions? BTL 1 Remembering 4. List the main characteristics of SMT processor. 5. What inference can you make from loop unrolling technique? BTL1 Remembering 6. Define VLIW processor. BTL1 Remembering 7. What is meant by anti-dependence? How is it removed? BTL 2 Understanding 8. How would you examine the efficiency of superscalar processor? BTL 1 Remembering 9. Will you state the need of speculation? BTL 2 Understanding 10. Show the performance of cluster organization. BTL 3 Applying 11. What is the relationship between SMT and hardware multithreading? BTL 5 Evaluating 12. Define the Flynn classification. BTL 1 Remembering 13. How do you integrate the ideas of in-order execution and out-of-order BTL 6 Creating execution? 14. Can you make the distinction between UMA and NUMA? BTL 5 Evaluating 15. Identify the use of hardware in multithreading option. BTL 1 Remembering 16. What can you say about sub-word parallelism? BTL 2 Understanding 17. How would you formulate the various approaches to hardware BTL 6 Creating multithreading? 18. Categorize the various multithreading options. 19. What ideas justify a multicore processor? 20. What approaches would you use to improve performance of a BTL 3 Applying processor? PART B 1. List the main characteristics of Instruction level parallelism. BTL 1 Remembering 2. What are the facts or challenges faced by parallel processing BTL 2 Understanding programs? Summarize. 3. What is the main idea of using message passing in multiprocessor? BTL 2 Understanding 4. How would you show your understanding of using hardware in BTL 3 Applying multithreading? 5. Describe data level parallelism in SIMD and MISD machine. BTL 1 Remembering 6. a) How would you use shared memory concept in multi-processor?(8) BTL Applying b)compare and contrast Fine grained and Coarse grained 3&4 multithreading.(8) 7. What are the features of Multicore processors? BTL 5 Evaluating 8. How would you classify the types of multithreading? 9. How would you formulate the ideas of Flynn s classification? BTL 6 Creating 10. a) Define vector processor. b) Describe SPMD processor. BTL 1 Remembering
UNIT V MEMORY AND I/O SYSTEM PART A Q.No Questions BT Level Competence 1. Distinguish the types of locality of references. BTL 2 Understanding 2. Define the structure of memory hierarchy. BTL 1 Remembering 3. How would you summarize the various memory technologies? BTL 2 Understanding 4. Compare and contrast SRAM and DRAM. 5. What is flash memory? BTL 1 Remembering 6. Define Rotational Latency. BTL 1 Remembering 7. What is direct-mapped cache? BTL 1 Remembering 8. Evaluate the following instance wherein the cache size is 64 blocks BTL 5 Evaluating and block size is 16 bytes. What block number does byte address 1200 map? 9. How many total bits are required for a direct-mapped cache BTL 6 Creating with 16 KB of data and 4-word blocks, assuming a 32-bit address? 10. How would you analyze the writing strategies in cache memory? 11. What are the functional steps required in an instruction cache miss? BTL 6 Creating 12. Define hit rate and miss rate. BTL 1 Remembering 13. Summarize the various block placement schemes in cache memory. BTL 2 Understanding 14. Define Mean Time to Failure rate. BTL 1 Remembering 15. Compare the three ways to improve MTTF. 16. How would you show your understanding of the role of TLB in BTL 3 Applying virtual memory? 17. Can you make use of virtual memory concept in memory BTL 3 Applying management? 18. What is the relationship between physical address and logical BTL 5 Evaluating address? 19. What is main idea of address mapping? BTL 2 Understanding 20. How would you use interrupts in cases of exceptions? BTL 3 Applying PART B 1. List the various memory technologies and examine its relevance in architecture design. BTL 1 Remembering 2. Describe in detail the memory hierarchy with neat diagram. BTL 1 Remembering 3. Summarize the basic operations of cache in detail with diagram. BTL 2 Understanding 4. Distinguish the various mapping schemes used in cache design. BTL 2 Understanding 5. a) A byte addressable computer has a small data cache capable of holding eight 32-bit words. Each cache block contains 132-bit word. When a given program is executed, the processor reads data from the following sequence of hex addresses 200, 204, 208, 20C, 2F4, 2F0, 200,204,218, 21C, 24C, 2F4. The pattern is repeated four times. Assuming that the cache is initially empty, show the contents of the cache at the end of each pass, and compute the hit rate for a direct mapped cache. (8) BTL 3 Applying
b) What are the methods used to measure and improve the performance of the cache. (8) 6. Describe the virtual memory address translation and TLB with BTL 1 Remembering necessary diagram. 7. How would you demonstrate the DMA controller for data transfer BTL 3 Applying between memory and peripherals? 8. Can you summarize the concept of interrupts with neat diagrams? BTL 5 Evaluating 9. What choice in design would you have made for standard input and output interfaces required to connect the I/O device to the bus? BTL 6 Creating 10. How would you classify the bus arbitration techniques in DMA?