i-1 PrimeTime: Introduction to Static Timing Analysis Workshop Synopsys Customer Education Services 2002 Synopsys, Inc. All Rights Reserved PrimeTime: Introduction to Static 34000-000-S16 Timing Analysis i-1 Unit i:
First Things First i-2 and Introductions Materials you should have: 10 Student Guide 10 Lab Guide 10 PrimeTime Quick Reference 10 Synopsys Online Documentation (SOLD) CD Breaks Facilities i-2 Unit i:
Workshop Goal i-3 Use PrimeTime to to perform Static Timing Analysis (STA) on on a Functional Core prior to to Place and Route (P&R). Obtain the prerequisite knowledge to to attend the PrimeTime: Chip STA workshop. A/D DSP CODEC Processor_CORE USB RAM MPEG Functional Core Core Clock Assumptions: 1. STA is performed on the Functional core only; level STA has been done in DC. (See Flow Diagram) 2. No scan chains yet (Flow diagram in PT:Chip level STA workshop) 3. Functional Core routing parasitic RCs (detailed SPEF) and sub block WLMs are available from early design planning (Chip level floor plan) 4. No clock tree synthesis yet (Flow diagram in PT:Chip level STA workshop) 5. s may be either synthesized netlist or QTMs (will be covered if class time permits) 6. Functional Core has Logical hierarchical partitions (blocks) 7. No I/O pads, no BSD, no clock generation logic yet (Definition of Functional Core) 8. Chip specification is available (in Constraints modules) 9. Multiple Synch/Asynch clocks (in Constraints modules) 10. Multicycle paths (in Constraints modules) 11. Hold Time analysis is performed using Worst case PVT (as opposed to Best case PVT) (in Constraints modules) 12. No case analysis (absence of scan chains); no functional modes (Flow diagram in PT:Chip level STA workshop -- although it may apply to Functional CORE but is not discussed in this PT: ISTA) i-3 Unit i:
Workshop Target Audience i-4 or Verification engineers who perform STA at the functional core level Little or no formal experience with PrimeTime Little or no formal experience with Compiler Planning to take the PrimeTime: Chip level STA workshop You are here PrimeTime: ISTA PrimeTime: CHIP CHIP Synthesis ( Compiler) or Verification engineers who perform STA at the functional core level. In addition to block level STA, you will handle functional core integration. Little or no formal experience with Compiler. If you have taken CHIP Synthesis or have experience using Compiler, do not attend this workshop: Take PrimeTime: Chip STA If your expectation is to learn DC as you re expanding your portfolio to include synthesis, you should take the CHIP Synthesis workshop next and then PrimeTime: Chip STA. PT:Chip STA Workshop focuses on final, full chip, post route STA in order to achieve Timing closure. i-4 Unit i:
What is Functional Core on a CHIP? i-5 TOP CLOCK-GEN PLL MID FUNC_CORE JTAG/BSD Logic Synthesized 1(wlm) Synthesized 2 ASYNCH LOGIC Synthesized 3 RAM (Timing model) Functional CORE constitutes most of the CHIP containing: 10 10 10 Synthesized logic blocks (Gate level netlist) and Models (RAMs) Functional core constraints are derived from Chip-level constraints Functional core level parasitics are extracted ❽ Extraction is done after a CHIP level floorplan and global routing Parasitics are supplied in SPEF (Standard Parasitic Extraction Format). At the full-chip level one must consider the following issues: Model clock generation circuitry Analyze latch-based versus flip-flop design styles Functional vs. Test modes (Case analysis) Analyze PVT corners These issues are addressed in the PrimeTime: Chip level STA workshop. i-5 Unit i:
Functional Core Integration Pre-Layout i-6 Fully synthesized Functional Core. Chip- floorplan and constraints. Functional core interblock RC parasitics extracted. Units 4-6 Fix data Unit 3 yes Write Top- constraints and exceptions Read required files Errors/ Warnings? no Compiler Resynthesis Units 1,8 Generate STA Reports Timing violations Place&Route After synthesis of all sub-blocks, perform Chip level floorplan, global routing and extract the parasitic RCs between blocks within the Functional core. QTMs (or Timing models) may be used for the blocks for which synthesized gate level netlist is not available. Day-1: Objective: Using the basic 5 step STA flow, constrain all the Register to Register (Internal) timing paths within the functional core Day-2: Objectives:Using the 5 step STA flow, constrain all the I/O (interface) timing paths within the functional core and apply the necessary single clock cycle timing exceptions i-6 Unit i:
PT Compatibility with other Tools i-7 Compiler Physical Compiler Mapped netlist (using WLM) Placed netlist PrimeTime CHIP Architect STAMP Parasitics, SDF PathMill 3 rd Party Layout i-7 Unit i:
What Will Be Covered i-8 Performing basic 5 step Static Timing Analysis (STA) flow on a functional core prior to P&R using PrimeTime GUI and shell (Units 1-3) Applying required constraints and exceptions and checking for missing constraints and ignored exceptions (Units 4-6) Creating a Quick Timing Model (Unit 7) Analyzing in detail for timing, design rules and timing bottlenecks (Unit 8) i-8 Unit i:
Workshop Prerequisites i-9 Understanding of digital IC design Familiarity with UNIX, X-Windows and Unix-based text editor i-9 Unit i:
Agenda: Day One i-10 DAY 1 Unit Register to Register Paths Lab 0i 1 Introduction to Static Timing Analysis 2 Writing Basic Tcl Constructs in PT 3 Reading Data 4 Constraining Internal Reg-Reg Paths Unit 1 Objective: Is to introduce Static Timing Analysis in PrimeTime by: Defining the 2 steps performed by a Static Timing Analyzer; Understanding under the hood calculation of cell and net delays based on NLDM (Non-Linear Delay Model) and WLM (Wire Load Model); Listing 4 types of timing paths; Identifying the path with the WNS (worst negative slack) or longest delay using the report_timing command; Interpreting results of the report_delay_calculation command and for cell and net timing arcs and Finding specific topics in SOLD using key word search. Unit 2 Objective: Is to find Tcl syntax errors using the Tcl Syntax checker, to fix these errors and to obtain command and variable syntax information. Unit 3 Objective: Is to create a basic PT setup file, read all the required files for STA and resolve errors and warnings associated with reading the files. Unit 4 Objective: Is to create a Tcl script, which fully constrains internal Register-to-Register paths by Applying clock constraints and design environmental attributes; Modeling multiple synchronous/asynchronous clocks, Modeling pre-layout non ideal clocks, Invoking appropriate report commands to verify the correctness of constraints and Invoking a report to verify the completeness of constraints. i-10 Unit i:
Agenda: Day Two i-11 DAY 2 Unit I/O Paths and Exceptions Lab 5 Constraining I/O Interface Paths 6 Specifying Timing Exceptions 7 Introduction to Timing Models (QTM) 8 Performing STA 9 Summary 10 Customer Support Unit 5 Objective: Is to create a Tcl script which fully constrains the Input/Output interface paths by applying port constraints and environmental attributes, modeling I/O data paths between multiple synchronous and asynchronous clock domains, modeling pre-layout non ideal clock effects, Invoking appropriate report commands to verify the correctness of constraints, Invoking a report to ensure the completeness of constraints and Identifying the effect of constraints on the path reported by a timing report. Unit 6 Objective: Is to Efficiently constrain a design for non-single-clock cycle behavior by Defining Timing exceptions, Modeling multi cycle path, Modeling logically false paths, Writing efficient constraints to model the above and Identifying any ignored exceptions and remove them. Unit 7 Objective: Is to Create a Quick Timing model using a given specification for use in PT by Defining what QTM is, Writing a QTM script to create a QTM library cell for the given specification and Modifying the link_path to use the QTM just created. Unit 8 Objective: Is to Apply three techniques in a systematic approach to analyze timing and design rule violations by Listing the 3 techniques in the appropriate order, Obtaining summary reports of all constraint violations and determining the next course of action, Identifying timing bottleneck blocks for re-synthesis. Enabling generation of Divide and conquer Timing reports to investigate what types of timing paths are causing violations (group_path) and Generating timing reports for setup check, hold check and showing the fanout, capacitance and transition time along the path. Unit 9 Objective: Is to list ways to improve the runtime and memory when using the STA flow in PT and summarize the workshop. Unit 10 Objective: Is to introduce you to our Customer Support Services. i-11 Unit i:
Test For Understanding i-12 In this class, what are the 2 types of blocks which you assume are contained within the floor-planned Functional Core? In this class, how are the net parasitics (RC values) within Functional Core modeled prior to Place and Route? Nets within a block Nets between blocks After attending this class, you will be able to perform Static Timing Analysis on: (Circle all that apply) a. (Module) level design that is either a mapped netlist or a timing model b. Functional CORE level design containing synthesized gate level blocks c. Functional CORE level design with some blocks described as an RTL verilog/vhdl file d. CHIP level design that has been placed and routed (P&R) i-12 Unit i:
Abbreviations and Acronyms i-13 Acronym Meaning Acronym Meaning STA STA PVT PVT DC DC WLM WLM PT PT WNS WNS GUI GUI SPEF SPEF Tcl Tcl DRC DRC SOLD SOLD NLDM NLDM QTM QTM - - i-13 Unit i:
Appendix i-14 Icons used in this workshop Conventions used in this workshop The Synopsys Physical Synthesis Hierarchical Flow i-14 Unit i:
Icons Used in This Workshop (1/2) i-15 Lab Exercise Group Exercise Recommendation Acronyms For further reference i-15 Unit i:
Icons Used in This Workshop (2/2) i-16 Question Remember Checklist Caution Hint, Tip or Suggestion Note i-16 Unit i:
Conventions Used in this Workshop i-17 Convention Courier Courier italic Courier bold [ ] Indicates command syntax. Description Indicates a user-defined value in Synopsys. Indicates user input text you type verbatim in Synopsys syntax and examples. (User input that is not Synopsys syntax, such as a user name or password you enter in a GUI, is indicated by regular text font bold.) Denotes optional parameters, such as pin1 [pin2... pinn] Control-c \ / Edit > Copy Indicates a choice among alternatives, such as low medium high (This example indicates that you can enter one of three possible values for an option: low, medium, or high.) Indicates a keyboard combination, such as holding down the Control key and pressing c. Indicates a continuation of a command line. Indicates levels of directory structure or design s hierarchy. Indicates a path to a menu command, such as opening the Edit menu and choosing Copy. i-17 Unit i:
The Synopsys Physical Synthesis Flow i-18 START START RTL RTL and and Chip Chip Constraints Constraints Objectives Develop a realizable floorplan for the chip and realistic design budgets for blocks Planning Implementation Create a placed design which passes STA. Perform an initial detail route of chip Refinement and Chip Finishing ECO the P&R until it meets required performance specs for tapeout END END RTL (Register Transfer ) The Synopsys Physical Synthesis hierarchical design flow was created by the Synopsys Flow Group to help promote and ease the adoption of Synopsys design tools, as well as to provide feedback and drive enhancements of product performance and usability. The Synopsys Flow Group engages in customer partnerships from RTL to tapeout to drive success for multi-million gate designs. The flow encourages top-level floorplanning, power planning and global routing early in the flow followed by successive refinement of data and design until timing closure (i.e. the Planning, Implementation, and Refinement phases). i-18 Unit i:
An Overview of Planning i-19 START START RTL, RTL, Chip Chip constraints constraints Planning Implementation Refinement and Chip Finishing END END VCS CoverMeter Vera MC, ACS BSDC CA CA CA A New in 2.2 RTL, chip constraints RTL RTL verification verification Obtain Obtain target target RTL RTL and and toggle toggle coverage coverage compile compile datapath datapath synthesis synthesis with with scan scan JTAG insertion JTAG insertion Die Initialization Die Initialization IO Pad Assignment IO Pad Assignment Floor-planning, Floor-planning, hierarchy manipulation hierarchy manipulation reshaping reshaping FV PP CA CA CA CA FR Power Analysis Power Analysis Power Planning Power Planning Initial Initial pin pin assignment assignment Top-level Top-level global global routing routing and and congestion congestion analysis analysis Top-level Top-level repeater repeater insertion insertion Top-level Top-level route route estimation estimation Initial Initial block block timing timing budget budget VCS CA PP FR BSDC FV MC ACS VCS Verilog Simulator Chip Architect PrimePower Flex Route BSD Compiler, Boundary Scan Synthesis Formal Verification (FM Formality) Module Compiler Automatic Chip Synthesis Interface Logic Model i-19 Unit i:
An Overview of Implementation i-20 START START RTL, RTL, Chip Chip constraints constraints Planning Implementation Chip Finishing and Refinement END END New in 2.2 A PC PT PC PC PT physical physical synthesis synthesis Low Low Power Power Optimization Optimization One One Pass Pass Scan Scan Placement Placement Generation Generation Top Top physical physical synthesis synthesis Low Low Power Power Optimization Optimization One One Pass Pass Scan Scan Placement Placement FV FV ATPG Full Full Chip Chip STA STA Placement Placement handoff handoff timing OK no yes PT CA FV CTS CTS Detail Detail Routing Routing RC RC Extraction Extraction STA and STA and creation creation timing OK? yes no Chip Chip Integration Integration Top Top CTS CTS Top Top Detail Detail Route Route CTC Arcadia Detail Router Detail Router ECO ECO Route Route FV RCcorrelation RCcorrelation level level IPO IPO CTC, STAMP Detail Router PC CTS ECO PC CTC ATPG IPO Clock Tree Synthesis Engineering Change Order Physical Compiler ClockTree Compiler Automatic Test Pattern Generation In-Place Optimization i-20 Unit i:
An Overview of Refinement i-21 START START RTL, RTL, Chip Chip constraints constraints Planning Implementation Refinement and Chip Finishing END END PC Detail Router Arcadia New in 2.2 PT PT level level IPO, IPO, hold hold fix fix ECO Route ECO Route Top Extraction Top Extraction Full Chip STA Full Chip STA timing OK Capture Capture Constraints Constraints yes Top Top level level IPO, IPO, hold hold fix fix Top Top ECO ECO Route Route PC Detail Router Arcadia PT PT PP PT-SI Detail Router SLE Calibre Calibre SLE no s/top s/top RC RC Extraction Extraction Generation Generation Full Chip STA Full Chip STA timing OK yes Final Final Power Power Analysis Analysis Crosstalk Crosstalk Analysis Analysis Crosstalk Crosstalk Repair Repair GDSII Merge GDSII Merge DRC DRC LVS LVS Chip Finishing Chip Finishing SLE LVS DRC GDSII Synopsys Layout Editor Layout vs. Schematic Rule Checker Graphics Standard Format II i-21 Unit i: