Packaging for parallel optical interconnects with on-chip optical access I. INTRODUCTION Parallel optical interconnects requires the integration of lasers and detectors directly on the CMOS chip. In the IO project the hybridization and the packaging of such electro-optical modules is developed. This paper summarizes the development of high-performance packages that goes a step beyond of what is currently available. The packaging consists of two major steps: -A first step is wafer scale hybridization; this is the flip-chip mounting of the opto-chips on the CMOS and eventually the flip chip mounting of alignment benches on CMOS to allow ultra-precise connector alignment. Although mounting on CMOS has been reported by various groups and for different applications, high yield, high throughput, and reliability remain issues to be solved. -B second step is packaging: placement and sealing of the hybridized module in the package. on package mounting of alignment structures and transparent/semi-hermetic sealing are the main issues to address. II. FLIP-CHIP on CMOS Both VCSEL and detector chips are flip-chip mounted on the CMOS using an Indium bump technology. The indium bumps allow for a high-yield and high reliable flip-chip. The ductile property of Indium decreases the mechanical stresses at the ball joints. A. Hybridization The CMOS wafers from the foundry are first post-processed: the solder is deposited on the wafer heated to form bumps. Opto-chips and alignment benches are prepared for hybridization. (figure 1) : the flip-chipping is done on a Suss flip-chip machine The XY alignment is made excellent thanks to the self-aligning effect of the reflow flip-chip technique. The accuracy on the relative position of the chips is measured better than +/-1.0 micron after soldering. Preliminary experiments show a good connection yield. Figure 1 : CMOS, optochips and alignment benches before hybridization
B. Postprocess After the hybridization, the on wafer optochips are thinned and coated.. This is done as follows: following the flip-chipping operation a polymer underfill is applied (wafer scale processing) to increase the yield and reliability of the flip-chip connection. Finally the optochips are mechanically thinned to 30um to allow future fiber s butt coupling, and an antireflection is applied to both VCSEL and detector chips. (figure 2). At this stage, the functionality of the electro-optical hybrid can be tested on wafer-scale. As will be described later silicon alignment benches may also be sequentially hybridized next to optochips to allow for connector/optochips future alignment. Figure 2: thinned optochips (30µm) on CMOS wafer C. Silicon benches hybridization Finally silicon benches can be flip-chipped around the opto-chips at the wafer scale, they allow future positioning of optical connector (figure 3). These benches are precision micromechanical silicon parts that are used as a reference to obtain a good alignment from optical connector to the package. Figure 3: silicon benches on CMOS wafer Finally each equipped CMOS chip is diced before package integration III. The opto-electronic package A. Specifications The packaging of parallel optical interconnect modules is different compared to the
packaging of electronic chips. The package has to fulfill optical, thermal, electrical and mechanical interface from the chip to the rest of the system. The requirements can be summarized as follows: OPTICAL REQUIREMENTS The light has to enter the chip, requiring a transparent interface. (at least transparent at VCSEL wavelength) THERMAL REQUIREMENTS Current and future electronic chips will show increasing power dissipation, up to 70W per package. The package has to thermally dissipate this heat, and must address thermal spreading and thermal resistance issues. MECHANICAL REQUIREMENTS The package has to provide alignment aids for connector, these aids must allow for repeated optical connections with better than +/- 10µm X,Y final alignment tolerances between any multimode fiber from the connector and any VCSEL or detector from the flip-chipped opto-arrays. ELECTRICAL REQUIREMENTS The package has to provide high frequency inputs/outputs (2,5 Gb/s LVDS I/Os required) RELIABILITY A hermetic and transparent protection is required to guarantee the component reliability over its life. Depending on the requirements set by the application, a polymeric encapsulation or a sealed glass package can be used. B. Description of the realizations 1) Mounting in package The chip (on which the 8*8 VCSELs and detectors arrays are hybridized) is mounted and wire-bonded on a custom 302 I/Os ceramic BGA (Ball Grid Array) package having 32 LVDS differential pairs for high speed signals,. The BGA 302 ceramic package is shown in figure 4. Figure 4 : BGA 302 with CMOS and optos mounted in 2) Alignment techniques The package needs an optical access that accepts the connector with the fibers. The
alignment of the fibers to the opto-electronic components is of uttermost importance. Therefore, special attention is given to the alignment procedure. The package includes a spacer plate, with alignment pins for guiding the optical connector. The position of the spacer plate relative to the hybridized modules should be very precise, as this determines the optical coupling to (and from) the fiber. The position of the alignment pins determine the XY alignment, the position of the plate determines the Z alignment. There are two techniques under development for spacer plate alignment: one uses Silicon benches for precise XY alignment, and one technique uses index alignment.(figure 5). silicon bench approach: a silicon bench with precision holes for the alignment pins is flip-chip mounted on the CMOS, next to the opto chips. The precision of the XY alignment is determined by the precision of the bench, and the flip-chip process. This alignment can be very precise, typically better than 1micron. (figure 6). In this case the spacer plate guarantees the mechanical stiffness of the assembly. Figure 6 : package with alignment pins guided by silicon benches index alignment approach: a coordinate measurement machine is used to measure the relative coordinates of the spacer plate and the package, and bring the spacer plate automatically to the desired location. Afterwards, the position of the spacer plate is fixed by UV curable adhesive. This is a contact less approach, offering full 3-D
alignment of 2 independent objects. The positioning accuracy is estimated at +/-5um, which is sufficient for this application.(figure 7) Figure 7 : index alignment, package with alignment guide 3 Hermeticity In electronic packages, the chip is encapsulated to protect the die against external influences, such as dust, but more important the humidity. There are two different approaches: a complete hermetic sealing, where metals and ceramic lids are used to guarantee a very good protection against moisture. A low-cost technique uses a polymeric encapsulation, which guarantees sufficient protection against moisture. However, the cost advantage is important. Both type of encapsulation can be extended for optical applications. In case of full hermetic encapsulation, a transparent glass lid is used, or the optical fibers are soldered into a metal package. In case of polymeric encapsulation, transparent polymers are used. Standard transparent polymers offer limited protection, but newer, advanced polymers such as silicones have better protective characteristics and will be studied in the course of the project. IV. FUTURE pathways for integration Together for the development of the packaging techniques for 8*8 arrays two other advanced techniques are under evaluation in the IO program A. CSP packaging In the advanced version of packaging for 16*16 arrays, the CMOS (with opto arrays already flip-chipped on) is directly flip-chip mounted over the CSP ceramic (figure 8).
Figure 8 : CSP packaging for 16*16 arrays In this case one speaks about CSP packages (=Chip Scale Package) and the size of the package is no more than 20% the CMOS chip size. This allows for ultra high-speed connection, hermetic sealing is made easier and optics can be included in the optical pathway. Guide pins for the optical connector alignment are fixed into the CSP package. B. Direct flip chip over glass sheet A second advanced packaging technique is directly linked to glass sheet PCB development, in this case direct flip-chipping over the optical PCB is performed (COB).(figure 9). Figure 9 : flip chip over glass sheet PCB V. CONCLUSION We demonstrated the direct optical access over CMOS based on : - direct flip chip on CMOS of 8*8 opto chips - on wafer post-processing of the hybridized opto chips (thinning, coating ) - on wafer hybridization of alignment silicon benches We demonstrated the possible integration in high speed BGA packages with tight tolerances of the subassembly. We demonstrated the direct on package integration of guiding pins for connectorization We are developing CSP type packaging for future high pins count opto electronic devices and also direct flip-chip on glass sheet boards.
Biographies François Marion, born 1953,received his Diploma in electrical engineering from the polytechnique institute in Grenoble (INPG). In 1978 he joined Motorola Semiconductors as product, device, process engineer. He joined LETI in 1988 and was in charge of the development of assembly and wafer scale techniques for very large starring IR arrays.development. In the course of this project he developed the first flip-chip machines together with Suss Microtec (to day the world best sell FC150 ) and built the first in the world 15µm pitch mega pixel arrays for IR detection. Since 2000 he is project manager on several projects related to the assembly of optical components for telecommunications and data links (POLA, IO, Intexys ). He holds more than 30 patents.