Yu will learn the fllwing in this lab: The UNIVERSITY f NORTH CAROLINA at CHAPEL HILL Cmp 541 Digital Lgic and Cmputer Design Prf. Mntek Singh Fall 2017 Lab #8: A Full Single-Cycle MIPS Prcessr Issued Wed 10/18/17; Due Fri 10/27/17 (1:25pm) Integrating ALU, registers, etc., t frm a full datapath Designing the cntrl unit fr a prcessr Integrating the cntrl unit with the datapath Integrating memry units with a prcessr Encding instructins Mre practice with test fixtures fr testing a prcessr Part 0: Carefully review the single-cycle MIPS prcessr design f Lecture 11. Study the lecture slides carefully, and review Chapter 7.1-7.3 f textbk. Als review the Pattersn Hennessy frnt inside green flap fr summary f the MIPS instructin set; a PDF versin f this ( green card ) is psted n the class website. Wherever there are differences between the Pattersn Hennessy textbk and the Harris and Harris textbk, we will adhere t the frmer. We will d s because the MARS simulatr, which yu will use t assemble yur MIPS assembly cde fllws the frmer. Please study Slides 33-38 especially carefully t nte three specific design chices fr ur lab versin f MIPS: Exceptins: Our lab versin des nt supprt exceptins. Reset: It des supprt handling resets thugh. In particular, if the Reset input is asserted, the prgram cunter is re-initialized t the address 0x0040_0000. This address was chsen fr cmpatibility with the MARS assembler. Accrdingly, the PC register in the datapath shuld be initialized t this address, and re-initialized whenever reset is asserted. Enable: T help with debugging, we will als incrprate an Enable input. When enabled, the prcessr runs nrmally. When Enable = 0, hwever, the prcessr freezes. This is accmplished by disabling writes t: PC, register file and data memry. This mdificatin will allws us later t single-step thrugh executin as a debugging aid. (cntinued n next page) 1
Part 1: The Cntrl Unit In preparatin fr designing a full MIPS CPU, we will develp the Cntrl Unit in this exercise. Belw are tw diagrams f ur single-cycle MIPS CPU (frm Cmp411), first a tp-level verview, then a detailed ne. Here is the picture shwing the details: 2
Let us first develp the cntrl unit. It shuld handle ALL f the fllwing instructins: lw and sw addi, addiu, slti, sltiu, ri, lui, andi, xri NOTE 1: Cntrary t what yu may have learned earlier (e.g., in Cmp411), addiu actually des nt perfrm unsigned additin. In fact, it sign-extends the immediate. This instructin (alng with addu) was actually misnamed! The nly difference between addiu and addi is that addiu des nt cause an exceptin n verflw, whereas addi des. Since we are nt implementing exceptins, addiu and addi are identical fr ur purpses. NOTE 2: Als, cntrary t what yu may have learned earlier, sltiu actually sign-extends the immediate, but perfrms unsigned cmparisn, i.e. ALUFN is LTU. Als nte that ri shuld zer-extend the immediate because it is a lgical peratin! Finally, sign-extensin fr lui is a dn t-care because the 16-bit immediate is placed in the upper half f the register withut any need fr padding. R-type: add, addu, sub, and, r, xr, nr, slt, sltu, sll, sllv, srl, sra NOTE: The addu instructin, fr ur purpses, is identical t the add instructin. They nly differ in hw they handle verflw, which we ignre in ur design. The reasn fr supprting the addu instructin is that the MARS assembler ften autmatically inserts addu instructins in ur cde, especially fr the range f memry addresses we will be using. beq, bne, j, jal and jr First study the Pwerpint slides n Single-Cycle MIPS prcessr (including Slides 33-38). Next, fill ut the table belw with the values f all the cntrl signals fr the 28 basic MIPS instructins listed here. If a cntrl signal s value des nt matter fr a particular instructin, please make it a dn t-care (i.e., 1 bx, 2 bx, etc., depending n the number f bits). Using the values in this table, cmplete the Verilg descriptin f the cntrl unit in the file cntrller.sv available n the website. Use the Verilg test fixture prvided n the website t simulate and test yur design. The text fixture is selfchecking, s any errrs will be flagged autmatically. Please use exactly the same names fr the tp-level inputs and utputs as used in the tester. 3
Instr werf wdsel wasel asel bsel sext wr alufn pcsel Z=1 Z=0 LW 1 10 01 00 1 1 0 0XX01 SW ADDI ADDIU SLTI SLTIU ORI LUI ANDI XORI BEQ BNE J JAL ADD ADDU SUB AND OR XOR NOR SLT SLTU SLL SLLV SRL SRA JR MIPS instructin decding table These values will depend n the Z flag. 4
Part 2: Design a full single-cycle MIPS. Put all the pieces tgether t create a full single-cycle MIPS CPU as discussed in class. Verilg templates fr sme f the higher-level mdules are n the curse website. In particular, d the fllwing: Design the tp-level mdule, with instructin and data memries and the MIPS CPU, as shwn n Slides #37-38 f Lecture 11. Name this file tp.sv. Fr nw, chse a reasnably small size fr each memry, e.g. 64 memry lcatins. Nte: The addresses generated by the CPU t access these memries will still be 32 bits lng, even thugh fewer address bits will actually be used inside these memries. Use the template ram.sv frm the previus lab, and make the fllwing mdificatins: The instructin memry will be read-nly, while the data memry will be read-write. Send full 32-bit PC t instructin memry; strip the last tw bits inside the instructin memry t derive a wrd address frm the byte address. Similarly, send full 32 bits f address t data memry; strip the last tw bits inside the data memry t derive a wrd address. Bth f these memries shuld return a full 32-bit wrd (i.e., Nlc = 64, Dbits = 32, and initfile is the file name fr initializatin values). Yur instructin memry mdule shuld be in its wn file called imem.sv, and the data memry mdule in its wn file called dmem.sv. Bth shuld be directly based n the template ram.sv frm Lab 7. Initialize the instructin and data memries, using the methd explained in Lab 7. The file that cntains the initial values fr the instructin memry will cntain a 32-bit assembly cded instructin per line (in hex). The file that cntains the initial values fr the data memry will cntain sme 32-bit data values, again ne per line. Nte: Yu can create these files either within Vivad, r utside f Vivad and then add these t the prject. Make sure t set their type t Memry File. Design the tp-level prcessr, cntaining cntrller and datapath mdules, using the figure belw fr guidance. Nte: There are differences between the MIPS design in the Harris and Harris textbk and what we are designing in the lab. Our lab versin has a much mre sphisticated ALU. Therefre, d nt blindly fllw the infrmatin in the bk; instead, fllw the lecture slides and the lab writeups. The datapath shuld be 32-bit wide (i.e., registers, ALU, data memry and instructin memry, all use 32-bit wrds). Cmplete all the little pieces, s the design lks like that in Lecture 11, als reprduced belw. Small amunts f lgic can be inlined (instead f written as a separate mdule), e.g., muxes, sign extensin, adders, shift-by-2, etc. The figures n Page 2 shw the tp-level hierarchical decmpsitin. Yur design is required t fllw this hierarchy. 5
6
Other helpful tips and testing aids: Remember t use the directive `default_nettype nne t make it easier t catch missing declaratins r name mismatches due t typs, etc. Use the test fixture t test yur CPU via simulatin. A self-checking tester is prvided n the class website. It was initially written in MIPS assembly, then cmpiled using MARS and cnverted t hex machine cde, which shuld be used t initialize yur instructin memry. Stre the machine cde int the file that is used t initialize the instructin memry. Be sure t initialize the prgram cunter (PC) inside yur MIPS design t 0x0040_0000, s that it starts executing frm the beginning f the instructin memry. Similarly, t initialize yur data memry, put the initial values in the crrespnding file. The tester is called full (tester_full.sv): The assembly prgram (full.asm) executes each f the 28 instructins we have implemented, including prcedure calls/returns, and recursin using a stack. Yu dn t have t run this prgram in MARS, but yu may. It has 59 instructins ttal, s the instructin memry shuld be 64 lcatins; set the Nlc parameter fr instructin memry t 64. Als, in the tp mdule, mdify the names f the files that have initializatin values t full_imem.mem and full_dmem.mem, respectively. Fr nw, yu will nt be implementing yur design n the bard. Yu will d s next lab. Start thinking abut what yu wuld like t build fr yur final prject! Every prject must use a VGA display as utput. Nexys 4 bards have audi utput built-in. Keybard/muse inputs will be available t every prject. The Nexys 4 bards have accelermeters built-in; a limited number f ther input devices (jysticks, keypads, etc.) may be available t use instead. Start thinking! Okay, gd luck! What t submit: Part 1: The file fr the (cntrller.sv), a picture f the instructin decding table (phne picture is fine), and a screensht f the simulatin wavefrm windw using the self-checking tester. Part 2: ALL f the Verilg files, but skip the ALU and its submdules. Als, the screensht f the simulatin wavefrms fr the full self-checking tester prvided. Hw t submit: Please submit yur wrk by email by 1:25pm, Oct 27 (Fri), as fllws: Send email t: cmp541-submit-f17@cs.unc.edu Use subject line: Lab 8 Include all f the attachments, and yur statement/bservatin, as specified abve 7