Virtual Memory CSCI 315 Operating Systems Design Department of Computer Science Notice: The slides for this lecture have been largely based on those from an earlier edition of the course text Operating Systems Concepts, 8th ed., by Silberschatz, Galvin, and Gagne. Many, if not all, the illustrations contained in this presentation come from this source.
Logical vs. Physical Address Space The concept of a logical address space that is bound to a separate physical address space is central to proper memory management. Logical address generated by the CPU; also referred to as virtual address. Physical address address seen by the memory unit. Logical and physical addresses are the same in compiletime and load-time address-binding schemes; logical (virtual) and physical addresses differ in execution-time address-binding scheme. CSCI 315 Operating Systems Design 2
Contiguous Allocation Main memory usually into two partitions: Resident operating system, usually held in low memory with interrupt vector. User processes then held in high memory. Single-partition allocation Relocation-register scheme used to protect user processes from each other, and from changing operating-system code and data. Relocation-register contains value of smallest physical address; limit register contains range of logical addresses each logical address must be less than the limit register. CSCI 315 Operating Systems Design 3
Contiguous Allocation Multiple-partition allocation Hole block of available memory; holes of various size are scattered throughout memory. When a process arrives, it is allocated memory from a hole large enough to accommodate it. Operating system maintains information about: a) allocated partitions b) free partitions (hole) OS OS OS OS process 5 process 5 process 5 process 5 process 9 process 9 process 8 process 10 process 2 process 2 process 2 process 2 CSCI 315 Operating Systems Design 4
Dynamic Storage-Allocation Problem How to satisfy a request of size n from a list of free holes. First-fit: Allocate the first hole that is big enough. Best-fit: Allocate the smallest hole that is big enough; must search entire list, unless ordered by size. Produces the smallest leftover hole. Worst-fit: Allocate the largest hole; must also search entire list. Produces the largest leftover hole. First-fit and best-fit better than worst-fit in terms of speed and storage utilization. CSCI 315 Operating Systems Design 5
Fragmentation External Fragmentation total memory space exists to satisfy a request, but it is not contiguous. Internal Fragmentation allocated memory may be slightly larger than requested memory; this size difference is memory internal to a partition, but not being used. Reduce external fragmentation by compaction: Shuffle memory contents to place all free memory together in one large block. Compaction is possible only if relocation is dynamic, and is done at execution time. I/O problem Latch job in memory while it is involved in I/O. Do I/O only into OS buffers. CSCI 315 Operating Systems Design 6
Paging Logical address space of a process can be noncontiguous; process is allocated physical memory whenever the latter is available. Divide physical memory into fixed-sized blocks called frames (size is power of 2, between 512 bytes and 8192 bytes). Divide logical memory into blocks of same size called pages (we want to make page size equal to frame size). Keep track of all free frames. To run a program of size n pages, need to find n free frames and load program. Set up a page table to translate logical to physical addresses. Internal fragmentation. CSCI 315 Operating Systems Design 7
Address Translation Scheme Address generated by CPU is divided into: Page number (p) used as an index into a page table which contains base address of each page in physical memory. Page offset (d) combined with base address to define the physical memory address that is sent to the memory unit. CSCI 315 Operating Systems Design 8
Address Translation Architecture CSCI 315 Operating Systems Design 9
Paging Example CSCI 315 Operating Systems Design 10
Free Frames Before allocation After allocation CSCI 315 Operating Systems Design 11
Implementation of Page Table Page table is kept in main memory. Page-table base register (PTBR) points to the page table. Page-table length register (PRLR) indicates size of the page table. In this scheme every data/instruction access requires two memory accesses. One for the page table and one for the data/instruction. The two memory access problem can be solved by the use of a special fast-lookup hardware cache called associative memory or translation look-aside buffers (TLBs). CSCI 315 Operating Systems Design 12
Associative Memory Associative memory parallel search Page # Frame # Address translation (A, A ) If A is in associative register, get frame # out. Otherwise get frame # from page table in memory Associative memory is used to implement a TLB. Note that the TLB is nothing more than a special purpose cache memory to speed up access to the page table. CSCI 315 Operating Systems Design 13
Paging Hardware With TLB CSCI 315 Operating Systems Design 14
Effective Access Time Associative Lookup = ε time unit Assume memory cycle time is 1 microsecond Hit ratio percentage of times that a page number is found in the associative registers; ration related to number of associative registers. Hit ratio = α Effective Access Time (EAT) EAT = (1 + ε) α + (2 + ε)(1 α) = 2 + ε α CSCI 315 Operating Systems Design 15
Memory Protection Memory protection implemented by associating protection bit with each frame. Valid-invalid bit attached to each entry in the page table: valid indicates that the associated page is in the process logical address space, and is thus a legal page. invalid indicates that the page is not in the process logical address space. CSCI 315 Operating Systems Design 16
Hierarchical Page Tables Break up the logical address space into multiple page tables. A simple technique is a two-level page table. CSCI 315 Operating Systems Design 17
Two-Level Paging Example A logical address (on 32-bit machine with 4K page size) is divided into: a page number consisting of 20 bits. a page offset consisting of 12 bits. Since the page table is paged, the page number is further divided into: a 10-bit page number. a 10-bit page offset. Thus, a logical address is as follows: page number p 1 p 2 d page offset 10 10 12 where p 1 is an index into the outer page table, and p 2 is the displacement within the page of the outer page table. CSCI 315 Operating Systems Design 18
Two-Level Page-Table Scheme CSCI 315 Operating Systems Design 19
Address-Translation Scheme Address-translation scheme for a two-level 32-bit paging architecture: CSCI 315 Operating Systems Design 20
Shared Pages Shared code One copy of read-only (reentrant) code shared among processes (i.e., text editors, compilers, window systems). Shared code must appear in same location in the logical address space of all processes. Private code and data Each process keeps a separate copy of the code and data. The pages for the private code and data can appear anywhere in the logical address space. CSCI 315 Operating Systems Design 21
Shared Pages Example CSCI 315 Operating Systems Design 22
Virtual Memory Virtual memory separation of user logical memory from physical memory. Only part of the program needs to be in memory for execution. Logical address space can therefore be much larger than physical address space. Allows address spaces to be shared by several processes. Allows for more efficient process creation. Virtual memory can be implemented via: Demand paging Demand segmentation CSCI 315 Operating Systems Design 23
Virtual Memory Larger than Physical Memory CSCI 315 Operating Systems Design 24
Demand Paging Bring a page into memory only when it is needed. Less I/O needed. Less memory needed. Faster response. More users. Page is needed (there is a reference to it): invalid reference abort. not-in-memory bring to memory. CSCI 315 Operating Systems Design 25
Transfer of a Paged Memory to Contiguous Disk Space CSCI 315 Operating Systems Design 26
Valid-Invalid Bit With each page table entry a valid invalid bit is associated (1 in-memory, 0 not-in-memory) Initially valid invalid but is set to 0 on all entries. Example of a page table snapshot. Frame # M page table valid-invalid bit 1 1 1 1 0 0 0 During address translation, if valid invalid bit in page table entry is 0 page fault. CSCI 315 Operating Systems Design 27
Page Table when some pages are not in Main Memory CSCI 315 Operating Systems Design 28
Page Fault If there is ever a reference to a page, first reference will trap to OS page fault. OS looks at page table to decide: If it was an invalid reference abort. If it was a reference to a page that is not in memory, continue. Get an empty frame. Swap page into frame. Correct the page table and make validation bit = 1. Restart the instruction that caused the page fault. CSCI 315 Operating Systems Design 29
Steps in Handling a Page Fault CSCI 315 Operating Systems Design 30
What if there is no free frame? Page replacement find some page in memory, that is not really in use and swap it out. Must define an algorithm to select what page is replaced. Performance: want an algorithm which will result in minimum number of page faults. The same page may be brought in and out of memory several times. CSCI 315 Operating Systems Design 31
No free frame: now what? Page replacement: Are all those pages in memory being referenced? Choose one to swap back out to disk and make room to load a new page. Algorithm: How you choose a victim. Performance: Want an algorithm that will result in minimum number of page faults. Side effect: The same page may be brought in and out of memory several times. CSCI 315 Operating Systems Design 32
Performance of Demand Paging Page Fault Rate: 0 p 1.0 if p = 0 no page faults. if p = 1, every reference is a fault. Effective Access Time (EAT): EAT = [(1 p) (memory access)] + [p (page fault overhead)] where: page fault overhead = [swap page out ] + [swap page in] + [restart overhead] CSCI 315 Operating Systems Design 33
Page Replacement Prevent over-allocation of memory by modifying pagefault service routine to include page replacement. Use modify (dirty) bit to reduce overhead of page transfers only modified pages are written to disk. Page replacement completes separation between logical memory and physical memory large virtual memory can be provided on a smaller physical memory. CSCI 315 Operating Systems Design 34
Need For Page Replacement CSCI 315 Operating Systems Design 35
Basic Page Replacement 1. Find the location of the desired page on disk. 2. Find a free frame: - If there is a free frame, use it. - If there is no free frame, use a page replacement algorithm to select a victim frame. 3. Read the desired page into the (newly) free frame. Update the page and frame tables. 4. Restart the process. CSCI 315 Operating Systems Design 36
Page Replacement CSCI 315 Operating Systems Design 37
Page Replacement Algorithms Goal: Produce a low page-fault rate. Evaluate algorithm by running it on a particular string of memory references (reference string) and computing the number of page faults on that string. The reference string is produced by tracing a real program or by some stochastic model. We look at every address produced and strip off the page offset, leaving only the page number. For instance: 1, 2, 3, 4, 1, 2, 5, 1, 2, 3, 4, 5 CSCI 315 Operating Systems Design 38
Graph of Page Faults Versus The Number of Frames CSCI 315 Operating Systems Design 39
FIFO Page Replacement Reference string: 1, 2, 3, 4, 1, 2, 5, 1, 2, 3, 4, 5. 3 frames (3 pages can be in memory at a time per process) 1 1 4 5 2 2 1 3 9 page faults 3 3 2 4 4 frames 1 1 5 4 2 2 1 5 10 page faults 3 3 2 4 4 3 FIFO Replacement Belady s Anomaly: more frames, more page faults. CSCI 315 Operating Systems Design 40
FIFO Page Replacement CSCI 315 Operating Systems Design 41
FIFO (Belady s Anomaly) CSCI 315 Operating Systems Design 42
Optimal Algorithm Replace the page that will not be used for longest period of time. (How can you know what the future references will be?) 4 frames example: 1, 2, 3, 4, 1, 2, 5, 1, 2, 3, 4, 5 1 4 2 6 page faults 3 4 5 Used for measuring how well your algorithm performs. CSCI 315 Operating Systems Design 43
Optimal Page Replacement CSCI 315 Operating Systems Design 44
LRU Algorithm Reference string: 1, 2, 3, 4, 1, 2, 5, 1, 2, 3, 4, 5 1 5 2 3 5 4 Counter implementation: 4 3 Every page entry has a counter; every time page is referenced through this entry, copy the clock into the counter. When a page needs to be changed, look at the counters to determine which are to change. CSCI 315 Operating Systems Design 45
LRU Page Replacement CSCI 315 Operating Systems Design 46
LRU Algorithm (Cont.) Stack implementation keep a stack of page numbers in a double link form: Page referenced: move it to the top requires 6 pointers to be changed No search for replacement. CSCI 315 Operating Systems Design 47
LRU and Belady s Anomaly LRU does not suffer from Belady s Anomaly (OPT doesn t either). It has been shown that algorithms in a class called stack algorithms can never exhibit Belady s Anomaly. A stack algorithm is one for which the set of pages in memory for n frames is a subset of the pages that Could be in memory for n+1 frames. CSCI 315 Operating Systems Design 48
Use Of A Stack to Record The Most Recent Page References CSCI 315 Operating Systems Design 49
LRU Approximation Algorithms Reference bit With each page associate a bit, initially = 0 When page is referenced bit set to 1. Replace the one which is 0 (if one exists). We do not know the order, however. Second chance Need reference bit. Clock replacement. If page to be replaced (in clock order) has reference bit = 1. then: set reference bit 0. leave page in memory. replace next page (in clock order), subject to same rules. CSCI 315 Operating Systems Design 50
Second-Chance (clock) Page-Replacement Algorithm CSCI 315 Operating Systems Design 51
Counting Algorithms Keep a counter of the number of references that have been made to each page. LFU Algorithm: replaces page with smallest count. MFU Algorithm: based on the argument that the page with the smallest count was probably just brought in and has yet to be used. CSCI 315 Operating Systems Design 52
Allocation of Frames Each process needs a minimum number of pages. There are two major allocation schemes: fixed allocation priority allocation CSCI 315 Operating Systems Design 53
Fixed Allocation Equal allocation e.g., if 100 frames and 5 processes, give each 20 pages. Proportional allocation Allocate according to the size of process. CSCI 315 Operating Systems Design 54
Priority Allocation Use a proportional allocation scheme using priorities rather than size. If process P i generates a page fault, select for replacement one of its frames. select for replacement a frame from a process with lower priority number. CSCI 315 Operating Systems Design 55
Global vs. Local Allocation Global replacement process selects a replacement frame from the set of all frames; one process can take a frame from another. Local replacement each process selects from only its own set of allocated frames. CSCI 315 Operating Systems Design 56
Thrashing If a process does not have enough pages, the page-fault rate is very high. This leads to: Low CPU utilization. Operating system thinks that it needs to increase the degree of multiprogramming. Another process added to the system. Thrashing a process is busy swapping pages in and out. CSCI 315 Operating Systems Design 57
Thrashing Why does paging work? Locality model Process migrates from one locality to another. Localities may overlap. Why does thrashing occur? Σ size of locality > total memory size CSCI 315 Operating Systems Design 58
Locality in Memory-Reference Pattern CSCI 315 Operating Systems Design 59
Working-Set Model Δ working-set window a fixed number of page references. WSS i (working set of Process P i ) = total number of pages referenced in the most recent Δ (varies in time) if Δ too small will not encompass entire locality. if Δ too large will encompass several localities. if Δ = will encompass entire program. D = Σ WSS i total demand frames if D > m Thrashing Policy if D > m, then suspend one of the processes. CSCI 315 Operating Systems Design 60
Working-set model CSCI 315 Operating Systems Design 61
Keeping Track of the Working Set Approximate with interval timer + a reference bit Example: Δ = 10,000 Timer interrupts after every 5000 time units. Keep in memory 2 bits for each page. Whenever a timer interrupts copy and sets the values of all reference bits to 0. If one of the bits in memory = 1 page in working set. Why is this not completely accurate? Improvement = 10 bits and interrupt every 1000 time units. CSCI 315 Operating Systems Design 62
Page-Fault Frequency Scheme Establish acceptable page-fault rate. If actual rate too low, process loses frame. If actual rate too high, process gains frame. CSCI 315 Operating Systems Design 63
Memory-mapped Files Memory mapping a file can be accomplished by mapping a disk block to one or more pages in memory. A page-sized portion of the file is read from the file system into a physical page. Subsequent read() and write() operations are handled as memory (not disk) accesses. Writing to the file in memory is not necessarily synchronous to the file on disk. The file can be committed back to disk when it s closed. CSCI 315 Operating Systems Design 64
Memory-mapped Files 3 1 2 3 4 5 6 process A virtual memory 6 1 5 4 2 1 2 3 4 5 6 1 2 3 4 5 6 disk file process B virtual memory CSCI 315 Operating Systems Design 65
Prepaging Prepaging: In order to avoid the initial number of page faults, the system can bring into memory all the pages that will be needed all at once. This can also be applied when a swapped-out process is restarted. The smart thing to do is to remember the working set of the process. One question that arises is whether all the pages brought in will actually be used Is the cost of prepaging less than the cost of servicing each individual page fault? CSCI 315 Operating Systems Design 66