Memory Technology Caches 1 Static RAM (SRAM) 0.5ns 2.5ns, $2000 $5000 per GB Dynamic RAM (DRAM) 50ns 70ns, $20 $75 per GB Magnetic disk 5ms 20ms, $0.20 $2 per GB Ideal memory Average access time similar to that of SRAM Capacity and cost/gb similar to that of disk
Principle of Locality Caches 2 Programs access a small proportion of their address space at any time Temporal locality Items accessed recently are likely to be accessed again soon e.g., instructions in a loop, induction variables Spatial locality Items near (in memory) those accessed recently are likely to be accessed soon E.g., sequential instruction access, array data
Taking Advantage of Locality Caches 3 Memory hierarchy Store everything on disk Copy recently accessed (and nearby) items from disk to smaller DRAM memory Main memory Copy more recently accessed (and nearby) items from DRAM to smaller SRAM memory Cache memory attached to CPU
Memory Hierarchy Levels Caches 4 Block(aka line): fundamental unit of copying May be multiple words If accessed data is present in upper level Hit: access satisfied by upper level Hit ratio: hits/accesses cache DRAM If accessed data is absent Miss: block copied from lower level Time taken: miss penalty Miss ratio: misses/accesses = 1 hit ratio Then accessed data supplied from upper level
Cache Memory Caches 5 Cache memory The level of the memory hierarchy closest to the CPU Given accesses X 1,, X n 1, X n How do we know if the data is present? Where do we look?
Direct Mapped Cache Caches 6 Location in cache determined entirely by memory address of cached data Direct mapped: only one choice (Block address) modulo (#Blocks in cache) #Blocks is a power of 2 Use low-order address bits
Tags and Valid Bits Caches 7 How do we know which particular block is stored in a cache location? Store the block address as well as the data Actually, only need the high-order bits --- why?? Called the tag What if there is no data in a location? Valid bit: 1 = present, 0 = not present Initially valid bit is 0
Cache Example Caches 8 8-blocks, 1 word/block, direct mapped Initial state: Index V Tag Data 000 N 001 N 010 N 011 N 100 N 101 N 110 N 111 N
Cache Example Caches 9 Word addr Binary addr Hit/miss Cache block 22 10 110 Miss 110 Index V Tag Data 000 N 001 N 010 N 011 N 100 N 101 N 110 N 111 N
Cache Example Caches 10 Word addr Binary addr Hit/miss Cache block 22 10 110 Miss 110 Index V Tag Data 000 N 001 N 010 N 011 N 100 N 101 N 110 Y 10 Mem[10110] 111 N
Cache Example Caches 11 Word addr Binary addr Hit/miss Cache block 26 11 010 Miss 010 Index V Tag Data 000 N 001 N 010 Y 11 Mem[11010] 011 N 100 N 101 N 110 Y 10 Mem[10110] 111 N
Cache Example Caches 12 Word addr Binary addr Hit/miss Cache block 22 10 110 Hit 110 26 11 010 Hit 010 Index V Tag Data 000 N 001 N 010 Y 11 Mem[11010] 011 N 100 N 101 N 110 Y 10 Mem[10110] 111 N
Cache Example Caches 13 Word addr Binary addr Hit/miss Cache block 16 10000 Miss 000 3 00011 Miss 011 16 10000 Hit 000 Index V Tag Data 000 Y 10 Mem[10000] 001 N 010 Y 11 Mem[11010] 011 Y 00 Mem[00011] 100 N 101 N 110 Y 10 Mem[10110] 111 N
Cache Example Caches 14 Word addr Binary addr Hit/miss Cache block 18 10 010 Miss 010 Index V Tag Data 000 Y 10 Mem[10000] 001 N 010 Y 11 Mem[11010] 011 Y 00 Mem[00011] 100 N 101 N 110 Y 10 Mem[10110] 111 N
Cache Example Caches 15 Word addr Binary addr Hit/miss Cache block 18 10 010 Miss 010 Index V Tag Data 000 Y 10 Mem[10000] 001 N 010 Y 10 Mem[10010] 011 Y 00 Mem[00011] 100 N 101 N 110 Y 10 Mem[10110] 111 N
Cache Addressing Caches 16 QTP:how are the low 2 bits used?
Memory Organization Caches 17 4 GiB DRAM = 2 32 bytes = 2 20 blocks of 2 12 bytes = 2 20 4-KiB blocks 0 1 2 3 0 1 2 3 S 2 20-1 4-KiB blocks W 1023 4-byte words 0 1 2 3 1 byte
Address Subdivision Caches 18 Address: Block# x 2 12 + Word# x 4 + Byte# 4 GiB memory 0x00000 0x00001 0x00002 0x00003 0x00004 0x00005...... 4-KiB block 0x000 0x001 0x002 0x003...... 0x278 0 1 word...... 1 2 0xFFFFF 0x3FF 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 1 1 1 1 0 0 0 0 1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0
Address Subdivision Caches 19
Example: Larger Block Size Caches 20 64 blocks, 16 bytes/block To what block number does address 1200 map? Block address = 1200/16 = 75 Block number = 75 modulo 64 = 11 0000 0000 0000 0000 0000 0100 1011 0000 0000 0000 0000 0000 0000 0100 1011 31 10 9 4 3 0 Tag Index Offset 22 bits 6 bits 4 bits
Block Size Considerations Caches 21 Larger blocks should reduce miss rate Due to spatial locality But in a fixed-sized cache Larger blocks fewer of them fit in cache at once More competition increased miss rate Larger blocks pollution of cache Larger miss penalty Can override benefit of reduced miss rate Early restart and critical-word-first can help
Cache Misses Caches 22 On cache hit, CPU proceeds normally On cache miss Stall the CPU pipeline Fetch block from next level of hierarchy Instruction cache miss Restart instruction fetch Data cache miss Complete data access
Write-Through Caches 23 On data-write hit, could just update the block in cache But then cache and memory would be inconsistent Write through: also update memory But makes writes take longer e.g., if base CPI = 1, 10% of instructions are stores, write to memory takes 100 cycles Effective CPI = 1 + 0.1 100 = 11 Solution: write buffer Holds data waiting to be written to memory CPU continues immediately Only stalls on write if write buffer is already full
Write-Back Caches 24 Alternative: On data-write hit, just update the block in cache Keep track of whether each block is dirty When a dirty block is replaced Write it back to memory Can use a write buffer to allow replacing block to be read first
Write Allocation Caches 25 What should happen on a write miss? Alternatives for write-through Allocate on miss: fetch the block Write around: don t fetch the block Since programs often write a whole block before reading it (e.g., initialization) For write-back Usually fetch the block
Main Memory Supporting Caches Caches 26 Use DRAMs for main memory Fixed width (e.g., 1 word) Connected by fixed-width clocked bus Bus clock is typically slower than CPU clock Example cache block read 1 bus cycle for address transfer 15 bus cycles per DRAM access 1 bus cycle per data transfer For 4-word block, 1-word-wide DRAM Miss penalty = 1 + 4 (15 + 1) = 65 bus cycles Bandwidth = 16 bytes / 65 cycles = 0.25 B/cycle 1 15 1
Increasing Memory Bandwidth Caches 27 4-word wide memory Miss penalty = 1 + 15 + 1 = 17 bus cycles Bandwidth = 16 bytes / 17 cycles = 0.94 B/cycle 4-bank interleaved memory Miss penalty = 1 + 15 + 4 1 = 20 bus cycles Bandwidth = 16 bytes / 20 cycles = 0.8 B/cycle
Advanced DRAM Organization Caches 28 Bits in a DRAM are organized as a rectangular array DRAM accesses an entire row Burst mode: supply successive words from a row with reduced latency Double data rate (DDR) DRAM Transfer on both rising and falling clock edges Quad data rate (QDR) DRAM Separate DDR inputs and outputs
Measuring Cache Performance Caches 29 Components of CPU time Program execution cycles Includes cache hit time Memory stall cycles Mainly from cache misses With simplifying assumptions: Memory stall cycles Memory accesses = Miss rate Miss penalty Program = Instructions Program Misses Instruction Miss penalty
Cache Performance Example Given I-cache miss rate = 2% D-cache miss rate = 4% Miss penalty = 100 cycles Base CPI (ideal cache) = 2 Load & stores are 36% of instructions Caches 30 Miss cycles per instruction I-cache: 0.02 100 = 2 D-cache: 0.36 0.04 100 = 1.44 Actual CPI = 2 + 2 + 1.44 = 5.44 Ideal CPU is 5.44/2 =2.72 times faster
Average Access Time Caches 31 Hit time is also important for performance Average memory access time (AMAT) AMAT = Hit time + Miss rate Miss penalty Example CPU with 1ns clock, hit time = 1 cycle, miss penalty = 20 cycles, I-cache miss rate = 5% AMAT = 1 + 0.05 20 = 2ns 2 cycles per instruction
Performance Summary Caches 32 When CPU performance increased Miss penalty becomes more significant Decreasing base CPI Greater proportion of time spent on memory stalls Increasing clock rate Memory stalls account for more CPU cycles Can t neglect cache behavior when evaluating system performance
Associative Caches Caches 33 Fully associative Allow a given block to go in any cache entry Requires all entries to be searched at once Comparator per entry (expensive) n-way set associative Each set contains n entries Block number determines which set (Block number) modulo (#Sets in cache) Search all entries in a given set at once n comparators (less expensive)
Associative Cache Example Caches 34
Spectrum of Associativity Caches 35 For a cache with 8 entries
Associativity Example Caches 36 Compare 4-block caches Direct mapped vs 2-way set associative vs fully associative Block access sequence: 0, 8, 0, 6, 8 Direct mapped Block address Cache index Hit/miss Cache content after access 0 1 2 3 0 0 Miss Mem[0] 8 0 Miss Mem[8] 0 0 Miss Mem[0] 6 2 Miss Mem[0] Mem[6] 8 0 Miss Mem[8] Mem[6]
Associativity Example Caches 37 2-way set associative Block address Cache index Hit/miss Cache content after access Set 0 Set 1 0 0 miss Mem[0] 8 0 miss Mem[0] Mem[8] 0 0 hit Mem[0] Mem[8] 6 0 miss Mem[0] Mem[6] 8 0 miss Mem[8] Mem[6] Fully associative Block address Hit/miss Cache content after access 0 miss Mem[0] 8 miss Mem[0] Mem[8] 0 hit Mem[0] Mem[8] 6 miss Mem[0] Mem[8] Mem[6] 8 hit Mem[0] Mem[8] Mem[6]
How Much Associativity Caches 38 Increased associativity decreases miss rate But with diminishing returns Simulation of a system with 64KB D-cache, 16-word blocks, SPEC2000 1-way: 10.3% 2-way: 8.6% 4-way: 8.3% 8-way: 8.1%
Set Associative Cache Organization Caches 39
Replacement Policy Caches 40 Direct mapped: no choice Set associative Prefer non-valid entry, if there is one Otherwise, choose among entries in the set Least-recently used (LRU) Choose the one unused for the longest time Simple for 2-way, manageable for 4-way, too hard beyond that Random Gives approximately the same performance as LRU for high associativity
Multilevel Caches Caches 41 Primary cache attached to CPU Small, but fast Level-2 cache services misses from primary cache Larger, slower, but still faster than main memory Main memory services L-2 cache misses Some high-end systems include L-3 cache
Multilevel Cache Example Caches 42 Given CPU base CPI = 1, clock rate = 4GHz Miss rate/instruction = 2% Main memory access time = 100ns With just primary cache Miss penalty = 100ns/0.25ns = 400 cycles Effective CPI = 1 + 0.02 400 = 9
Example (cont.) Caches 43 Now add L-2 cache Access time = 5ns Global miss rate to main memory = 0.5% Primary miss with L-2 hit Penalty = 5ns/0.25ns = 20 cycles Primary miss with L-2 miss Extra penalty = 400 cycles CPI = 1 + 0.02 20 + 0.005 400 = 3.4 Performance ratio = 9/3.4 = 2.6
Multilevel Cache Considerations Caches 44 Primary cache Focus on minimal hit time L-2 cache Focus on low miss rate to avoid main memory access Hit time has less overall impact Results L-1 cache usually smaller than a single cache L-1 block size smaller than L-2 block size