Recommended JTAG Circuitry for Debug with Intel Xscale Microarchitecture Application Note June 2001 Document Number: 273538-001
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Contents Contents 1.0 Introduction...5 2.0 Requirements...5 3.0 JTAG Signals / Header...6 4.0 System Requirements...7 5.0 Hardware Requirements...8 5.1 Macraigor Raven* and Wind River Systems visionprobe* / visionice*...8 5.2 ARM* Multi-ICE*...8 6.0 References...9 Figures 1 JTAG Header...6 2 Example JTAG Signals at Power-Up...7 3 Example JTAG Signals at Debug Start-Up...7 4 Example Power-Up Circuit for ntrst...8 Tables Application Note 3
Contents Revision History Date Revision Description June 2001 001 Initial release. 4 Application Note
Introduction 1.0 Introduction Certain restrictions exist in order to use JTAG based debuggers with the Intel XScale microarchitecture (ARM* Architecture compliant). This is primarily due to the Tap Controller reset requirements of the Intel 80200 processor with Intel XScale microarchitecture and the reset requirements of specific JTAG debuggers. The following sections outline these requirements along with suggestions for circuitry to alleviate potential problems. 2.0 Requirements The Intel 80200 processor with Intel XScale microarchitecture, like many others, requires that ntrst (Tap Reset) is asserted low during power up for at least 32 core clock cycles. This is to ensure a fully initialized boundary scan chain. Failure to comply with this requirement may result in spurious behavior of the application. The ARM Multi-ICE JTAG debugger requires that ntrst is always weakly pulled high. This requirement stems from the fact that the debugger can only assert ntrst (drive low). Both reset signals coming from the Multi-ICE (ntrst and nsrst) are open collector and must be weakly pulled high in order to avoid unintentional resets (System or TAP). Application Note 5
JTAG Signals / Header 3.0 JTAG Signals / Header Figure 1 is the pin definition (20-pin standard ARM connector) for JTAG (See specific Product Design Guide for part number information). Figure 1. JTAG Header VTref 1 2 Vsupply ntrst 3 4 TDI 5 6 TMS 7 8 TCK 9 10 RTCK 11 12 TD0 13 14 nsrst 15 16 DBGRQ 17 18 DGBACK 19 20 A8982-01 The ARM Multi-ICE debugger along with the Macraigor Raven* and Wind River Systems visionprobe* / visionice* utilize this connector. The main difference to be noted is the specific implementation of ntrst for each debugger. The Macraigor Raven implementation actively drives ntrst (high and low). The Wind River Systems visionprobe / visionice can configure ntrst active or open collector (only drive low). ARM Multi-ICE is configured as open collector only. 6 Application Note
System Requirements 4.0 System Requirements In order to successfully invoke a debug session, the JTAG debug unit must be able to control ntrst and nsrst independently. The ntrst signal allows the debugger to get the TAP controller in a known state. The nsrst signal allows the debugger to control system/processor reset in order to download the debug handler via the JTAG interface. See Figure 2, Example JTAG Signals at Power-Up and Figure 3, Example JTAG Signals at Debug Start-Up. Figure 2. Note: Figure 2 and Figure 3 are examples and do not reflect actual signal timings. Example JTAG Signals at Power-Up VCC ntrst nsrst TCK TMS TDI TD0 A8978-01 Figure 3. Example JTAG Signals at Debug Start-Up VCC ntrst nsrst TCK TMS TDI TD0 A8979-01 Application Note 7
Hardware Requirements 5.0 Hardware Requirements Due to the conflicting requirements of Multi-ICE and the Intel 80200 processor, it is necessary to incorporate a circuit that can drive ntrst low at power up and weakly pull it high at all other times. This section details the circuits required for ntrst when using the Macraigor Raven, Wind River Systems visionprobe / visionice, and ARM Multi-ICE. Note: This section does not discuss circuitry needed for nsrst, due to varying system level requirements. 5.1 Macraigor Raven* and Wind River Systems visionprobe* / visionice* Both the Macraigor Raven and Wind River Systems visionprobe / visionice (when configured as active) do not require any special power-up circuitry. Simply, the requirement is that ntrst is weakly pulled down at the processor. It is suggested that the value of the pull-down resistor is 10kΩ or greater. The value of this resistor should be confirmed with the JTAG debugger manufacturer to ensure optimal performance. 5.2 ARM* Multi-ICE* The ARM Multi-ICE debugger requires special power-up circuitry due to the open collector implementation of the ntrst signal. This power-up circuit must ensure that ntrst is asserted (low)atpoweronandweaklypulledhighthereafter.seefigure 4, Example Power-Up Circuit for ntrst. This circuit is a universal solution and will work with other JTAG debug systems. Figure 4. Example Power-Up Circuit for ntrst ntrst-dgb 3.3 V 3.3 V 1 kω 3 MR# RESET# 2 220Ω ntrst 4 VCC 1 0.01µF MAX811S A8980-01 8 Application Note
References 6.0 References 1. Multi-ICE System Design Considerations Application Note 72 (http://www.arm.com/) 2. Intel 80310 I/O Processor Chipset with Intel XScale Microarchitecture Design Guide (http://developer.intel.com/design/iio/docs/iop310.htm) 3. Intel 80200 Processor Evaluation Platform Board Schematics (http://proto-cps.jf.intel.com/design/iio/docs/iop310.htm) 4. Max811/812 Datasheet (http://www.maxim-ic.com/) Application Note 9
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