Last (family) name: Answer Key First (given) name: Student I.D. #: Department of Electrical and Computer Engineering University of Wisconsin - Madison ECE 551 Digital System Design and Synthesis Midterm Exam Thursday, October 24, 2002 1:00--2:15PM (75 minutes) Instructions: 1. Open textbook examination, plus two 8.5x 11 note sheets allowed. 2. Five points penalty if fail to enter name or ID number. 3. No one shall leave room during last 5 minutes of the examination. 4. Upon announcement of the of the exam, stop writing on the exam paper immediately. Pass the exam to isles to be picked up by the instructor. The instructor will announce when to leave the room. 5. Failure to follow instructions may result in forfeiture of your exam and will be handled according to UWS 14 Academic misconduct procedures. Problem Points Score 1 18 2 20 3 16 4 10 5 12 6 12 Total 88 Solution notes: Answers are given in boxes. For many questions, multiple answers are possible. ECE 551 Midterm Exam 10/31/02 1
1. (18 points) General Verilog questions. (a) ( 4 pts) Give the result of each Verilog expression (in binary) for the following inputs: A = 4 b0011, B = 3 b011, and C = 3 b101. A + (B C); 1010 ~& A; 1 (A = = B)? B : C; 011 {A, {2{C}}; _0011_101_101 (b) (3 pts) Briefly, explain how a wand differs from a wor. A wand is forced to zero if any driver to it is zero, while a wor is forced to one if any driver to it is one. (c) (2 pts) Write a Verilog statement that declares a 6-bit register constant, C_24, with the decimal value 24. parameter C_24 = 6 d24; (d) (2 pts) Write Verilog code that declares an 8-bit register, R_H38, and initially assigns it the hexadecimal value 38. reg [7:0] R_H38; initial R_H38 = 8 h38;. (e) (4 pts) Complete the following clk_gen module, which generates a clock signal that initially goes to zero for 15 ns, then goes to one for 5 ns, and then repeats this pattern indefinitely. Your module can only use one initial statement. module clk_gen; reg clock; initial begin clock = 0; forever begin #15 clock = 1; #5 clock = 0; module; ECE 551 Midterm Exam 10/31/02 2
(f) (3 pts) Give the instantiation of an array of five 3-input AND gates (with inputs a, b, and c and output y, and the instance name A3), where each AND gate has a falling delay of 12 time units and a rising delay of 9 time units. Assume a, b, c, and d are each 5-bit wires. and #(9, 12) A3[0:4] (y, a, b, c); 2. (20 points) Verilog Coding Styles and Timing Specifications Below is an RTL description for a circuit. module RTL_circuit(x, y, a, b, c, d); parameter x_delay = 3, y_delay = 7; input a, b, c, d; output x, y; assign #y_delay y = (a b) & (c ~d); assign #x_delay x = a ^~ b; module (a) (3 points) Give a Verilog statement that instantiates the above RTL_circuit, with the instance name RTC, so that x has a delay of 7 time units and y has a delay of 5 time units. When you instantiate the circuit, use the same names for wires as is used in the module port list. RTL_circuit #(7, 5) RTC (x, y, a, b, c, d); (b) (6 pts) Rewrite the RTL_circuit using Verilog built-in primitives and structural Verilog. Your design should have the same overall delays (from module inputs to module outputs) as the original code. It is fine to let some gates have zero delay. Part of the module is done for you. module Struct_circuit(x, y, a, b, c, d); parameter x_delay = 3, y_delay = 7; input a, b, c, d; output x, y; signal n0, n1, n2, n3 or (n0, a, b); not(n1, d); or (n2, n1, c) and #x_delay (y, n0, n2); xnor #y_delay (x, a, b); module; ECE 551 Midterm Exam 10/31/02 3
(c) (3 pts) Draw a gate-level diagram for your module in (b). Label all nets on the diagram and write the delay of each gate inside the gate. Answers vary based on design in (b). (d) (6 points) Rewrite the RTL_circuit using behavioral Verilog. Use a specify section and specparam to specify the delays between inputs and outputs. Part of the module is done for you. module Behave_circuit(x, y, a, b, c, d); input a, b, c, d; output x, y; reg x, y; always @(a, b, c, d) begin y = (a b) & (c ~d); x = a ^~ b; specify specparam x_delay = 3, y_delay = 7; (a, b, c, d *> y) = y_delay; (a, b *> x) = x_delay; specify module; (e) (2 pts) Show how to use the timescale directive so that the x_delay and y_delay correspond to 0.3 ns and 0.7 ns, respectively and the simulator time step is 1 ps. timescale 100 ps / 1 ps ECE 551 Midterm Exam 10/31/02 4
3. (16 points) VHDL and Verilog Below is VHDL code for a common digital circuit. library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity circuit is generic (delay : Time := 6 ns); port ( clk, reset, en : in std_logic; q : out std_logic_vector(3 downto 0)); circuit; architecture behavioral of circuit is signal count : std_logic_vector(3 downto 0); begin process (reset, clk) begin if (reset event and (reset = 1 )) then count <= 0000 after delay; elsif (clk event and (clk = 1 ) and (en = 1 )) then count <= count + 0001 after delay; if; process; q <= count ; behavioral; (a) (2 points) Briefly tell what the circuit is or does. Is the reset signal synchronous or asynchronous? This circuit corresponds to a positive edge-triggered 4-bit counter with enable and reset signals. The circuit has a default delay of 6 ns. The reset signal is asynchronous. (b) (8 pts) Rewrite the circuit using behavioral Verilog. Use the same signal or variable names and basic flow of control as is used in the VHDL. timescale 1ns / 1 ns module circuit(clk, rst, en, q); parameter delay = 6; input clk, reset, en; output [3:0] q; reg [3:0] q; always@(posedge reset or posedge clk) begin if (reset == 1 b1) q <= #delay 4 b0000; else if ((clk == 1 b1) and (en == 1 b1)) q <= #delay q + 4 b0001; module; ECE 551 Midterm Exam 10/31/02 5
(c) (2 pts) What is an advantage that VHDL has over Verilog in terms of design reuse? VHDL supports packages and libraries, which allows components, functions, tasks, type declarations, etc. to be used by other entities. (d) (2 pts) What are two advantages that Verilog has over VHDL in terms of support for lowlevel constructs. Verilog supports both built-in primitives and user-define primitives. VHDL does not. (e) (2 pts) In what way is the VHDL generate statement more powerful than Verilog s ability to instantiate arrays of instances. In addition to allowing multiple instances to be instantiated, the VHDL generate statement allow allows multiple statements and processes to be generated. ECE 551 Midterm Exam 10/31/02 6
(4) (10 pts) Finite State Machines Below is a finite state machine for a simple branch predictor (hopefully those of you taking the ECE552 midterm today will appreciate this problem J ). reset taken = 1 00 predict = 1 taken = 0 taken = 1 01 predict = 1 taken = 1 taken = 0 11 predict = 0 taken = 1 taken = 0 10 predict = 0 taken = 0 (a) (2 pts) Does the above finite state machine correspond to a Mealy machine or a Moore machine. A Moore machine, since outputs only dep on the current state, not on inputs. (b) (8 pts) Write behavioral Verilog code that implements this state machine. Your code should use a single behavior for the state register, next-state logic, and output logic. Use the signal or register names and state assignments given on the above graph. Feel free to use the back of the previous sheet to write your code. module branch_predict(predict, taken, reset, clk); input taken, reset, clk; output predict; reg predict; reg [1:0] state; parameter s0 = 2 b00, s1 = 2 b01, s2 = 2 b10, s3 = 2 b11; always@(posedge clk or reset) begin if (reset = 1 b1) state == s0; else case (state) // determine next state s0: if (taken == 1 b0) state = s1; s1: if (taken == 1 b0) state = s2; else state = s0; s2: if (taken == 1 b1) state = s3; s3: if (taken == 1 b0) state = s2; else state = s0; case case (state) // set predict output based on state s0, s1: predict = 1 b1; s2, s3 : predict = 1 b0; default : predict = 1 bx; case module; ECE 551 Midterm Exam 10/31/02 7
(5) (12 pts) User-Defined Primitives (UDPs) (A) (6 pts) Fill in the following table for a UDP that implements the Boolean equation y = d(a b + c) if any input is equal to an x or z the output, y, should be x. Your table can only use five rows. Your table rows so should be ordered so that rows giving outputs of y=0 appear first. primitive comb_logic (y, a, b, c, d); output y; input a, b, c, d; table // a b c d : y b b b 0 : 0; 0 b 0 b : 0; // 0b01:0 sufficient b 1 0 b : 0; // b101:0 sufficient b b 1 1 : 1; 1 0 b 1 : 1; // 1001:1 sufficient table primitive (b) (2 pts). How many input/state combinations does the following row in a sequential UDP correspond to (or in other words, how many rows would the following row require if table shortcuts were not allowed). 1*2*2*3 = 12 // clk a b : state : q_out/next_state f b b :? : - (c) (2 pts) What are two advantages that UDPs have compared to Verilog modules? UDPs are faster to simulate and require less memory than Verilog modules. (d) (2 pts) What are two limitations of UDPs? UDPs can only have one output and they become difficult to write correctly when the number of inputs is large. ECE 551 Midterm Exam 10/31/02 8
(6) (12 pts) Test benches and Timing. (a) (6 pts) Write a Verilog testbench that applies inputs to exhaustively tests if the comb_logic module is working correctly. The testbench should apply a set of inputs and then wait for 5 ns before applying the next set of inputs. The testbench does not need to check the correctness of the result produced or write the result to a file. module comb_logic(q, r, s, t, u, v, w); input r, s, t, u, v, w; output q; reg q; always @(r, s, t, u, v, w) q = (r s) & (t u) & (v w); module; timescale 1ns/1ns module test_comb_logic; reg [5:0] x; comb_logic C1(q, x[5], x[4], x[3], x[2], x[1], x[0]); initial begin x = = 6 b000000; repeat (62) #5 x = x + 6b 000001; module (b) (6 pts) Give values for a, b, c, and d in the following table. Only show times at which the values change (including time 0). module make_waves; integer a, b, c, d; initial begin a = 0; b = 1; c = 2; d = 0; #1 a = 1; #3 b = 2; #2 c = b; always (a, b, c) d <= #3 a + b + c; module; Note: Time 2 is missing in the table. It is not needed. Although c is assigned a 2 at time 6, this is the same value it had previously, so no change occurs. time a b c d time a b c d 0 0 1 2 0 6 1 1 7 5 3 3 8 4 2 4 9 5 10 ECE 551 Midterm Exam 10/31/02 9