Digital System Design II

Digital System Design II 数字系统设计 II Peng Liu ( 刘鹏 ) Dept. of Info. Sci. & Elec. Engg. Zhejiang University liupeng@zju.edu.cn

Lecture 2 MIPS Instruction Set Architecture 2

Textbook reading MIPS ISA 2.1-2.4 Look at how instructions are defined and represented What is an instruction set architecture (ISA)? Interplay of C and MIPS ISA Components of MIPS ISA Register operands Memory operands Arithmetic operations Control flow operations 3

5 Components of any Computer Computer Processor Memory Devices Keyboard, Mouse Control ( brain ) Datapath ( brawn ) (where programs, data live when running) Input Output Disk (where programs, data live when not running) Display, Printer 4

Computer (All Digital Systems) Are At Their Core Pretty Simple Computers only work with binary signals Signal on a wire is either 0, or 1 Usually called a bit More complex stuff (numbers, characters, strings, pictures) Must be built from multiple bits Built out of simple logic gates that perform boolean logic AND, OR, NOT, And memory cells that preserve bits over time Flip-flops, registers, SRAM cells, DRAM cells, To get hardware to do anything, need to break it down to bits Stings of bits that tell hardware what to do are called instructions A sequence of instructions called machine language program (machine code) 5

Hardware/Software Interface The Instruction Set Architecture (ISA) defines what instructions do MIPS, Intel IA32 (x86), Sun SPARC, PowerPC, IBM 390, Intel IA64 These are all ISAs Many different implementations can implement same ISA (family) 8086,386, 486, Pentium, Pentium II, Pentium 4 implement IA32 Of course they continue to extend it, while maintaining binary compatibility ISA last a long time X86 has been in use since the 70s IBM 390 started as IBM 360 in 60s 6

Running An Application 7

MIPS ISA MIPS semiconductor company that built one of the first commercial RISC architectures Founded by J.Hennessy We will study the MIPS architecture in some detail in this class Why MIPS instead of Intel 80x86? MIPS is simple, elegant and easy to understand X86 is ugly and complicated to explain X86 is dominant on desktop MIPS is prevalent in embedded applications as processor core of system on chip (SOC) 8

C vs MIPS Programmers Interface C MIPS I ISA Registers 32 32b integer, R0=0 32 32b single FP Memory local variables global variables 16 64b double FP PC and special registers 2 32 linear array of bytes Data types int, short, char, unsigned, float, double, aggregate data types, pointers word (32b), byte (8b), half-word (16b) single FP (32b), double FP (64b) Arithmetic operators +, -, *, %, ++, <, etc. add, sub, mult, slt, etc. Memory access a, *a, a[i], a[i][j] lw, sw, lh, sh, lb, sb Control If-else, while, do-while, for, switch, procedure call, return branches, jumps, jump and link 9

MIPS Processor History 10

Memory-memory ISA Why Have Registers? ALL HLL variables declared in memory Why not operate directly on memory operands? E.g. Digital Equipment Corp (DEC) VAX ISA Benefits of registers Smaller is faster Multiple concurrent accesses Shorter names Load-Store ISA Arithmetic operations only use register operands Data is loaded into registers, operated on, and stored back to memory All RISC instruction sets 11

Using Registers Registers are a finite resource that needs to be managed Programmer Compilers: register allocation Goals Keep data in registers as much as possible Always use data still in registers if possible Issues Finite number of registers available Spill register to memory when all register in use Arrays Data is too large to store in registers What s the impact of fewer or more registers? 12

Register Naming Registers are identified by a $<num> By convention, we also give them names $zero contains the hardwired value 0 $v0, $v1 are for results and expression evaluation $a0-$a3 are for arguments $s0, $s1, $s7 are for save values $to, $t1, $t9 are for temporary values The others will be introduced as appropriate Compilers use these conventions to simplify linking 13

Assembly Instructions The basic type of instruction has four components: 1. Operation name 2. Destination operand 3. 1 st source operand 4. 2 nd source operand add dst, src1, src2 # dst = src1 + src2 dst, src1, and src2 are register names ($) What do these instructions do? - add $1, $1, $1 14

C Example Simple C procedure: sum_pow2 = 2 b+c 1:int sum_pow2 (int b, int c) 2:{ 3: int pow2[8] = {1, 2, 4, 8, 16, 32, 64, 128}; 4: int a, ret; 5: a = b + c; 6: if (a < 8) 7: ret = pow2[a]; 8: else 9: ret = 0; 10: return (ret); 11:} 15

Arithmetic Operators Consider line 5, C operation for addition a = b + c; Assume the variables are in register $1-$3 respectively. The add operator using registers add $1, $2, $3 # a = b +c Use the sub operator for a=b-c in MIPS sub $1, $2, $3 # a = b - c But we know that variables a,b, and c really start in some memory location Will add load & store instruction soon 16

Complex Operations What about more complex statements? a = b + c + d e; Break into multiple instructions add $t0, $s1, $s2 # $t0 = b + c add $t1, $t0, $s3 # $t1 = $t0 + d sub $s0, $t1, $s4 # a = $t1 - e 17

Signed & Unsigned Number If given b[n-1:0] in a register or in memory Unsigned value value n 1 b i 0 i 2 i Signed value (2 s complement) ( n 2 n 1 12 ) n i i 2 i 0 value b b 18

Unsigned & Signed Numbers Example values 4 bits Unsigned: [0, 2 4-1] Signed : [ -2 3, 2 3-1] Equivalence Same encoding for non-negative values Uniqueness Every bit pattern represents unique integer value Not true with sign magnitude 19

Arithmetic Overflow 20

Constants Often want to be able to specify operand in the instruction: immediate or literal Use the addi instruction addi dst, src1, immediate The immediate is a 16 bit signed value between -215 and 215-1 Sign-extended to 32 bits Consider the following C code a++; The addi operator addi $s0, $s0, 1 # a = a + 1 21

Memory Data Transfer Data transfer instructions are used to move data to and from memory. A load operation moves data from a memory location to a register and a store operation moves data from a register to a memory location. 22

Data Transfer Instructions: Loads Data transfer instructions have three parts Operator name (transfer size) Destination register Base register address and constant offset Lw dst, offset (base) Offset value is a singed constant 23

Memory Access All memory access happens through loads and stors Aligned words, half-words, and bytes More on this later today Floating Point loads and stores for accessing FP registers Displacement based addressing mode 24

Consider the example Loading Data Example a = b + *c; Use the lw instruction to load Assume a($s0), b($s1), c($s2) lw $t0, 0 ($s2) # $t0 = Memory[c] add $s0, $s1, $t0 # a = b + *c 25

Accessing Arrays Arrays are really pointers to the base address in memory Address of element A[0] Use offset value to indicate which index Remember that addresses are in bytes, so multiply by the size of the element Consider the integer array where pow2 is the base address With this compiler on this architecture, each int requires 4 bytes The data to be accessed is at index 5: pow2[5] Then the address from memory is pow2 + 5*4 Unlike C, assembly does not handle pointer arithmetic for you! 26

Array Memory Diagram 27

Array Example 28

Complex Array Example 29

Storing Data Storing data is just the reverse and the instruction is nearly identical. Use the sw instruction to copy a word from the source register to an address in memory. sw src, offset (base) Offset value is signed 30

Consider the example Storing Data Example *a = b + c; Use the sw instruction to store add $ t0, $s1, $s2 sw $t0, 0($s0) # $t0 = b + c # Memory[s0] = b + c 31

Consider the example a[3] = b + c; Storing to an Array Use the sw instruction offset add $t0, $s1, $s2 sw $t0, 12($s0) # $t0 = b + c # Memory[a[3]] = b + c 32

Complex Array Storage Consider the example a [i] = b + c; Use the sw instruction offset add $t0, $s1, $s2 # $t0 = b + c sll $t1, $s3, 2 # $t1 = 4 * I add $t2, $s0, $t1 #t2 = a + 4*I sw $t0, 0($t2) # Memory[a[i]]= b + c 33

A short Array Example ANSI C requires a short to be at least 16 bits and no longer than an int, but does not define the exact size For our purposes, treat a short as 2 bytes So, with a short array c[7] is at c + 7*2, shift left by 1 34

MIPS Integer Load/Store 35

Alignment Restrictions 36

Alignment Restrictions (cont) 37

Memory Mapped I/O Data transfer instructions can be used to move data to and from I/O device registers A load operation moves data from an I/O device to a CPU register and a store operation moves data from a CPU register to an I/O device register. 38

Endianess: Big or Little Question: what is the order of bytes within a word? Big endian: Address of most significant byte == address of word IBM 360, Motorola 68K, MIPS, SPARC Little endian: Address of least significant byte == address of word Intel x86, ARM, DEC Vax & Alpha, Important notes Endianess matters if you store words and load byte or communicate between different systems Most modern processors are bi-endian (configuration register) For entertaining details, read On holy wars and a plea for peace 39

Changing Control Flow One of the distinguishing characteristics of computers is the ability to evaluate conditions and change control flow If-then-else Loops Case statements Control flow instructions: two types Conditional branch instructions are known as branches Unconditional changes in the control flow are called jumps The target of the branch/jump is a label 40

Conditional: Equality The simplest conditional test is the beq instruction for equality beq reg1, reg2, label Consider the code if ( a == b ) go to L1; // do something L1: //continue Use the beq instruction beq $s0, $s1, L1 # do something L1: #continue 41

Conditional: Not equal The simplest conditional test is the bne instruction for equality bne reg1, reg2, label Consider the code if ( a!= b ) go to L1; // do something L1: //continue Use the bne instruction bne $s0, $s1, L1 # do something L1: #continue 42

Unconditional: Jumps The j instruction jumps to a label j label 43

If-then-else Example 44

If-then-else Solution 45

Other Comparisons Other conditional arithmetic operators are useful in evaluating conditional < > <= expressions using <, >, <=, >= Use compare instruction to set register to 1 when condition met Consider the following C code if (f < g) goto Less; Solution slt $t0, $s0, $s1 # $t0 = 1 if $s0 < $s1 bne $t0, $zero, Less # Goto Less if $t0!= 0 46

MIPS Comparisons 47

C Example 48

sum_pow2 Assembly 49

MIPS Jumps & Branches 50

Support for Simple Branches Only Notice that there is no branch less than instruction for comparing two registers? The reason is that such an instruction would be too complicated and might require a longer clock cycle time Therefore, conditionals that do not compare against zero take at least two instructions where the first is a set and the second is a conditional branch As we ll see later, this is a design trade-off Less time per instruction vs. fewer instructions How do you decide what to do? Other RISC ISAs made a different choice. 51

Consider a while loop While (A[i] == k) i = i + j; While Loop in C Assembly loop Assume i = $s0, j = $s1, k = $s2 Loop: sll $t0, $s0, 2 #$t0 = 4 *i addu $t1, $t0, $s3 # $t1 = &(A[i]) lw $t2, 0($t1) # $t2 = A[i] bne $t2, $s2, Exit # goto Exit if!= addu $s0, $s0, $s1 # i = i + j j Loop # goto Loop Exit Basic Block Maximal sequence of instructions with out branches or branch targets 52

Improve Loop Efficiency 53

Improved Loop Solution Remove extra jump loop body j Cond # goto Cond Loop: addu $s0, $s0, $s1 # i = i + j Cond: sll $t0, $s0, 2 # $t0 = 4 * i addu $t1, $t0, $s3 # $t1 = &(A[i]) lw $t2, 0($t1) # $t2 = A[i] beq $t2, $s2, Loop # goto Loop if == Exit: Reduced loop from 6 to 5 instructions Even small improvements important if loop executes many times 54

Machine Language Representation Instructions are represented as binary data in memory Stored program Von Neumann Simplicity One memory system Same addresses used for branches, procedures, data, etc. The only difference is how bits are interpreted What are the risks of this decision? Binary compatibility (backwards) Commercial software relies on ability to work on next generation hardware This leads to very long life for an ISA 55

MIPS Instruction Encoding MIPS instructions are encoded in different forms, depending upon the arguments R-format, I-format, J-format MIPS architecture has three instruction formats, all 32 bits in length Regularity is simpler and improves performance A 6 bit opcode appears at the beginning of each instruction Control logic based on decode instruction type 56

R-Format Instructions (1/2) Define fields of the following number of bits each: 6 + 5 + 5 + 5 + 5 + 6 = 32 6 5 5 5 5 6 For simplicity, each field has a name: opcode rs rt rd shamt funct 57

R-Format Instructions (2/2) More fields: rs (Source Register): generally used to specify register containing first operand rt (Target Register): generally used to specify register containing second operand (note that name is misleading) rd (Destination Register): generally used to specify register which will receive result of computation 58

J-Format Instructions (1/2) Define fields of the following number of bits each: 6 bits 26 bits As usual, each field has a name: opcode target address Key Concepts Keep opcode field identical to R-format and I-format for consistency. Combine all other fields to make room for large target address. 59

J-Format Instructions (2/2) Summary: New PC = { PC[31..28], target address, 00 } Understand where each part came from! Note: In Verilog, {,, } means concatenation { 4 bits, 26 bits, 2 bits } = 32 bit address { 1010, 11111111111111111111111111, 00 } = 10101111111111111111111111111100 We use Verilog in this class 60

Instruction Formats I-format: used for instructions with immediates, lw and sw (since the offset counts as an immediate), and the branches (beq and bne), (but not the shift instructions; later) J-format: used for j and jal R-format: used for all other instructions It will soon become clear why the instructions have been partitioned in this way. 61

R-Format Example MIPS Instruction: add $8,$9,$10 Decimal number per field representation: 0 9 10 8 0 32 Binary number per field representation: 000000 01001 01010 01000 00000 100000 hex representation: 012A 4020 hex hex decimal representation: 19,546,144 ten On Green Card: Format in column 1, opcodes in column 3 62

MIPS I Operation Overview Arithmetic Logical: Add, AddU, Sub, SubU, And, Or, Xor, Nor, SLT, SLTU AddI, AddIU, SLTI, SLTIU, AndI, OrI, XorI, LUI SLL, SRL, SRA, SLLV, SRLV, SRAV Memory Access: LB, LBU, LH, LHU, LW, LWL,LWR SB, SH, SW, SWL, SWR 63

MIPS Logical Instructions Instruction Example Meaning Comment and and $1,$2,$3 $1 = $2 & $3 3 reg. operands; Logical AND or or $1,$2,$3 $1 = $2 $3 3 reg. operands; Logical OR xor xor $1,$2,$3 $1 = $2 ^ $3 3 reg. operands; Logical XOR nor nor $1,$2,$3 $1 = ~($2 $3) 3 reg. operands; Logical NOR and immediate andi $1,$2,10 $1 = $2 & 10 Logical AND reg, constant or immediate ori $1,$2,10 $1 = $2 10 Logical OR reg, constant xor immediate xori $1, $2,10 $1 = ~$2 &~10 Logical XOR reg, constant shift left logical sll $1,$2,10 $1 = $2 << 10 Shift left by constant shift right logical srl $1,$2,10 $1 = $2 >> 10 Shift right by constant shift right arithm. sra $1,$2,10 $1 = $2 >> 10 Shift right (sign extend) shift left logical sllv $1,$2,$3 $1 = $2 << $3 Shift left by variable shift right logical srlv $1,$2, $3 $1 = $2 >> $3 Shift right by variable shift right arithm. srav $1,$2, $3 $1 = $2 >> $3 Shift right arith. by variable Q: Can some multiply by 2 i? Divide by 2 i? Invert? 64

M I P S Reference Data :CORE INSTRUCTION SET (1) NAME MNE- MON-IC FOR- MAT OPERATION (in Verilog) OPCODE/FU NCT (hex) Add add R R[rd] = R[rs] + R[rt] (1) 0 / 20 hex Add Immediate addi I R[rt] = R[rs] + SignExtImm (1)(2) 8 hex Branch On Equal beq I if(r[rs]==r[rt]) PC=PC+4+ BranchAddr (4) 4 hex (1) May cause overflow exception (2) SignExtImm = { 16{immediate[15]}, immediate } (3) ZeroExtImm = { 16{1b 0}, immediate } (4) BranchAddr = { 14{immediate[15]}, immediate, 2 b0} 65

MIPS Data Transfer Instructions Instruction sw 500($4), $3 sh 502($2), $3 sb 41($3), $2 lw $1, 30($2) lh $1, 40($3) lhu $1, 40($3) lb $1, 40($3) lbu $1, 40($3) Comment Store word Store half Store byte Load word Load halfword Load halfword unsigned Load byte Load byte unsigned lui $1, 40 Load Upper Immediate (16 bits shifted left by 16) Q: Why need lui? LUI R5 R5 0000 0000 66

Multiply / Divide Start multiply, divide MULT rs, rt MULTU rs, rt DIV rs, rt DIVU rs, rt Move result from multiply, divide MFHI rd MFLO rd Move to HI or LO MTHI rd MTLO rd Registers HI LO 67

MIPS Arithmetic Instructions Instruction Example Meaning Comments add add $1,$2,$3 $1 = $2 + $3 3 operands; exception possible subtract sub $1,$2,$3 $1 = $2 $3 3 operands; exception possible add immediate addi $1,$2,100 $1 = $2 + 100 + constant; exception possible add unsigned addu $1,$2,$3 $1 = $2 + $3 3 operands; no exceptions subtract unsigned subu $1,$2,$3 $1 = $2 $3 3 operands; no exceptions add imm. unsign. addiu $1,$2,100 $1 = $2 + 100 + constant; no exceptions multiply mult $2,$3 Hi, Lo = $2 x $3 64-bit signed product multiply unsigned multu$2,$3 Hi, Lo = $2 x $3 64-bit unsigned product divide div $2,$3 Lo = $2 $3, Lo = quotient, Hi = remainder Hi = $2 mod $3 divide unsigned divu $2,$3 Lo = $2 $3, Unsigned quotient & remainder Hi = $2 mod $3 Move from Hi mfhi $1 $1 = Hi Used to get copy of Hi Move from Lo mflo $1 $1 = Lo Used to get copy of Lo Q: Which add for address arithmetic? Which add for integers? 68

Green Card: ARITHMETIC CORE INSTRUCTION SET (2) NAME MNE- MON-IC FOR- MAT OPERATION (in Verilog) OPCODE/FMT / FT/ FUNCT (hex) Branch On FP True bc1t FI if (FPcond) PC=PC + 4 + BranchAddr (4) 11/8/1/-- Load FP Single lwc1 I F[rt] = M[R[rs] + SignExtImm] (2) 11/8/1/-- Divide div R Lo=R[rs]/R[rt]; Hi=R[rs]%R[rt] 31/--/--/-- 69

When does MIPS Sign Extend? When value is sign extended, copy upper bit to full value: Examples of sign extending 8 bits to 16 bits: 00001010 00000000 00001010 10001100 11111111 10001100 When is an immediate operand sign extended? Arithmetic instructions (add, sub, etc.) always sign extend immediates even for the unsigned versions of the instructions! Logical instructions do not sign extend immediates (They are zero extended) Load/Store address computations always sign extend immediates Multiply/Divide have no immediate operands however: unsigned treat operands as unsigned The data loaded by the instructions lb and lh are extended as follows ( unsigned don t extend): lbu, lhu are zero extended lb, lh are sign extended Q: Then what is does add unsigned (addu) mean since not immediate? 70

MIPS Compare and Branch Compare and Branch BEQ rs, rt, offset if R[rs] == R[rt] then PC-relative branch BNE rs, rt, offset <> Compare to zero and Branch BLEZ rs, offset if R[rs] <= 0 then PC-relative branch BGTZ rs, offset > BLT < BGEZ >= BLTZAL rs, offset if R[rs] < 0 then branch and link (into R 31) BGEZAL >=! Remaining set of compare and branch ops take two instructions Almost all comparisons are against zero! 71

MIPS jump, branch, compare Instructions Instruction Example Meaning branch on equal beq $1,$2,100 if ($1 == $2) go to PC+4+100 Equal test; PC relative branch branch on not eq. bne $1,$2,100 if ($1!= $2) go to PC+4+100 Not equal test; PC relative set on less than slt $1,$2,$3 if ($2 < $3) $1=1; else $1=0 Compare less than; 2 s comp. set less than imm. slti $1,$2,100 if ($2 < 100) $1=1; else $1=0 Compare < constant; 2 s comp. set less than uns. sltu $1,$2,$3 if ($2 < $3) $1=1; else $1=0 Compare less than; natural numbers set l. t. imm. uns. sltiu $1,$2,100 if ($2 < 100) $1=1; else $1=0 Compare < constant; natural numbers jump j 10000 go to 10000 Jump to target address jump register jr $31 go to $31 For switch, procedure return jump and link jal 10000 $31 = PC + 4; go to 10000 For procedure call 72

Signed vs. Unsigned Comparison $1= 0 00 0000 0000 0000 0001 $2= 0 00 0000 0000 0000 0010 $3= 1 11 1111 1111 1111 1111 After executing these instructions: slt $4,$2,$1 ; if ($2 < $1) $4=1; else $4=0 slt $5,$3,$1 ; if ($3 < $1) $5=1; else $5=0 sltu $6,$2,$1 ; if ($2 < $1) $6=1; else $6=0 sltu $7,$3,$1 ; if ($3 < $1) $7=1; else $7=0 What are values of registers $4 - $7? Why? $4 = ; $5 = ; $6 = ; $7 = ; 73

MIPS Assembler Register Convention Name Number Usage Preserved across a call? $zero 0 the value 0 n/a $v0-$v1 2-3 return values no $a0-$a3 4-7 arguments no $t0-$t7 8-15 temporaries no $s0-$s7 16-23 saved yes $t18-$t19 24-25 temporaries no $sp 29 stack pointer yes $ra 31 return address yes caller saved callee saved On Green Card in Column #2 at bottom 74

Peer Instruction: $s3=i, $s4=j, $s5=@a Loop: addiu $s4,$s4,1 # j = j + 1 sll $t1,$s3,2 # $t1 = 4 * i addu $t1,$t1,$s5 # $t1 = @ A[i] lw $t0,0($t1) # $t0 = A[i] addiu $s3,$s3,1 # i = i + 1 slti $t1,$t0,10 # $t1 = $t0 < 10 beq $t1,$0, Loop # goto Loop slti $t1,$t0, 0 # $t1 = $t0 < 0 bne $t1,$0, Loop # goto Loop do j = j + 1 while ( ); What C code properly fills in the blank in loop on right? 1: A[i++] >= 10 2: A[i++] >= 10 A[i] < 0 3: A[i] >= 10 A[i++] < 0 4: A[i++] >= 10 A[i] < 0 5: A[i] >= 10 && A[i++] < 0 6 None of the above 75

Green Card: OPCODES, BASE CONVERSION, ASCII (3) MIPS opcode (31:26) (1) MIPS funct (5:0) (2) MIPS funct (5:0) Binary Decimal Hexadeci-mal ASCII (1) sll add.f 00 0000 0 0 NUL j srl mul.f 00 0010 2 2 STX lui sync floor.w.f 00 1111 15 f SI lbu and cvt.w.f 10 0100 36 24 $ (1) opcode(31:26) == 0 (2) opcode(31:26) == 17 ten (11 hex ); if fmt(25:21)==16 ten (10 hex ) f = s (single); if fmt(25:21)==17 ten (11 hex ) f = d (double) Note: 3-in-1 - Opcodes, base conversion, ASCII! 77

Green Card green card /n./ [after the "IBM System/360 Reference Data" card] A summary of an assembly language, even if the color is not green. For example, "I'll go get my green card so I can check the addressing mode for that instruction." www.jargon.net Image from Dave's Green Card Collection: http://www.planetmvs.com/greencard/ 78

Peer Instruction Which instruction has same representation as 35 ten? A. add $0, $0, $0 B. subu $s0,$s0,$s0 C. lw $0, 0($0) D. addi $0, $0, 35 E. subu $0, $0, $0 F. Trick question! Instructions are not numbers Registers numbers and names: 0: $0, 8: $t0, 9:$t1,..15: $t7, 16: $s0, 17: $s1,.. 23: $s7 Opcodes and function fields (if necessary) add: opcode = 0, funct = 32 subu: opcode = 0, funct = 35 addi: opcode = 8 lw: opcode = 35 opcode rs rt opcode rs rt rd shamt opcode rs rt offset opcode rs rt immediate opcode rs rt rd rd shamt shamt funct funct funct 79

Branch & Pipelines Time li $3, #7 sub $4, $4, 1 execute ifetch execute bz $4, LL ifetch execute Branch addi $5, $3, 1 ifetch execute Delay Slot LL: slt $1, $3, $5 Branch Target ifetch execute By the end of Branch instruction, the CPU knows whether or not the branch will take place. However, it will have fetched the next instruction by then, regardless of whether or not a branch will be taken. Why not execute it? 81

Delayed Branches li $3, #7 sub $4, $4, 1 bz $4, LL addi $5, $3, 1 subi $6, $6, 2 LL: slt $1, $3, $5 In the Raw MIPS, the instruction after the branch is executed even when the branch is taken This is hidden by the assembler for the MIPS virtual machine allows the compiler to better utilize the instruction pipeline (???) Jump and link (jal inst): Put the return addr. Into link register ($31): PC+4 (logical architecture) Delay Slot Instruction PC+8 physical ( Raw ) architecture delay slot executed Then jump to destination address 82

Filling Delayed Branches Branch: Inst Fetch Dcd & Op Fetch Execute execute successor even if branch taken! Then branch target or continue Inst Fetch Dcd & Op Fetch Inst Fetch Execute Single delay slot impacts the critical path Compiler can fill a single delay slot with a useful instruction 50% of the time. try to move down from above jump move up from target, if safe add $3, $1, $2 sub $4, $4, 1 bz $4, LL NOP... LL: add rd,... Is this violating the ISA abstraction? 83

Summary: Salient Features of MIPS I 32-bit fixed format inst (3 formats) 32 32-bit GPR (R0 contains zero) and 32 FP registers (and HI LO) partitioned by software convention 3-address, reg-reg arithmetic instr. Single address mode for load/store: base+displacement no indirection, scaled 16-bit immediate plus LUI Simple branch conditions compare against zero or two registers for =, no integer condition codes Delayed branch execute instruction after a branch (or jump) even if the branch is taken (Compiler can fill a delayed branch with useful work about 50% of the time) 84

And in conclusion... Continued rapid improvement in Computing 2X every 1.5 years in processor speed; every 2.0 years in memory size; every 1.0 year in disk capacity; Moore s Law enables processor, memory (2X transistors/chip/ ~1.5 ro 2.0 yrs) 5 classic components of all computers Control Datapath Memory Input Output Processor 85

MIPS Machine Instruction Review: Instruction Format Summary 86

Addressing Modes Summary Register addressing Operand is a register (e.g. ALU) Base/displacement addressing (ex. load/store) Operand is at the memory location that is the sum of a base register + a constant Immediate addressing (e.g. constants) Operand is a constant within the instruction itself PC-relative addressing (e.g. branch) Address is the sum of PC and constant in instruction (e.g. branch) Pseudo-direct addressing (e.g. jump) Target address is concatenation of field in instruction and the PC 87

Addressing Modes Summary 88

Readings: HomeWork Read Chapter 2.5-2.14, then Appendix C and D. 89

Acknowledgements These slides contain material from courses: UCB CS152. Stanford EE108B 90