SmartFusion2 MSS. DDR Memory Simulation

SmartFusion2 MSS DDR Memory Simulation

SmartFusion2 MSS DDR Memory Simulation Table of Contents Introduction...................................................................... 3 1 Design Testbench Setup for DDR Memory Simulation..................................... 4 Design Setup.............................................................................. 4 Testbench Setup - Memory Model Integration..................................................... 5 Testbench Example........................................................................ 11 2 BFM Simulation Setup for DDR Memory Simulation...................................... 14 Accessing DDR Memory Space and Base Addresses............................................. 14 3 DDR Memory Space Access Example................................................. 15 SmartFusion2 Example with Cortex-M3 as Master................................................ 15 IGLOO2 Example (AHB/AXI Fabric Master)..................................................... 16 Simulation Timescale and 3rd-party DDR Memory Simulation Model.................................. 17 A Product Support.................................................................. 18 Customer Service......................................................................... 18 Customer Technical Support Center........................................................... 18 Technical Support......................................................................... 18 Website................................................................................. 18 Contacting the Customer Technical Support Center............................................... 18 ITAR Technical Support..................................................................... 19 2

Introduction SmartFusion2 devices included embedded DDR controllers, intended to control an off-chip DDR memory. This document describes the steps required to simulate the configuration and usage of the DDR controller to access a DDR memory. To simulate a design with a DDR Memory: 1. Set up your design and testbench. 2. Set up BFM simulation (set DDR Memory read/write operations). 3. Run simulation. 3

1 Design Testbench Setup for DDR Memory Simulation Design Setup Begin your design setup by creating a design using System Builder or by writing HDL. Microsemi recommends using System Builder. When you use System Builder to build your design it automatically manages APB configuration bus setup and the DDR Controller connections. To set up your design from System Builder: 1. Include MDDR/FDDR in your top level design. In the System Builder GUI, select MDDR and FDDR in the Device Features page. 2. Configure the MDDR or FDDR in the System Builder Memories page. Specify or configure the parameters in the relevant tabs of the DDR Configurator (General, Memory Initialization, Memory Timing) per the type and features of the external DDR memory used in your design. The configuration shown in Figure 1-1 is used to configure the MDDR to access a DDR2 Memory, using a DDR PHY width of 16 bits, no ECC, a burst length of 8, and a DDR Memory settling time of 200 us. Note: If the DDR Memory model fails to initialize correctly, you may need to increase the settling time. Consult your DDR Memory vendor's documentation for settling time specifications. Figure 1-1 MDDR/FDDR Configurator in System Builder Alternatively, you can click Import Configuration to import an existing working Register file to configure the DDR controllers. 3. Proceed through the rest of the pages in System Builder to complete the top level System Builder block. The generated System Builder block will have the pads exposed at the top level for you to connect to the DDR memory block. 4

[Document Title] 4. Connect the Datapath bus in the SmartDesign Canvas (if necessary). This step involves connecting the AXI or AHB Bus interfaces of the MDDR/FDDR to the bus Master. This is necessary in the case of a fabric Master accessing the MDDR, or in any use case involving the FDDR. The Cortex-M3 has a hardwired connection to the MDDR. Therefore, if your design does not have any fabric Master, and does not have the Cortex-M3 accessing the FDDR, it is not necessary to set up the datapath between the Cortex-M3 and the MDDR. 5. Generate the top level design in SmartDesign Canvas. Testbench Setup - Memory Model Integration A correctly constructed Libero SoC design that uses a DDR Memory has a set of DDR pads exposed at the top level. For the MDDR, these pads are called MDDR _* (Figure 1-2). For the FDDR, they are called FDDR_*. These pads are intended to be connected to the DDR memory. Figure 1-2 MSS Instance in SmartDesign Showing MDDR DRAM PADs To simulate your application correctly you must integrate a memory model in the testbench (Figure 1-3). You can: Use Microsemi s DDR Memory Simulation Model and the SmartDesign testbench. Use a third-party DDR Memory Simulation model and the SmartDesign Testbench. 5

Use a third-party DDR Memory Simulation Model and a user HDL testbench. Figure 1-3 Testbench Overview Memory Model Integration Using Microsemi s DDR Memory Simulation Model and the SmartDesign Testbench Microsemi provides a DDR Memory Simulation Model (SimDRAM) for DDR memory simulation. This is a Microsemi IP in the Microsemi Repository and available for download in the Libero Catalog. It is a generic DDR memory simulation model that emulates DDR/DDR2/LPDDR DRAM (non-timing) functionality. To use the DDR Memory Simulation Model and SmartDesign testbench: 1. In the Design Flow window, click Create SmartDesign Testbench. 2. Enter a name for your testbench. A SmartDesign Testbench Canvas opens. 3. In the Catalog, select the Generic DDR Memory Simulation Model IP. Click and drag the IP onto the SmartDesign Testbench Canvas. You must select Simulation Mode in the Catalog to display the DDR Simulation Model IP. It is listed under Memory & Controllers. 4. Click and drag the DDR Memory Model into the SmartDesign Testbench Canvas. Figure 1-4 Generic DDR Memory Simulation Model 6

[Document Title] 5. Configure the SimDRAM model to match the MDDR/FDDR's parameters (Figure 1-5). Refer to the SimDRAM: Generic DDR Memory Simulation Core User Guide for details on how to configure the SimDRAM. Microsemi's DDR Memory Simulation Core can be configured to model the nontiming functionality of a DDR2, DDR3 or LPDDR. In all cases it models non-timing functionality. Figure 1-5 SimDRAM Configurator 6. Connect the MDDR/FDDR pads of the System Builder Block to the DDR_PADS of the SimDram_0 Instance (Figure 1-6, Figure 1-7 and Figure 1-8) Tie MDDR/FDDR_DQS_TMATCH_0_OUT and MDDR/FDDR_DQS_TMATCH_0_IN together if you are not using FIFO. Mark the output port of the MDDR Controller MDDR_RESET_N unused if your SimDRAM model is configured for DDR2. Connect this output port to DRAM_RESET_N of the SimDRAM model if it is configured for DDR3. 7

Mark output port DRAM_RDQS_N[1:0] of the SimDRAM model unused for DDR2. Figure 1-6 MDDR Controller and SimDRAM_0 (Configured as DDR2) Pad Connections Figure 1-7 MDDR Controller and SimDRAM_0 (Configured as DDR3) Pad Connections 8

[Document Title] Figure 1-8 MDDR Controller and SimDRAM_0 (Configured as LPDDR) Pad Connections 7. Click the Generate icon in the SmartDesign Testbench Canvas to generate the Testbench (Figure 1-9). Figure 1-9 Connecting the MDDR/FDDR Pads to Microsemi's DDR Memory Simulation Model on the SmartDesign Testbench Canvas The Stimulus Hierarchy window displays the Hierarchy of the SmartDesign Testbench that instantiates the System Builder Block and the SimDRAM DDR Simulation Model. It also generates an HDL 9

Testbench that is ready for use in simulation (Figure 1-10). Figure 1-10 Stimulus Hierarchy Window with the SmartDesign Testbench and Microsemi DDR Memory Model Use a Third-Party DDR Memory Simulation Model and the SmartDesign Testbench To use a third-party DDR Memory Simulation model and SmartDesign Testbench: 1. Obtain the DDR Memory Model from the DDR Memory vendor of your choice. This should correspond to the actual DDR Memory you intend to use in your application. 2. Import the third-party DDR Memory Simulation Model into the Libero SoC Project as a stimulus HDL file. 3. From the Design Flow window, invoke SmartDesign Testbench to create your top level SmartDesign Testbench and give it a name. 4. Click and drag the third-party DDR Memory Simulation Model (HDL file) into the SmartDesign Testbench canvas. 5. Connect the MDDR/FDDR pads of the System Builder block (DUT) to the third-party Memory Model. If the third-party DDR memory simulation model has an address bus width different than the MDDR/FDDR, you may have to slice the address bus and mark the extra address bits unused. 6. Click the Generate icon in the SmartDesign Testbench Canvas to generate the Testbench component. 10

[Document Title] Use a Third-Party DDR Memory Simulation Model and a User HDL Testbench To use a third-party DDR Memory Simulation model with a user HDL testbench: 1. Obtain the DDR Memory Model from the DDR Memory vendor of your choice. This should correspond to the actual DDR Memory you intend to use in your application. If you use System Builder, it will automatically generate a testbench for you in the following directory: <Project>/component/work/<top_level_name>/testbench.v(hd) 2. Modify the autogenerated HDL testbench (testbench.v or testbench.vhd) to connect the memory model as follows: Add an include statement to include the Memory Model HDL file. Instantiate the Memory Model in the testbench.v or testbench.vhd. Connect the MDDR/FDDR pad signals to the Memory Model instance. 3. If necessary: edit the timescale in the Verilog testbench to match the timescale used in your DDR simulation model. Testbench Example If you use a DDR Memory Simulation Model of your choice from a third-party vendor, you must edit the auto-generated HDL testbench to include the DDR Simulation Model in your design and make the connections to the Testbench. The following is a Verilog testbench that instantiates a DDR2 Memory Model and connects it to the DUT. // Created by Actel SmartDesign Tue Jan 24 22:09:24 2012 // Testbench Template // This is a basic testbench that instantiates your design with basic // clock and reset pins connected. If your design has special // clock/reset or testbench driver requirements then you should // copy this file and modify it. `timescale 1ps/1fs //Edit and use a timescale that matches the timescale of your model `include "ddr2.v" //Add the include statement to include the ddr2 memory model file module testbench; parameter SYSCLK_PERIOD = 10000; // 100MHz reg SYSCLK; reg NSYSRESET; // Input ports in M3_MDDR wire MDDR_DQS_TMATCH_0_IN; // Output ports in M3_MDDR wire [15:0] MDDR_ADDR; wire [2:0] MDDR_BA; wire MDDR_CAS_N; wire MDDR_CKE; wire MDDR_CLK; wire MDDR_CLK_N; wire MDDR_CS_N; wire MDDR_DQS_TMATCH_0_OUT; wire MDDR_ODT; wire MDDR_RAS_N; wire MDDR_RESET_N; 11

wire MDDR_WE_N; // Inout ports in M3_MDDR wire [1:0] MDDR_DM_RDQS; wire [15:0] MDDR_DQ; wire [1:0] MDDR_DQS; wire [1:0] MDDR_DQS_N; initial begin SYSCLK = 1'b0; NSYSRESET = 1'b0; end // Reset Pulse initial begin #(SYSCLK_PERIOD * 1000 ) NSYSRESET = 1'b1; end // 10MHz Clock Driver always @(SYSCLK) #(SYSCLK_PERIOD / 2.0) SYSCLK <=!SYSCLK; // Instantiate Unit Under Test: M3_MDDR_PI M3_MDDR_PI M3_MDDR_PI_0 ( // Inputs.MDDR_DQS_TMATCH_0_IN(MDDR_DQS_TMATCH_0_OUT),.DEVRST_N(NSYSRESET), ); // Outputs.MDDR_CAS_N(MDDR_CAS_N ),.MDDR_CKE(MDDR_CKE ),.MDDR_CLK(MDDR_CLK ),.MDDR_CLK_N(MDDR_CLK_N ),.MDDR_CS_N(MDDR_CS_N ),.MDDR_ODT( MDDR_ODT),.MDDR_RAS_N( MDDR_RAS_N ),.MDDR_RESET_N(MDDR_RESET_N),.MDDR_WE_N(MDDR_WE_N),.MDDR_ADDR(MDDR_ADDR),.MDDR_BA(MDDR_BA),.MDDR_DQS_TMATCH_0_OUT(MDDR_DQS_TMATCH_0_OUT), // Inouts.MDDR_DM_RDQS(MDDR_DM_RDQS),.MDDR_DQS(MDDR_DQS),.MDDR_DQS_N(MDDR_DQS_N),.MDDR_DQ(MDDR_DQ) // Instantiate DDR2: ddr2 Memory Model 12

[Document Title] ddr2 u_ddr2_16_i0 (.ck(mddr_clk),.ck_n(mddr_clk_n),.cke(mddr_cke),.cs_n(mddr_cs_n),.ras_n(mddr_ras_n ),.cas_n(mddr_cas_n),.we_n(mddr_we_n),.dm_rdqs(mddr_dm_rdqs[1:0]),.ba(mddr_ba),.addr(mddr_addr[13:0]),.dq(mddr_dq[15:0]),.dqs(mddr_dqs[1:0]),.dqs_n(mddr_dqs_n[1:0]),.rdqs_n(),.odt(mddr_odt) ); endmodule When you have correctly edited the testbench to include the DDR Memory Model and made the correct connections, the Stimulus Hierarchy window displays the User Testbench and the DDR Memory Model from the Third-Party Vendor (Figure 1-11). Figure 1-11 Stimulus Hierarchy with User-Generated Testbench and DDR Memory Model from a Third-Party Vendor 13

2 BFM Simulation Setup for DDR Memory Simulation Please refer to the SmartFusion2 FPGA Microcontroller Subsystem BFM Simulation Guide for general guidelines on BFM simulations for SmartFusion2 designs. Accessing DDR Memory Space and Base Addresses You can access DDR Memory from the following masters: Cortex-M3 (SmartFusion2 Only) HPDMA (SmartFusion2 and IGLOO2) AHB/AXI Fabric Master (SmartFusion2 and IGLOO2) The memory address space can be found in the Memory Mapping page (last page) of System Builder. During simulations, the base addresses are: MDDR (Memory Space): 0xA0000000-0xD0000000 FDDR (Memory Space): 0x0 (depending on which AHB/AXI slot the FDDR memory interface is connected to) 14

3 DDR Memory Space Access Example SmartFusion2 and IGLOO2 DDR simulation examples are provided below. SmartFusion2 Example with Cortex-M3 as Master The following is a user.bfm file that simulates writing and reading the MDDR (with Cortex M-3 as the master). #=========================================================== # Enter your BFM commands in this file. # # Syntax: # ------- # # memmap resource_name base_address; # # write width resource_name byte_offset data; # read width resource_name byte_offset; # readcheck width resource_name byte_offset data; # #=========================================================== memmap M_DDR0_SPACE_0 memmap M_DDR0_SPACE_1 memmap M_DDR0_SPACE_2 memmap M_DDR0_SPACE_3 0xA0000000; //Base Address from Data Sheet 0xB0000000; //Base Address from Data Sheet 0xC0000000; //Base Address from Data Sheet 0xD0000000; //Base Address from Data Sheet include "subsystem.bfm" procedure user_main; # perform subsystem initialization routine call subsystem_init; # add your BFM commands below: print "MDDR TEST STARTS"; write w M_DDR0_SPACE_0 0x0000 0xA1B2C3D4 ; write w M_DDR0_SPACE_0 0x0004 0x10100101 ; write w M_DDR0_SPACE_0 0x0008 0xD7D7E1E1 ; write w M_DDR0_SPACE_0 0x000C 0xA5DEF6E7 ; readcheck w M_DDR0_SPACE_0 0x0000 0xA1B2C3D4; readcheck w M_DDR0_SPACE_0 0x0004 0x10100101; readcheck w M_DDR0_SPACE_0 0x0008 0xD7D7E1E1 ; readcheck w M_DDR0_SPACE_0 0x000C 0xA5DEF6E7 ; write w M_DDR0_SPACE_1 0x0010 0xA1A2A3A4 ; write w M_DDR0_SPACE_1 0x0014 0xB1B2B3B4 ; write w M_DDR0_SPACE_1 0x0018 0xC1C2C3C4 ; write w M_DDR0_SPACE_1 0x001C 0xD1D2D3D4 ; readcheck w M_DDR0_SPACE_1 0x0010 0xA1A2A3A4 ; readcheck w M_DDR0_SPACE_1 0x0014 0xB1B2B3B4 ; readcheck w M_DDR0_SPACE_1 0x0018 0xC1C2C3C4 ; readcheck w M_DDR0_SPACE_1 0x001C 0xD1D2D3D4 ; 15

write w M_DDR0_SPACE_2 0x0020 0xE1E2E3E4 ; write w M_DDR0_SPACE_2 0x0024 0xD1D2D3D4 ; write w M_DDR0_SPACE_2 0x0028 0x11121314 ; write w M_DDR0_SPACE_2 0x002C 0x21222324 ; readcheck w M_DDR0_SPACE_2 0x0020 0xE1E2E3E4 ; readcheck w M_DDR0_SPACE_2 0x0024 0xD1D2D3D4 ; readcheck w M_DDR0_SPACE_2 0x0028 0x11121314 ; readcheck w M_DDR0_SPACE_2 0x002C 0x21222324 ; write w M_DDR0_SPACE_3 0x0030 0x31323334 ; write w M_DDR0_SPACE_3 0x0034 0x41424344 ; write w M_DDR0_SPACE_3 0x0038 0x51525354 ; write w M_DDR0_SPACE_3 0x003C 0x61626364 ; readcheck w M_DDR0_SPACE_3 0x0030 0x31323334 ; readcheck w M_DDR0_SPACE_3 0x0034 0x41424344 ; readcheck w M_DDR0_SPACE_3 0x0038 0x51525354 ; readcheck w M_DDR0_SPACE_3 0x003C 0x61626364 ; print "MDDR TEST ENDS"; return IGLOO2 Example (AHB/AXI Fabric Master) For IGLOO2, you may have a custom AHB/AXI fabric Master access the MDDR. In this case, your Fabric Master performs the transactions shown in Table 3-1. Table 3-1 IGLOO2 READ and WRITE Transactions Read/Write Base Address Data write 0xA0000000 0xa1b2c3d4 write 0xA0000004 0x10100101 write 0xB0000000 0xa1a2a3a4 write 0xB0000004 0xb1b2b3b4 read 0xA0000000 (expected): 0xa1b2c3d4 read 0xA0000004 (expected): 0x10100101 read 0xB0000000 (expected) 0xa1a2a3a4 read 0xB0000004 (expected) 0xb1b2b3b4 16

[Document Title] Simulation Timescale and 3rd-party DDR Memory Simulation Model The SmartDesign or HDL testbench from Libero has a timescale of 1 ns/100 ps by default. This timescale directive is not passed to the 3rd-party DDR memory simulation model. To have the timescale directive passed from the Testbench to the DDR memory simulation model, you must add an include statement in the HDL testbench, such as: 'include "ddr2.v" If the memory model does not have a timescale, refer to the vendor's documentation and add a timescale directive to the DDR simulation memory model per vendor's specifications. Alternatively, do both of the following to the HDL testbench: 1. Add an include statement to include the DDR Memory simulation model. 2. Change the timescale from Libero's default timescale to match the DDR memory simulation model's specification from vendor. 17

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