Intel FPGA Low Latency Ethernet 10G MAC Design Example User Guide for Intel Stratix 10 Devices

Intel FPGA Low Latency Ethernet 10G MAC Design Example User Guide for Intel Stratix 10 Devices Updated for Intel Quartus Prime Design Suite: 17.1 Subscribe Send Feedback Latest document on the web: PDF HTML

Contents Contents 1 Quick Start Guide... 5 1.1 Directory Structure... 6 1.2 Generating the Design...8 1.2.1 Procedure...8 1.2.2 Design Example Parameters... 9 1.3 Compiling and Simulating the Design...10 1.3.1 Procedure... 10 1.3.2 Testbench... 11 1.4 Compiling and Testing the Design in Hardware... 12 1.4.1 Procedure... 12 1.4.2 Hardware Setup...13 2 10GBASE-R Ethernet Design Example for Intel Stratix 10 Devices... 14 2.1 Features... 14 2.2 Hardware and Software Requirements... 14 2.3 Functional Description... 15 2.3.1 Design Components... 15 2.3.2 Clocking and Reset Scheme...16 2.4 Simulation... 16 2.5 Hardware Testing...16 2.5.1 Test Cases... 17 2.5.2 Signal Tap Debug Signals... 18 2.6 Interface Signals...20 2.7 Configuration Registers...20 3 10M/100M/1G/2.5G/10G Ethernet Design Example for Intel Stratix 10 Devices...22 3.1 Features... 22 3.2 Hardware and Software Requirements... 22 3.3 Functional Description... 22 3.3.1 Design Components... 23 3.3.2 Clocking Scheme... 24 3.3.3 Reset Scheme... 24 3.4 Simulation... 25 3.5 Hardware Testing...26 3.5.1 Test Procedure...26 3.6 Interface Signals...29 3.7 Configuration Registers...29 4 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature for Intel Stratix 10 Devices... 31 4.1 Features... 31 4.2 Hardware and Software Requirements... 31 4.3 Functional Description... 32 4.3.1 Design Components... 32 4.3.2 Clocking Scheme... 34 4.3.3 Reset Scheme... 34 4.4 Simulation... 35 4.4.1 Test Case Design Example with the IEEE 1588v2 Feature...35 2

Contents 4.5 Hardware Testing...36 4.5.1 Test Procedure...36 4.6 Interface Signals...39 4.7 Configuration Registers...39 5 1G/2.5G/10G Ethernet Design Example with IEEE 1588v2 Feature for Intel Stratix 10 Devices... 41 5.1 Features... 41 5.2 Hardware and Software Requirements... 41 5.3 Functional Description... 41 5.3.1 Design Components... 42 5.3.2 Clocking Scheme... 43 5.3.3 Reset Scheme... 44 5.4 Simulation... 45 5.4.1 Test Case Design Example with the IEEE 1588v2 Feature...45 5.5 Hardware Testing...46 5.5.1 Changing to SFP+ Setting... 47 5.5.2 Test Procedure...47 5.6 Interface Signals...50 5.7 Configuration Registers...50 6 10G USXGMII Ethernet Design Example for Intel Stratix 10 Devices...52 6.1 Features... 52 6.2 Hardware and Software Requirements... 52 6.3 Functional Description... 52 6.3.1 Design Components... 53 6.3.2 Clocking Scheme... 54 6.3.3 Reset Scheme... 54 6.4 Simulation... 55 6.5 Hardware Testing...56 6.5.1 Test Procedure...56 6.6 Interface Signals...58 6.7 Configuration Registers...59 7 Interface Signals Description... 60 7.1 Clock and Reset Interface Signals... 60 7.2 Avalon-MM Interface Signals... 60 7.3 Avalon-ST Interface Signals...62 7.4 PHY Interface Signals... 64 7.5 Status Interface...64 7.6 IEEE 1588v2 Timestamp Interface Signals...65 7.7 Packet Classifier Interface Signals... 66 7.8 ToD Interface Signals... 67 8 Configuration Registers Description...68 8.1 Register Access... 68 8.2 Low Latency Ethernet 10G MAC... 68 8.3 PHY... 72 8.3.1 Register Map... 72 8.3.2 Register Definitions... 73 8.4 Transceiver Reconfiguration...78 8.5 TOD... 78 3

Contents 9 Document Revision History for Intel FPGA Low Latency Ethernet 10G MAC Design Example User Guide for Intel Stratix 10 Devices... 80 4

1 Quick Start Guide The Intel FPGA Low Latency 10G Ethernet (LL 10GbE) MAC IP core for Intel Stratix 10 provides the capability of generating design examples for selected configurations. Figure 1. Development Stages for the Design Example Compilation (Simulator) Functional Simulation Design Example Generation Compilation (Quartus Prime) Hardware Testing Related Links 10GBASE-R Ethernet Design Example for Intel Stratix 10 Devices on page 14 Provides details for the 10GBASE-R Ethernet design example. 10M/100M/1G/2.5G/10G Ethernet Design Example for Intel Stratix 10 Devices on page 22 Provides details for the 10M/100M/1G/2.5G/10G Ethernet design example. 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature for Intel Stratix 10 Devices on page 31 Provides details for the 1G/2.5G Ethernet design example. 1G/2.5G/10G Ethernet Design Example with IEEE 1588v2 Feature for Intel Stratix 10 Devices on page 41 Provides details for the 1G/2.5G/10G Ethernet design example with IEEE 1588v2 feature. 10G USXGMII Ethernet Design Example for Intel Stratix 10 Devices on page 52 Provides details for the 10G USXGMII Ethernet design example. Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. ISO 9001:2008 Registered

1 Quick Start Guide 1.1 Directory Structure Figure 2. Directory Structure for the Design Example <Design Example> rtl altera_eth_multi_channel.sv altera_eth_channel.sv <Design Component> simulation ed_sim models cadence mentor hwtesting system_console output_files altera_eth_top.sof altera_eth_top.qpf altera_eth_top.qsf altera_eth_top.sv altera_eth_top.sdc <Design Component> synopsys vcs Table 1. Directory and File Description Directory/File altera_eth_top.qpf altera_eth_top.qsf altera_eth_top.sv altera_eth_top.sdc rtl rtl/ altera_eth_10g_mac_base_r.sv rtl/ altera_10g_mac_base_r_wrap.v rtl/altera_mge_rd.sv rtl/altera_mge_channel.v rtl/altera_eth_channel.v rtl/ altera_eth_multi_channel.sv rtl/altera_eth_channel_1588.v rtl/ altera_eth_multi_channel_1588.sv rtl/ altera_mge_multi_channel.sv rtl/altera_mge_channel.v rtl/<design Component> simulation/ed_sim/models simulation/ed_sim/cadence simulation/ed_sim/mentor Description Intel Quartus Prime Pro Edition project file. Intel Quartus Prime Pro Edition settings file. Design example top-level HDL. Synopsys Design Constraints (SDC) file. The folder that contains the design example synthesizable components. Design example DUT top-level files for 10GBASE-R ethernet design example. Design example DUT top-level files for the following ethernet design examples: 1G/2.5G with 1588v2 feature 1G/2.5G/10G Design example DUT top-level files for the following ethernet design examples: 10M/100M/1G/10G 1G/10G Design example DUT top-level files for the following ethernet design examples: 10M/100M/1G/10G with with 1588v2 feature 1G/10G with 1588v2 feature Design example DUT top-level files for 10G USXGMII ethernet design example. The folder for each synthesizable component including Platform Designer generated IPs, such as LL10GbE MAC, PHY, and FIFO. The folder that contains the testbench files. The folder that contains the simulation script. It also serves as a working area for the simulator. continued... 6

1 Quick Start Guide Directory/File Description simulation/ed_sim/ synopsys/vcs hwtesting/system_console output_files The folder that contains system console scripts for hardware testing. The folder that contains Intel Quartus Prime Pro Edition output files including Intel Quartus Prime Pro Edition compilation reports and design programing file (.sof file). 7

1 Quick Start Guide 1.2 Generating the Design 1.2.1 Procedure You can generate the design example from the IP Parameter Editor. Start Parameter Editor Specify IP Variation and Select Device Select Design Parameters Specify Example Design Initiate Design Generation Figure 3. Example Design Tab 1. Select Tools IP Catalog to open the IP Catalog and select Low Latency Ethernet 10G MAC. The IP parameter editor appears. 2. Specify a top-level name and the folder for your custom IP variation, and the target device. Click OK. 3. To generate a design example, select a design example preset from the Presets library and click Apply. When you select a design, the system automatically populates the IP parameters for the design. The Parameter Editor automatically sets the parameters required to generate the design example. Do not change the preset parameters in the IP tab. 4. Specify the parameters in the Example Design tab. 5. Click the Generate Example Design button. The software generates all design files in sub-directories. You require these files to run simulation, compilation, and hardware testing. Related Links Directory Structure on page 6 Provides more information about the generated design example directories and files. 8

1 Quick Start Guide 1.2.2 Design Example Parameters Table 2. Parameters in the Example Design Tab Parameter Description Select Design Example Design Files for Simulation or Synthesis Generate File Format Select Board Change Target Device Specify Number of Channels Analog Voltage Enable ADME support Available example designs for the IP parameter settings. When you select an example design from the Preset library, this field shows the selected design. The files to generate for the different development phase. Simulation generates the necessary files for simulating the example design. Synthesis generates the synthesis files. Use these files to compile the design in the Intel Quartus Prime Pro Edition software for hardware testing and perform static timing analysis. The format of the RTL files for simulation Verilog or VHDL. Supported hardware for design implementation. When you select an Intel FPGA development board, the Target Device is the one that matches the device on the Development Kit. If this menu is grayed out, there is no supported board for the options that you select. Intel Stratix 10 H-Tile GX Transceiver Signal Integrity Development Kit: This option allows you to test the design example on selected Intel FPGA IP development kit. This selection automatically selects the Target Device to match the device on the Intel FPGA IP development kit. If your board revision has a different device grade, you can change the target device. Custom Development Kit: This option allows you to test the design example on a third party development kit with Intel FPGA IP device, a custom designed board with Intel FPGA IP device, or a standard Intel FPGA IP development kit not available for selection. You can also select a custom device for the custom development kit. No Development Kit: This option excludes the hardware aspects for the design example. Select this parameter to display and select all devices for the Intel FPGA IP development kit. The number of Ethernet channels. VCCR_GXB and VCCT_GXB supply voltage for the Transceiver. Turn on this option to enable Transceiver ADME feature. 9

1 Quick Start Guide 1.3 Compiling and Simulating the Design 1.3.1 Procedure You can compile and simulate the design by running a simulation script from the command prompt. Change to Testbench Directory Run <Simulation Script> Analyze Results 1. At the command prompt, change the working directory to <Example Design> \simulation\ed_sim\<simulator>. 2. Run the simulation script for the simulator of your choice. Simulator Working Directory Command Modelsim* <Example Design>/simulation/ed_sim/mentor vsim -c -do tb_run.tcl VCS* <Example Design>/simulation/ed_sim/ synopsys/vcs sh tb_run.sh NCSim* <Example Design>/simulation/ed_sim/cadence sh tb_run.sh A successful simulation ends with the following message: Simulation stopped due to successful completion! Simulation passed. After successful completion, you can analyze the results. 10

1 Quick Start Guide 1.3.2 Testbench Figure 4. Block Diagram of the Testbench Testbench Avalon-MM Control Register Ethernet Packet Monitor Avalon-MM Avalon-ST Transmit Frame Generator Avalon-ST Receive Frame Monitor avalon_bfm_wrapper.sv Avalon Driver TX data RX data Ethernet Packet Monitor DUT Ordinary Clock Channel 0 Channel 1... Channel n-1 Channel n Loopback on Serial Table 3. Testbench Components Component Description Device under test (DUT) Avalon driver Ethernet packet monitors The design example. Consists of Avalon-ST master bus functional models (BFMs). This driver forms the TX and RX paths. The driver also provides access to the Avalon-MM interface of the DUT. Monitor TX and RX datapaths, and display the frames in the simulator console. 11

1 Quick Start Guide 1.4 Compiling and Testing the Design in Hardware 1.4.1 Procedure You can compile and test the design in the supported Intel FPGA development kit. Compile Design in Quartus Prime Software Set up Hardware Program Device Test Design in Hardware 1. Launch the Intel Quartus Prime Pro Edition software and select Processing Start Compilation to compile the design. The timing constraints for the design example and the design components are automatically loaded during compilation. 2. Connect the development board to the host computer. 3. Launch the Clock Control tool, which is part of the development kit, and set new frequencies for the design example. Note: For the frequencies to set, refer to the Hardware Testing section of the specific design example chapter. 4. In the Intel Quartus Prime Pro Edition software, select Tools Programmer to configure the FPGA on the development board using the generated.sof file. 5. Reset the system by pressing the PB0 push button. 6. In the Intel Quartus Prime software, select Tools System Debugging Tools System Console to launch the system console. 7. Change the working directory to <Example Design>\hwtesting \system_console. You can now run any of the predefined hardware tests from the System Console. Observe the test results displayed. 12

1 Quick Start Guide 1.4.2 Hardware Setup Figure 5. Block Diagram of the Hardware Setup PC Intel System Console Software Intel Stratix 10 Transceiver Signal Integrity Development Board Intel Stratix 10 FPGA JTAG TAP Controller System Controller Ethernet Frame Generation & Monitoring (Master) Ethernet Frame Generation & Monitoring (Slave) Ethernet Frame Generation & Monitoring Ethernet Channel 0 Ethernet Channel 1 Ethernet Channel n - 1 (2) (1) Ethernet Frame Generation & Monitoring Ethernet Channel n (1) Use this type of loopback to test IEEE 1588v2 features. (2) Use this type of loopback to test features other than IEEE 1588v2. This loopback is different than the loopback used for simulating multiple channels. 13

2 10GBASE-R Ethernet Design Example for Intel Stratix 10 Devices 2.1 Features The 10GBASE-R Ethernet design example demonstrates an Ethernet solution for Intel Stratix 10 devices using the LL 10GbE MAC IP core, the native PHY IP core, and a small form factor pluggable (SFP +) module. Generate the design example from the Example Design tab of the LL 10GbE IP parameter editor. Supports dual Ethernet channel operating at 10G using Intel Stratix 10 Native PHY. On the transmit and receive paths: Provides packet monitoring system. Reports Ethernet MAC statistics counter. Supports testing using different types of Ethernet packet transfer protocol. 2.2 Hardware and Software Requirements Intel uses the following hardware and software to test the design example in a Linux system: Intel Quartus Prime Pro Edition software ModelSim-AE, ModelSim-SE, NCSim (Verilog only), and VCS simulator For hardware testing: Intel Stratix 10 Signal Integrity Development Board (1SG280LU3F50E3VGS1) and Intel Stratix 10 H-Tile GX Signal Integrity Development Board (1SG280HU3F50E3VGS1) Cables SMA cable, SFP+, and fiber optic cable Related Links Analyzing and Debugging Designs with System Console Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. ISO 9001:2008 Registered

2 10GBASE-R Ethernet Design Example for Intel Stratix 10 Devices 2.3 Functional Description Figure 6. Block Diagram 10GBASE-R Ethernet Design Example Design Example (altera_eth_10g_mac_base_r) Avalon-MM Address Decoder S Avalon-MM Master M altera_eth_10g_mac_base_r_wrap S S Adapter LL 10GbE MAC Adapter PHY FIFO Avalon-ST TX/RX Serial Data Transceiver Reset Controller PLL Reset Synchronizer ATX PLL Generated with Platform Designer Generated with IP Catalog Input Clock Reset 2.3.1 Design Components Table 4. Design Components Component LL 10GbE MAC Description The Intel FPGA Low Latency Ethernet 10G MAC IP core with the following configuration: Speed: 10G Datapath options: TX & RX Enable ECC on memory blocks: Not selected Enable 10GBASE-R register mode: Not selected Enable supplementary address: Selected Enable statistics collection: Selected Statistics counters: Memory-based Use legacy XGMII Interface: Selected. Use legacy Avalon Memory-Mapped Interface: Not Selected Use legacy Avalon Streaming Interface: Not selected PHY Intel FPGA Transceiver Native PHY configured for the 10GBASE-R protocol. The preset sets the PHY's TX FIFO MODE to Phase Compensation and RX FIFO MODE to 10GBASE-R. Transceiver Reset Controller Address decoder Reset synchronizer ATX PLL Intel FPGA Transceiver PHY Reset Controller IP core. Resets the transceiver. Decodes the addresses of the components. Synchronizes the reset of all design components. Generates a TX serial clock for the Intel Stratix 10 10G transceiver. FIFO Avalon Streaming (Avalon-ST) single-clock and dual-clock FIFO. Buffers the RX and TX data between the MAC IP core and the client. 15

2 10GBASE-R Ethernet Design Example for Intel Stratix 10 Devices Related Links Low Latency Ethernet 10G MAC User Guide Provides more information about the MAC parameters. 10GBASE-R, 10GBASE-R with IEEE 1588v2, and 10GBASE-R with KR FEC Variants Provides more information about the PHY parameters. 2.3.2 Clocking and Reset Scheme Figure 7. Clocking and Reset Scheme for 10GBASE-R Design Example Generator and Checker reset_n clk rx_sc_fifo_clk_clk rx_sc_fifo_clk_reset_reset FIFO tx_sc_fifo_clk_clk tx_sc_fifo_clk_reset_reset outclk_0 PLL outclk_1 ATX PLL 644.53125 MHz ref_clk_clk avalon_st_rx_clk_156 avalon_st_rx_156_reset_n avalon_st_rx_clk_312 avalon_st_rx_312_reset_n Avalon-ST Adapter avalon_st_tx_clk_156 avalon_st_tx_156_reset_n avalon_st_tx_clk_312 avalon_st_tx_312_reset_n tx_312_5_clk tx_156_25_clk tx_rst_n LL 10GbE MAC tx_clkout rx_clkout reconfig_clk PHY tx_xcvr_half_clk tx_serial_clk rx_cdr_refclk0 reconfig_reset sl_clock sl_reset Avalon-MM Adapter ms_clock ms_reset csr_clk csr_rst_n rx_312_5_clk rx_156_25_clk rx_rst_n Reset Synchronizer master_reset_n rx_xcvr_clk_clk sync_rx_rst_reset_n Address Decoder tx_xcvr_half_clk_clk sync_tx_half_rst_reset_n tx_xcvr_clk_clk sync_tx_rst_reset_n clk_csr_clk csr_reset_n Transceiver Reset Controller reset clock 125 MHz csr_clk 2.4 Simulation The simulation test case demonstrates how the MAC and PHY configuration is changed at 10-Gbps throughput. The test case is for dual Ethernet channels. At the end of the simulation, the simulator generates the statistics of TX and RX packets in the Transcript window. Related Links Compiling and Simulating the Design on page 10 Provides information on the procedure and testbench. 2.5 Hardware Testing Follow the procedure at the provided link to test the design example in the selected hardware. In the Clock Control tool, which is part of the development kit, set the following frequencies: Y1 322.265625 MHz U5, OUT 8 125 MHz 16

2 10GBASE-R Ethernet Design Example for Intel Stratix 10 Devices Related Links Compiling and Testing the Design in Hardware on page 12 2.5.1 Test Cases You can run any of the following tests from the System Console. Table 5. Hardware Test Cases Test Case Command Description SFP+ loopback source gen_conf.tcl The generator generates and sends about 100 000 packets. Wait 1 minutes for it to complete its tasks. source monitor_conf.tcl source show_stats.tcl The monitor checks the number of good and bad packets received. This script displays the values of the statistics counters. Avalon-ST loopback source loopback_conf.tcl This command enables the Avalon-ST loopback. This test is used with an external tester such as Spirent tester. After the test is completed, observe the output displayed in the System Console. Figure 8. Test Output Sample for SFP+ Loopback 17

2 10GBASE-R Ethernet Design Example for Intel Stratix 10 Devices Figure 9. Test Output Sample TX and RX Statistics Counters 2.5.2 Signal Tap Debug Signals The Signal Tap file is included for debugging. This feature is disabled by default. To enable it, set the following assignment: set_global_assignment -name ENABLE_SIGNALTAP ON Table 6. Signal Tap Debug Signals Component Module Name Signal Top-level design example altera_eth_top csr_clk ref_clk_clk master_reset_n block_lock_n tx_ready_export_n rx_ready_export_n Design Example MAC IP core altera_eth_top.altera_eth_10g_mac_base_r_low_ latency altera_eth_top.altera_eth_10g_mac_base_r_low_ latency.altera_eth_10g_mac_base_r_low_latency _wrap.low_latency_mac atx_pll_locked iopll_locked avalon_st_tx_startofpacket avalon_st_tx_endofpacket avalon_st_tx_data avalon_st_tx_ready avalon_st_tx_valid continued... 18

2 10GBASE-R Ethernet Design Example for Intel Stratix 10 Devices Component Module Name Signal avalon_st_tx_error avalon_st_tx_empty avalon_st_rx_startofpacket avalon_st_rx_endofpacket avalon_st_rx_data avalon_st_rx_ready avalon_st_rx_valid avalon_st_rx_error avalon_st_rx_empty MAC TX MAC RX PHY altera_eth_top.altera_eth_10g_mac_base_r_low_ latency.altera_eth_10g_mac_base_r_low_latency _wrap.low_latency_mac.alt_em10g32.alt_em10g32 unit.alt_em10g32_tx_top.alt_em10g32_tx_rs_lay er.alt_em10g32_tx_rs_xgmii_layer_ultra altera_eth_top.altera_eth_10g_mac_base_r_low_ latency.altera_eth_10g_mac_base_r_low_latency _wrap.low_latency_mac.alt_em10g32.alt_em10g32 unit.alt_em10g32_rx_top.alt_em10g32_rx_rs_lay er.alt_em10g32_rx_rs_xgmii_ultra altera_eth_top.altera_eth_10g_mac_base_r_low_ latency.altera_eth_10g_mac_base_r_low_latency _wrap.low_latency_baser xgmii_tx_valid xgmii_tx_data xgmii_tx_control xgmii rx valid xgmii rx data xgmii rx control xgmii rx link fault status tx_analogreset tx_digitalreset rx_analogreset rx_digitalreset tx_cal_busy rx_cal_busy rx_is_lockedtodata tx_clkout 19

2 10GBASE-R Ethernet Design Example for Intel Stratix 10 Devices 2.6 Interface Signals Figure 10. Interface Signals of the 10GBASE-R Ethernet Design Example Avalon-ST Transmit Data Interface Avalon-ST Transmit Flow Control Interface Avalon-ST Transmit Status Interface Avalon-ST Receive Data Interface Avalon-ST Receive Status Interface Status Interface 10BASE-R Ethernet Design Example avalon_st_tx_startofpacket[n] avalon_st_tx_endofpacket[n] avalon_st_tx_valid[n] avalon_st_tx_ready[n] avalon_st_tx_error[n] avalon_st_tx_data[n][32] avalon_st_tx_empty[n][2] avalon_st_pause_data[n][2] avalon_st_txstatus_valid[n] avalon_st_txstatus_data[n][40] avalon_st_txstatus_error[n][7] avalon_st_rx_startofpacket[n] avalon_st_rx_endofpacket[n] avalon_st_rx_valid[n] avalon_st_rx_ready[n] avalon_st_rx_error[n][6] avalon_st_rx_data[n][32] avalon_st_rx_empty[n][2] avalon_st_rxstatus_valid[n] avalon_st_rxstatus_data[n][40] avalon_st_rxstatus_error[n][7] tx_ready_export[n] rx_ready_export[n] block_lock[n] atx_pll_locked link_fault_status_xgmii_rx_data[2] csr_clk csr_rst_n tx_rst_n rx_rst_n ref_clk_clk tx_clk_312 tx_clk_156 rx_clk_312 rx_clk_156 mac_csr_read[n] mac_csr_readdata[n][32] mac_csr_write[n] mac_csr_writedata[n][32] mac_csr_address[n][10] mac_csr_waitrequest[n] phy_csr_read[n] phy_csr_readdata[n][32] phy_csr_write[n] phy_csr_writedata[n][32] phy_csr_address[n][11] phy_csr_waitrequest[n] tx_serial_data[n] rx_serial_data[n] Clock and Reset Avalon-MM Interface PHY Interface Related Links Interface Signals Description on page 60 For more information on each interface signal. 2.7 Configuration Registers You can access the 32-bit configuration registers of the design components through the Avalon-MM interface. Table 7. Register Map Byte Offset 0x0000_0000 0x0001_CFFF 0x0001_D000 0xFFFF_FFFF Block Reserved Client Logic Channel 0 0x0000_0000 0x0000_8000 0x0000_d400 0x0000_d600 0x0000_c000 MAC PHY RX SC FIFO TX SC FIFO Packet Generator and Checker Channel 1 continued... 20

2 10GBASE-R Ethernet Design Example for Intel Stratix 10 Devices Byte Offset 0x0001_0000 0x0001_8000 0x0001_d400 0x0001_d600 0x0001_c000 Block MAC PHY RX SC FIFO TX SC FIFO Packet Generator and Checker Related Links Configuration Registers Description on page 68 For more information on each configuration register. 21

3 10M/100M/1G/2.5G/10G Ethernet Design Example for Intel Stratix 10 Devices 3.1 Features The 10M/100M/1G/2.5G/10G Ethernet design example demonstrates an Ethernet solution for Intel Stratix 10 using the LL 10GbE MAC IP core operating at 10M, 100M, 1G, 2.5G, and 10G. Generate the design example from the Example Design tab of the LL 10GbE IP parameter editor. Supports dual Ethernet channel operating at 10M, 100M, 1G, 2.5G, and 10G using Intel Stratix 10 Multi-rate PHY. On the transmit and receive paths: Provides packet monitoring system. Reports Ethernet MAC statistics counter. Supports testing using different types of Ethernet packet transfer protocol. 3.2 Hardware and Software Requirements Intel uses the following hardware and software to test the design example in a Linux system: Intel Quartus Prime Pro Edition software ModelSim-AE, ModelSim-SE, NCSim (Verilog only), and VCS simulator For hardware testing: Intel Stratix 10 Signal Integrity Development Board (1SG280LU3F50E3VGS1) and Intel Stratix 10 H-Tile GX Signal Integrity Development Board (1SG280HU3F50E3VGS1) Cables SMA cable, SFP+, and fiber optic cable 3.3 Functional Description The design example consists of various components. The following block diagram shows the design components and the top-level signals of the design example. Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. ISO 9001:2008 Registered

3 10M/100M/1G/2.5G/10G Ethernet Design Example for Intel Stratix 10 Devices Figure 11. Block Diagram 10M/100M/1G/2.5G/10G Ethernet Design Example Design Example (alt_mge_rd) Ethernet channel 0..(n-1) (alt_mge_channel) Avalon-MM S Address Decoder M... M M S S LL 10GbE MAC PHY Avalon-ST TX/RX Serial Data S Avalon-MM Mux Transceiver Reconfig Transceiver Reset Controller ATX PLL (10G) ATX PLL (2.5G) fpll (1G) Transceiver Reconfig Generated with Platform Designer Generated with IP Catalog Reset 10G Input Clock 1G Input Clock 3.3.1 Design Components Table 8. Design Components Component LL 10GbE MAC PHY Transceiver Reset Controller Description The Low Latency Ethernet 10G MAC IP core with the following configuration: Speed: 10M/100M/1G/2.5G/10G Datapath options: TX & RX Enable ECC on memory blocks: Not selected Enable supplementary address: Selected Enable statistics collection: Selected Statistics counters: Memory-based All Legacy Ethernet 10G MAC Interfaces options: Selected The 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP with the following configuration: Speed: 1G/2.5G/10G SGMII bridge: Selected Connect to MGBASE-T PHY: Selected Connect to NBASE-T PHY: Not selected PHY ID (32 bit): 0x00000000 VCCR_GXB and VCC_GXB supply voltage for the Tranceiver: 1_0V Reference clock frequency for 10GbE (MHz): 644.53125 Selected TX PMA local clock division factor for 1 GbE: 1 Selected TX PMA local clock division factor for 2.5 GbE: 1 Enable Altera Debug Master Endpoint: Not selected Enable capability registers: Not selected Enable control and status registers: Not selected Enable PRBS soft accumulators: Not selected The Intel FPGA Transceiver PHY Reset Controller IP core. Resets the transceiver. continued... 23

3 10M/100M/1G/2.5G/10G Ethernet Design Example for Intel Stratix 10 Devices Component Avalon-MM Mux Transceiver Reconfig Transceiver Reconfig ATX PLL fpll Description Provides the transceiver reconfig block and system console access to the PHY's Avalon-MM interface. Reconfigures the transceiver channel speed from 1G to 2.5G, or to 10G, and vice versa. Generates a TX serial clock for the Intel Stratix 10 2.5G and 10G transceiver. Generates a TX serial clock for the Intel Stratix 10 1G transceiver. Related Links Low Latency Ethernet 10G MAC User Guide Provides more information about the MAC parameters. 3.3.2 Clocking Scheme Figure 12. Clocking Scheme for 10M/100M/1G/2.5G/10G Ethernet Design Example PLL MAC Clock Design Example Channel 0 CDR Reference Clocks 644.53125 MHz Reference Clock User Logic MAC PHY 10G TX Serial Clock 10G PLL CSR Clock Transceiver Reset Controller 1G/2.5G/10G Reconfiguration Block 2.5G TX Serial Clock 1G TX Serial Clock 2.5G PLL 1G PLL 125 MHz Reference Clock Channel 1 User Logic MAC PHY CDR Reference Clock 125 MHz Reference Clock 644.53125 MHz Reference Clock 10G TX Serial Clock (5156.25 Mbps) 2.5G TX Serial Clock (1562.5 Mbps) 156.25 MHz MAC Clock 1G TX Serial Clock (625 Mbps) HSSI TX Clock Out 62.5 MHz at 1G, 156.25 MHz at 2.5G 125 MHz CSR Clock 3.3.3 Reset Scheme The global reset signal of the design example is asynchronous and active-high. Asserting this signal resets all channels and their components. Upon power-up, reset the design example. 24

3 10M/100M/1G/2.5G/10G Ethernet Design Example for Intel Stratix 10 Devices Figure 13. Reset Scheme for 10M/100M/1G/2.5G/10G Ethernet Design Example Design Example Channel 0 User Logic Global Reset User Logic MAC Transceiver Reset Controller PHY 1G/2.5G/10G Reconfiguration Block 10G PLL 2.5G PLL 1G PLL MAC Channel 1 PHY Global Reset Analog Reset Digital Reset Reconfiguration Done (triggers reset) 3.4 Simulation The simulation test case performs the following steps: 1. Starts up the example design with an operating speed of 10 Gbps. 2. Configures the MAC, PHY, and FIFO buffer for both channels. 3. Waits until the design example asserts the channel_tx_ready and channel_rx_ready signals for both channels. 4. Sends the following packets: 64-byte packet 1518-byte packet 100-byte packet 5. Repeats steps 2 to 4 for 2.5G, 1G, 100M, and 10M. When simulation ends, the values of the MAC statistics counters are displayed in the transcript window. The transcript window also displays PASSED if the RX Avalon-ST interface of channel 0 received all packets successfully, all statistics error counters are zero, and the RX MAC statistics counters are equal to the TX MAC statistics counters. 25

3 10M/100M/1G/2.5G/10G Ethernet Design Example for Intel Stratix 10 Devices 3.5 Hardware Testing Follow the procedure at the provided link to test the design example in the selected hardware. In the Clock Control tool, which is part of the development kit, set the following frequencies: Y1 644.53125 MHz U5, OUT 1 125 MHz U5, OUT 8 125 MHz Related Links 3.5.1 Test Procedure Compiling and Testing the Design in Hardware on page 12 Follow these steps to test the design examples in hardware: 1. Run the following command in the system console to start the test. TEST_EXT_LB <channel> <speed> <burst_size> Example: TEST_EXT_LB 0 10G 80000000 Table 9. Command Parameters Parameter Valid Values Description channel 0, 1 The channel number to test. speed 1G, 2.5G, 10G The PHY speed. burst_size An integer value The number of packets to generate for the test. 2. When the test is completed, observe the output displayed. The following diagrams show excerpts of the output, which shows that the packet monitor block receives the same number of packets generated without error, and the TX and RX statistics counters. 26

3 10M/100M/1G/2.5G/10G Ethernet Design Example for Intel Stratix 10 Devices Figure 14. Sample Output Packet Monitor 27

3 10M/100M/1G/2.5G/10G Ethernet Design Example for Intel Stratix 10 Devices Figure 15. Sample Output TX and RX Statistics Counters 28

3 10M/100M/1G/2.5G/10G Ethernet Design Example for Intel Stratix 10 Devices 3.6 Interface Signals Figure 16. Interface Signals of the Design Example Avalon-ST Transmit Data Interface Avalon-ST Transmit Flow Control Interface Avalon-ST Transmit Status Interface Avalon-ST Receive Data Interface Avalon-ST Receive Status Interface PHY Interface Status Interface avalon_st_tx_startofpacket[n] avalon_st_tx_endofpacket[n] avalon_st_tx_valid[n] avalon_st_tx_ready[n] avalon_st_tx_error[n] avalon_st_tx_data[n][64] avalon_st_tx_empty[n][3] avalon_st_pause_data[n][2] avalon_st_tx_status_valid[ n] avalon_st_tx_status_data[n][40] avalon_st_tx_status_error[n][7] avalon_st_rx_startofpacket[n] avalon_st_rx_endofpacket[n] avalon_st_rx_valid[n] avalon_st_rx_ready[n] avalon_st_rx_error[n][6] avalon_st_rx_data[n][64] avalon_st_rx_empty[n][3] avalon_st_rx_status_valid[n] avalon_st_rx_status_data[n][40] avalon_st_rx_status_error[n][7] rx_serial_data[n] tx_serial_data[n] led_link[n] led_panel_link[n] led_char_err[n] led_disp_err[n] led_an[n] rx_block_lock[n] channel_tx_ready[n] channel_rx_ready[n] n: Number of channels 10M/100M/1G/2.5G/10G Ethernet Design Example MAC RX csr_mac_read[n] csr_mac_readdata[n][32] csr_mac_write[n] csr_mac_writedata[32] csr_mac_address[n][10] csr_mac_waitrequest[n] csr_phy_read[n] csr_phy_readdata[n][32] csr_phy_write[n] csr_phy_writedata[32] csr_phy_address[n][11] csr_phy_waitrequest[n] csr_rcfg_read csr_rcfg_readdata[32] csr_rcfg_write csr_rcfg_writedata[32] csr_rcfg_address[2] csr_clk mac_clk mac64b_clk refclk_10g refclk_1g2p5g reset rx_pma_clkout tx_digitalreset[n] rx_digitalreset[n] Avalon-MM Interface (LL 10GbE MAC) Avalon-MM Interface (1G/2.5G/10G Multi-rate Ethernet PHY) Avalon-MM Interface (Reconfiguration) Clock and Reset Related Links Interface Signals Description on page 60 For more information on each interface signal. 3.7 Configuration Registers You can access the 32-bit configuration registers of the design components through the Avalon-MM interface. Table 10. Register Map Byte Offset 0x00_0000 0x00_4000 Block Transceiver Reconfiguration Reserved Channel 0 0x01_0000 0x01_8000 0x01_A000 MAC PHY Native PHY Reconfiguration Channel 1 0x02_0000 0x02_8000 MAC PHY continued... 29

3 10M/100M/1G/2.5G/10G Ethernet Design Example for Intel Stratix 10 Devices Byte Offset 0x02_A000 Block Native PHY Reconfiguration Traffic Controller 0x10_0000 Traffic Controller Related Links Configuration Registers Description on page 68 For more information on each configuration register. 30

4 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature for Intel Stratix 10 Devices 4.1 Features The 1G/2.5G Ethernet design example with the IEEE 1588v2 feature demonstrates an Ethernet solution for Intel Stratix 10 devices using the LL 10GbE MAC IP core operating at 1G and 2.5G. Generate the design example from the Example Design tab of the LL 10GbE IP parameter editor. Supports dual Ethernet channel operating at 1G and 2.5G using Intel Stratix 10 Multi-rate PHY. On the transmit and receive paths: Provides packet monitoring system. Reports Ethernet MAC statistics counter. Supports testing using different types of Ethernet packet transfer protocol. 4.2 Hardware and Software Requirements Intel uses the following hardware and software to test the design example in a Linux system: Intel Quartus Prime Pro Edition software ModelSim-AE, ModelSim-SE, NCSim (Verilog only), and VCS simulator For hardware testing: Intel Stratix 10 Signal Integrity Development Board (1SG280LU3F50E2VGS1) and Intel Stratix 10 H-Tile GX Signal Integrity Development Board (1SG280HU3F50E3VGS1) Cables SMA cable, SFP+, and fiber optic cable Related Links Analyzing and Debugging Designs with System Console Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. ISO 9001:2008 Registered

4 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature for Intel Stratix 10 Devices 4.3 Functional Description Figure 17. Block Diagram 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature altera_eth_top alt_mge_rd alt_mge_rd_addrdec_mch alt_mge_channel Avalon-MM Avalon-MM Master S M alt_mge_channel PTP Packet Classifier S LL 10GbE MAC S Pulse per Second Local TOD TOD Sync Avalon-ST 1G/2.5G Pulse Per Second S PHY TX/RX Serial Data Avalon-MM S Multiplexer S Transceiver Reconfiguration S Transceiver Reset Controller S Master TOD Transceiver S Reconfiguration ATX PLL fpll I/O PLL Pulse per Second Master Pulse Per Second fpll Generated with Platform Designer Generated with IP Catalog CSR Clock Reset Input Clock 4.3.1 Design Components Table 11. Design Components Component LL 10GbE MAC PHY Description The Low Latency Ethernet 10G MAC IP core with the following configuration: Speed: 1G/2.5G Datapath options: TX & RX Enable ECC on memory blocks: Not selected Enable supplementary address: Selected Enable statistics collection: Selected Statistics counters: Memory-based All Legacy Ethernet 10G MAC Interfaces options: Selected For the example design with the IEEE 1588v2 feature, the following additional parameters are configured: Enable time stamping: Selected Enable PTP one-step clock support: Selected Timestamp fingerprint width: 4 Time Of Day format: Enable both 96b and 64b Time of Day Format The 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP with the following configuration: continued... 32

4 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature for Intel Stratix 10 Devices Component Description Speed: 1G/2.5G Enable SGMII bridge: Not selected Enabled IEEE 1588 Precision Time Protocol: Selected PHY ID (32 bit): 0x00000000 VCCR_GXB and VCC_GXB supply voltage for the Tranceiver: 1_0V Selected TX PMA local clock division factor for 1 GbE: 1 Selected TX PMA local clock division factor for 2.5 GbE: 1 Enable Altera Debug Master Endpoint: Not selected Enable capability registers: Not selected Enable control and status registers: Not selected Enable PRBS soft accumulators: Not selected Transceiver Reset Controller Avalon-MM Mux Transceiver Reconfig Transceiver Reconfig ATX PLL fpll The Intel FPGA Transceiver PHY Reset Controller IP core. Resets the transceiver. Provides the transceiver reconfig block and system console access to the PHY's Avalon-MM interface. Reconfigures the transceiver channel speed from 1 Gbps to 2.5 Gbps, and vice versa. Generates a TX serial clock for the Intel Stratix 10 2.5G transceiver. Generates a TX serial clock for the Intel Stratix 10 1G transceiver. Design Components for the IEEE 1588v2 Feature IO PLL Master Time-of-Day (TOD) TOD Synch Local TOD Master Pulse Per Second (PPS) PPS PTP Packet Classifier Generates the clocks for the 1588 design components. The master TOD for all channels. Synchronizes the Master TOD to all Local TODs. The TOD for each channel. The master PPS. Returns pulse per second (pps) for all channels. The slave PPS. Returns pulse per second (pps) for each channel. Decodes the packet type of incoming PTP packets and returns the decoded information to the LL10GbE MAC IP core. Related Links Low Latency Ethernet 10G MAC User Guide Provides more information about the MAC parameters. 33

4 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature for Intel Stratix 10 Devices 4.3.2 Clocking Scheme Figure 18. Clocking Scheme for 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature User Logic MAC Clock Reference Design Channel N PTP Packet Classifier Core PLL MAC TOD 2.5G TOD 2.5G Sync PPS 2.5G TOD 1G TOD 1G Sync PPS 1G PHY Address Decoder Transceiver Reset Controller 1G/2.5G Reconfiguration Block 1G fpll 2.5G ATX PLL Sampling IOPLL Master ToD Master PPS 125 MHz Reference Clock Reference Clock (125 MHz) 2.5G TX Serial Clock (1562.5 MHz) 1G TX Serial Clock (625 MHz) HSSI TX Clock Out: 62.5 MHz at 1G, 156.25 MHz at 2.5G HSSI TX Clock In: 62.5 MHz at 1G, 156.25 MHz at 2.5G CSR Clock (125 MHz) Sampling Clock (53.33 MHz) Sampling Clock (80 MHz) MAC Clock (156.25 MHz) 125 MHz CSR Clock 4.3.3 Reset Scheme The global reset signal of the design example is asynchronous and active-low. Asserting this signal resets all channels and their components. Upon power-up, reset the design example. 34

4 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature for Intel Stratix 10 Devices Figure 19. Reset Scheme for 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature User Logic Design Example Channel N PTP Packet Classifier MAC TOD 2.5G TOD 2.5G Sync PPS 2.5G PHY TOD 1G TOD 1G Sync PPS 1G Address Decoder Transceiver Reset Controller 1G/2.5G Reconfiguration Block 1G fpll 2.5G ATX PLL Sampling IOPLL TOD Master PPS Master Global Reset Reconfiguration Done (to trigger reset after reconfiguration) Digital/Analog Reset Stat Global Reset Digital Reset Analog Reset 4.4 Simulation 4.4.1 Test Case Design Example with the IEEE 1588v2 Feature The simulation test case performs the following steps: 1. Starts up the design example with an operating speed of 2.5G. 2. Configures the MAC, PHY, and FIFO buffer for both channels. 3. Waits until the design example asserts the channel_tx_ready and channel_rx_ready signals for each channel. 4. Sends the following packets: Non-PTP No VLAN, PTP over Ethernet, PTP Sync Message, 1-step PTP VLAN, PTP over UDP/IPv4, PTP Sync Message, 1-step PTP Stacked VLAN, PTP over UDP/IPv6, PTP Sync Message, 2-step PTP No VLAN, PTP over Ethernet, PTP Delay Request Message, 1-step PTP VLAN, PTPover UDP/IPv4, PTP Delay Request Message, 2-step PTP Stacked VLAN, PTP over UDP/IPv6, PTP Delay Request Message, 1-step PTP 5. Repeats steps 2 to 4 for 1G. When simulation ends, the values of the MAC statistics counters are displayed in the transcript window. The transcript window also displays PASSED if the RX Avalon-ST interface of channel 0 received all packets successfully, all statistics error counters are zero, and the RX MAC statistics counters are equal to the TX MAC statistics counters. 35

4 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature for Intel Stratix 10 Devices Figure 20. Sample Simulation Output 4.5 Hardware Testing Follow the procedure at the provided link to test the design example in the selected hardware. In the Clock Control tool, which is part of the development kit, set the following frequencies: U5, OUT 0 125 MHz U5, OUT 8 125 MHz Related Links 4.5.1 Test Procedure Compiling and Testing the Design in Hardware on page 12 Follow these steps to test the design examples in hardware: 1. Run the following command in the system console to start the test. TEST_EXT_LB <channel> <speed> <burst_size> Example: TEST_EXT_LB 0 2.5G 1000000000 36

4 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature for Intel Stratix 10 Devices Table 12. Command Parameters Parameter Valid Values Description channel 0, 1 The channel number to test. speed 1G, 2.5G The PHY speed. burst_size An integer value The number of packets to generate for the test. 2. When the test is completed, observe the output displayed. The following diagrams show excerpts of the output, which shows that the packet monitor block receives the same number of packets generated without error, and the TX and RX statistics counters. Figure 21. Sample Output Packet Monitor 37

4 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature for Intel Stratix 10 Devices Figure 22. Sample Output TX and RX statistics counters 38

4 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature for Intel Stratix 10 Devices 4.6 Interface Signals Figure 23. Interface Signals of the 1G/2.5G Ethernet Design Examples with IEEE 1588v2 Feature Avalon-ST Transmit Data Interface Avalon-ST Transmit Flow Control Interface Avalon-ST Transmit Status Interface Avalon-ST Receive Data Interface Avalon-ST Receive Status Interface PHY Interface Status Interface IEEE 1588v2 Time-Stamp Interface 1G/2.5G Ethernet Design Example with 1588v2 Feature csr_mac_read[n] avalon_st_tx_startofpacket[n] csr_mac_readdata[n][32] avalon_st_tx_endofpacket[n] csr_mac_write[n] avalon_st_tx_valid[n] avalon_st_tx_ready[n] csr_mac_writedata[32] avalon_st_tx_error[n] csr_mac_address[n][10] avalon_st_tx_data[n][32] csr_mac_waitrequest[n] avalon_st_tx_empty[n][2] csr_phy_read[n] csr_phy_readdata[n][32] avalon_st_pause_data[n][2] csr_phy_write[n] csr_phy_writedata[32] csr_phy_address[n][11] avalon_st_txstatus_valid[n] csr_phy_waitrequest[n] avalon_st_txstatus_data[n][40] csr_rcfg_read[n] avalon_st_txstatus_error[n][7] csr_rcfg_readdata[32] csr_rcfg_write[n] avalon_st_rx_startofpacket[n] csr_rcfg_writedata[32] avalon_st_rx_endofpacket[n] csr_rcfg_address[2] avalon_st_rx_valid[n] csr_native_phy_rcfg_read avalon_st_rx_ready[n] csr_native_phy_rcfg_readdata[32] avalon_st_rx_error[n][6] csr_native_phy_rcfg_write avalon_st_rx_data[n][32] csr_native_phy_rcfg_writedata[32] avalon_st_rx_empty[n][2] csr_native_phy_rcfg_address[10] csr_native_phy_rcfg_waitrequest avalon_st_rxstatus_valid[n] MAC RX csr_master_tod_read[n] avalon_st_rxstatus_data[n][40] csr_master_tod_readdata[n][32] avalon_st_rxstatus_error[n][7] csr_master_tod_write[n] csr_master_tod_writedata[n][32] rx_serial_data[n] csr_master_tod_address[n][4] tx_serial_data[n] csr_master_tod_waitrequest[n] csr_clk led_link[n] mac_clk led_char_err[n] refclk led_disp_err[n] reset led_an[n] rx_pma_clkout channel_tx_ready[n] tx_digital_reset[n] channel_rx_ready[n] rx_digital_reset[n] rx_digital_reset_stat[n] tx_egress_timestamp_96b_valid[n] tx_egress_timestamp_96b_data[n][96] tx_egress_timestamp_96b_fingerprint[n][f] tx_egress_timestamp_64b_valid[n] tx_egress_timestamp_64b_data[n][64] tx_egress_timestamp_64b_fingerprint[n][f] rx_ingress_timestamp_96b_valid[n] rx_ingress_timestamp_96b_data[n][96] rx_ingress_timestamp_64b_valid[n] rx_ingress_timestamp_64b_data[n][64] n: Number of channels f: Timestamp fingerprint width tx_egress_timestamp_request_in_valid[n] tx_egress_timestamp_request_in_fingerprint[n][f] clock_operation_mode_mode[n][2] pkt_with_crc_mode[n] tx_ingress_timestamp_valid[n] tx_ingress_timestamp_96b_data[n][96] tx_ingress_timestamp_64b_data[n][64] tx_ingress_timestamp_format[n] master_pulse_per_second start_tod_sync[n] pps[n] Avalon-MM Interface (LL 10GbE MAC) Avalon-MM Interface (1G/2.5G/10G Multi-rate Ethernet PHY) Avalon-MM Interface (Reconfiguration) Avalon-MM Interface (Native PHY Reconfiguration) Avalon-MM Interface (Master ToD Clock) Clock and Reset Packet Classifier Interface TOD Interface Related Links Interface Signals Description on page 60 For more information on each interface signal. 4.7 Configuration Registers You can access the 32-bit configuration registers of the design components through the Avalon-MM interface. Table 13. Register Map Byte Offset 0x00_0000 0x00_4000 Block Transceiver Reconfiguration TOD Master continued... 39

4 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature for Intel Stratix 10 Devices Byte Offset Block Channel 0 0x01_0000 0x01_8000 0x01_A000 MAC PHY Native PHY Reconfiguration Channel 1 0x02_0000 0x02_8000 0x02_A000 MAC PHY Native PHY Reconfiguration Traffic Controller 0x10_0000 Traffic Controller Related Links Configuration Registers Description on page 68 For more information on each configuration register. 40

5 1G/2.5G/10G Ethernet Design Example with IEEE 1588v2 Feature for Intel Stratix 10 Devices 5.1 Features The 1G/2.5G/10G Ethernet design example with the IEEE 1588v2 feature demonstrates an Ethernet solution for Intel Stratix 10 using the LL 10GbE MAC IP core operating at 1G, 2.5G, and 10G. Generate the design example from the Example Design tab of the LL 10GbE IP parameter editor. Supports dual Ethernet channel operating at 1G, 2.5G, and 10G using Intel Stratix 10 Multi-rate PHY. On the transmit and receive paths: Provides packet monitoring system. Reports Ethernet MAC statistics counter. Supports testing using different types of Ethernet packet transfer protocol. 5.2 Hardware and Software Requirements Intel uses the following hardware and software to test the design example in a Linux system: Intel Quartus Prime Pro Edition software ModelSim-AE, ModelSim-SE, NCSim (Verilog only), and VCS simulator For hardware testing: Intel Stratix 10 Signal Integrity Development Board (1SG280LU3F50E2VGS1) and Intel Stratix 10 H-Tile GX Signal Integrity Development Board (1SG280HU3F50E2VGS1) Cables SMA cable, SFP+, and fiber optic cable 5.3 Functional Description The design example consists of various components. The following block diagram shows the design components and the top-level signals of the design example. Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. ISO 9001:2008 Registered

5 1G/2.5G/10G Ethernet Design Example with IEEE 1588v2 Feature for Intel Stratix 10 Devices Figure 24. Block Diagram 1G/2.5G/10G Ethernet Design Example with IEEE 1588v2 Feature altera_eth_top alt_mge_rd alt_mge_rd_addrdec_mch alt_mge_channel Avalon-MM Avalon-MM Master S M alt_mge_channel PTP Packet Classifier S LL 10GbE MAC S Pulse per Second Local TOD TOD Sync Avalon-ST 1G/2.5G/10G Pulse Per Second S PHY TX/RX Serial Data Avalon-MM S Multiplexer S Transceiver Reconfiguration Transceiver S Reconfiguration Transceiver S Reset Controller ATX PLL ATX PLL fpll fpll fpll S Master TOD Pulse per Second Master Pulse Per Second Core PLL Generated with Platform Designer Generated with IP Catalog CSR Clock Reset 1G/2.5G/10G Core Reference Clocks 5.3.1 Design Components Table 14. Design Components Component LL 10GbE MAC PHY Description The Low Latency Ethernet 10G MAC IP core with the following configuration: Speed: 1G/2.5G/10G Datapath options: TX & RX Enable ECC on memory blocks: Not selected Enable supplementary address: Selected Enable statistics collection: Selected Statistics counters: Memory-based All Legacy Ethernet 10G MAC Interfaces options: Selected For the design example with the IEEE 1588v2 feature, the following additional parameters are configured: Enable time stamping: Selected Enable PTP one-step clock support: Selected Timestamp fingerprint width: 4 Time Of Day format: Enable both 96b and 64b Time of Day Format The 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP with the following configuration: Speed: 1G/2.5G/5G/10G Enable SGMII bridge: Not selected Enabled IEEE 1588 Precision Time Protocol: Selected Connect to MGBASE-T PHY: Selected continued... 42

5 1G/2.5G/10G Ethernet Design Example with IEEE 1588v2 Feature for Intel Stratix 10 Devices Component Description Connect to NBASE-T PHY: Not selected PHY ID (32 bit): 0x00000000 VCCR_GXB and VCC_GXB supply voltage for the Tranceiver: 1_0V Reference clock frequency for 10GbE (MHz): 644.53125 Selected TX PMA local clock division factor for 1 GbE: 1 Selected TX PMA local clock division factor for 2.5 GbE: 1 Enable Altera Debug Master Endpoint: Not selected Enable capability registers: Not selected Enable control and status registers: Not selected Enable PRBS soft accumulators: Not selected Transceiver Reset Controller Avalon-MM Mux Transceiver Reconfig Transceiver Reconfig ATX PLL fpll The Intel FPGA Transceiver PHY Reset Controller IP core. Resets the transceiver. Provides the transceiver reconfig block and system console access to the PHY's Avalon-MM interface. Reconfigures the transceiver channel speed from 1G to 2.5G, or to 10G, and vice versa. Generates a TX serial clock for the Intel Stratix 10 2.5G and 10G transceiver. Generates a TX serial clock for the Intel Stratix 10 1G transceiver. Design Components for the IEEE 1588v2 Feature Core PLL Master ToD ToD Synch Local ToD Master PPS PPS PTP Packet Classifier Generates the clocks for the 1588 design components. The master ToD for all channels. Synchronizes the Master ToD to all Local ToDs. The ToD for each channel. The master PPS. Returns pulse per second (pps) for all channels. The slave PPS. Returns pulse per second (pps) for each channel. Decodes the packet type of incoming PTP packets and returns the decoded information to the LL10GbE MAC IP core. 5.3.2 Clocking Scheme 43

5 1G/2.5G/10G Ethernet Design Example with IEEE 1588v2 Feature for Intel Stratix 10 Devices Figure 25. Clocking Scheme for 1G/2.5G/10G Ethernet Design Example with IEEE 1588v2 Feature Design Example User Logic mac64b_clk PTP Packet Classifier ToD 10G ToD 10G Sync PPS 10G Core PLL MAC ToD 10G ToD 2.5G PPS 2.5G Sync PHY ToD 1G TOD 10G Sync PPS 1G Channel N Address Decoder Transceiver Reset Controller 1G/2.5G/10G Reconfiguration Block 10G ATX PLL 2.5G ATX PLL 1G fpll Transceiver Sampling fpll ToD Sampling fpll Master ToD Master PPS 644.53125 MHz refclk_10g 125 MHz refclk_1g2p5g 125 MHz refclk_core 125 MHz csr_clk refclk_10g (644.53125 MHz) refclk_1g2p5g (125 MHz) refclk_core (125 MHz) xcvr_pll_10g_serial_clk (5156.25 MHz) xcvr_pll_2p5g_serial_clk (1562.5 MHz) xcvr_pll_1g_serial_clk (625 MHz) gmii16b_tx_clk (62.5 MHz [1G], 156.25 MHz [2.5G]) gmii16b_rx_clk (62.5 MHz [1G], 156.25 MHz [2.5G]) csr_clk (125 MHz) latency_sclk (153.846153 MHz) tod_sampling_clk (80 MHz) mac_clk (312.5 MHz) mac64b_clk (156.25 MHz) 5.3.3 Reset Scheme The global reset signal of the design example is asynchronous and active-low. Asserting this signal resets all channels and their components. Upon power-up, reset the design example. Figure 26. Reset Scheme for 1G/2.5G/10G Ethernet Design Example with IEEE 1588v2 Feature User Logic Design Example Channel N PTP Packet Classifier ToD 10G ToD 10G Sync PPS 10G MAC ToD 1G ToD 1G Sync PPS 1G PHY ToD 1G ToD 1G Sync PPS 1G Address Decoder Transceiver Reset Controller 1G/2.5G/10G Reconfiguration Block 10G ATX PLL 2.5G ATX PLL 1G fpll Transceiver Sampling fpll ToD Sampling fpll Master ToD Master PPS Global Reset Reconfiguration Done (to trigger reset after reconfiguration) Global Reset Digital Reset Analog Reset 44

5 1G/2.5G/10G Ethernet Design Example with IEEE 1588v2 Feature for Intel Stratix 10 Devices 5.4 Simulation 5.4.1 Test Case Design Example with the IEEE 1588v2 Feature The simulation test case performs the following steps: 1. Starts up the design example with an operating speed of 10G. 2. Configures the MAC, PHY, and FIFO buffer for both channels. 3. Waits until the design example asserts the channel_tx_ready and channel_rx_ready signals for each channel. 4. Sends the following packets: Non-PTP No VLAN, PTP over Ethernet, PTP Sync Message, 1-step PTP VLAN, PTP over UDP/IPv4, PTP Sync Message, 1-step PTP Stacked VLAN, PTP over UDP/IPv6, PTP Sync Message, 2-step PTP No VLAN, PTP over Ethernet, PTP Delay Request Message, 1-step PTP VLAN, PTPover UDP/IPv4, PTP Delay Request Message, 2-step PTP Stacked VLAN, PTP over UDP/IPv6, PTP Delay Request Message, 1-step PTP 5. Repeats steps 2 to 4 for 1G and 2.5G. When simulation ends, the values of the MAC statistics counters are displayed in the transcript window. The transcript window also displays PASSED if the RX Avalon-ST interface of channel 0 received all packets successfully, all statistics error counters are zero, and the RX MAC statistics counters are equal to the TX MAC statistics counters. 45

5 1G/2.5G/10G Ethernet Design Example with IEEE 1588v2 Feature for Intel Stratix 10 Devices Figure 27. Sample Simulation Output 5.5 Hardware Testing Follow the procedure at the provided link to test the design example in the selected hardware. The design example is using board trace loopback by default. To use SFP+, follow instruction in Changing to SFP+ Setting on page 47. In the Clock Control tool, which is part of the development kit, set the following frequencies: For board trace loopback setting: U5, OUT 0 644.53125 MHz U5, OUT 4 125 MHz U5, OUT 8 125 MHz For SFP+ setting: 46

5 1G/2.5G/10G Ethernet Design Example with IEEE 1588v2 Feature for Intel Stratix 10 Devices Y1 644.53125 MHz U5, OUT 1 125 MHz U5, OUT 8 125 MHz Related Links Compiling and Testing the Design in Hardware on page 12 5.5.1 Changing to SFP+ Setting In order to use SFP+, modify altera_eth_top.qsf file with the following setting: 5.5.2 Test Procedure Follow these steps to test the design examples in hardware: 1. Run the following command in the system console to start the test. TEST_EXT_LB <channel> <speed> <burst_size> Example: TEST_EXT_LB 0 10G 200000 47

5 1G/2.5G/10G Ethernet Design Example with IEEE 1588v2 Feature for Intel Stratix 10 Devices Table 15. Command Parameters Parameter Valid Values Description channel 0, 1 The channel number to test. speed 1G, 2.5G, 10G The PHY speed. burst_size An integer value The number of packets to generate for the test. 2. When the test is completed, observe the output displayed. The following diagrams show excerpts of the output, which shows that the packet monitor block receives the same number of packets generated without error, and the TX and RX statistics counters. Figure 28. Sample Output Packet Monitor 48

5 1G/2.5G/10G Ethernet Design Example with IEEE 1588v2 Feature for Intel Stratix 10 Devices Figure 29. Sample Output TX and RX Statistics Counters 49

5 1G/2.5G/10G Ethernet Design Example with IEEE 1588v2 Feature for Intel Stratix 10 Devices 5.6 Interface Signals Figure 30. Interface Signals of the 1G/2.5G/10G Ethernet Design Examples with IEEE 1588v2 Feature Avalon-ST Transmit Data Interface Avalon-ST Transmit Flow Control Interface Avalon-ST Transmit Status Interface Avalon-ST Receive Data Interface Avalon-ST Receive Status Interface PHY Interface Status Interface IEEE 1588v2 Time-Stamp Interface 1G/2.5G/10G Ethernet Design Example with 1588v2 Feature avalon_st_tx_startofpacket[n] avalon_st_tx_endofpacket[n] avalon_st_tx_valid[n] avalon_st_tx_ready[n] avalon_st_tx_error[n] avalon_st_tx_data[n][64] avalon_st_tx_empty[n][3] avalon_st_pause_data[n][2] avalon_st_tx_status_valid[n] avalon_st_tx_status_data[n][40] avalon_st_tx_status_error[n][7] avalon_st_rx_startofpacket[n] avalon_st_rx_endofpacket[n] avalon_st_rx_valid[n] avalon_st_rx_ready[n] avalon_st_rx_error[n][6] avalon_st_rx_data[n][64] avalon_st_rx_empty[n][3] avalon_st_rx_status_valid[n] avalon_st_rx_status_data[n][40] avalon_st_rx_status_error[n][7] rx_serial_data[n] tx_serial_data[n] led_link[n] led_char_err[n] led_disp_err[n] led_an[n] channel_tx_ready[n] channel_rx_ready[n] tx_egress_timestamp_96b_valid[n] tx_egress_timestamp_96b_data[n][96] tx_egress_timestamp_96b_fingerprint[n][f] tx_egress_timestamp_64b_valid[n] tx_egress_timestamp_64b_data[n][64] tx_egress_timestamp_64b_fingerprint[n][f] rx_ingress_timestamp_96b_valid[n] rx_ingress_timestamp_96b_data[n][96] rx_ingress_timestamp_64b_valid[n] rx_ingress_timestamp_64b_data[n][64] MAC RX csr_mac_read[n] csr_mac_readdata[n][32] csr_mac_write[n] csr_mac_writedata[32] csr_mac_address[n][10] csr_mac_waitrequest[n] csr_phy_read[n] csr_phy_readdata[n][32] csr_phy_write[n] csr_phy_writedata[32] csr_phy_address[n][11] csr_phy_waitrequest[n] csr_rcfg_read csr_rcfg_readdata[32] csr_rcfg_write csr_rcfg_writedata[32] csr_rcfg_address[2] csr_native_phy_rcfg_read csr_native_phy_rcfg_readdata[32] csr_native_phy_rcfg_write csr_native_phy_rcfg_writedata[32] csr_native_phy_rcfg_address[11] csr_native_phy_rcfg_waitrequest csr_clk mac_clk mac64b_clk refclk_10g refclk_core refclk_1g2p5g reset tx_digitalreset[ n] rx_digitalreset[ n] rx_digitalreset_stat[ n] csr_master_tod_read[ n] csr_master_tod_readdata[n][32] csr_master_tod_write[ n] csr_master_tod_writedata[n][32] csr_master_tod_address[n] csr_master_tod_waitrequest[n] tx_egress_timestamp_request_in_valid[n] tx_egress_timestamp_request_in_fingerprint[n][f] clock_operation_mode_mode[n][2] pkt_with_crc_mode[n] tx_ingress_timestamp_valid[n] tx_ingress_timestamp_96b_data[n][96] tx_ingress_timestamp_64b_data[n][64] tx_ingress_timestamp_format[n] Avalon-MM Interface (LL 10GbE MAC) Avalon-MM Interface (1G/2.5G/5G/10G Multi-rate Ethernet PHY) Avalon-MM Interface (1G/2.5G/10G Ethernet Reconfiguration) Avalon-MM Interface (Direct Native PHY Reconfiguration) Clock and Reset Avalon-MM Interface (Master ToD Clock) Packet Classifier Interface master_pulse_per_second start_tod_sync[n] pps[n] TOD Interface n: Number of channels f: Timestamp fingerprint width 5.7 Configuration Registers You can access the 32-bit configuration registers of the design components through the Avalon-MM interface. Table 16. Register Map Byte Offset 0x00_0000 0x00_4000 Block Transceiver Reconfiguration TOD Master continued... 50

5 1G/2.5G/10G Ethernet Design Example with IEEE 1588v2 Feature for Intel Stratix 10 Devices Byte Offset Block Channel 0 0x01_0000 0x01_8000 0x01_A000 MAC PHY Native PHY Reconfiguration Channel 1 0x02_0000 0x02_8000 0x02_A000 MAC PHY Native PHY Reconfiguration Traffic Controller 0x10_0000 Traffic Controller 51

6 10G USXGMII Ethernet Design Example for Intel Stratix 10 Devices 6.1 Features The 10G USXGMII design example demonstrates an Ethernet solution for Intel Stratix 10 devices using the LL 10GbE MAC IP core operating at 1G, 2.5G, 5G, and 10G. Generate the design example from the Example Design tab of the LL 10GbE IP parameter editor. Supports dual Ethernet channel operating at 1G, 2.5G, 5G, and 10G. On the transmit and receive paths: Provides packet monitoring system. Reports Ethernet MAC statistics counter. Supports testing using different types of Ethernet packet transfer protocol. 6.2 Hardware and Software Requirements Intel uses the following hardware and software to test the design example in a Linux system: Intel Quartus Prime Pro Edition software ModelSim-AE, ModelSim-SE, NCSim (Verilog only), and VCS simulator For hardware testing: Intel Stratix 10 Signal Integrity Development Board (1SG280LU3F50E3VGS1) and Intel Stratix 10 H-Tile GX Signal Integrity Development Board (1SG280HU3F50E3VGS1) Cables SMA cable, SFP+, and fiber optic cable 6.3 Functional Description The design example consists of various components. The following block diagram shows the design components and the top-level signals of the design example. Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. ISO 9001:2008 Registered

6 10G USXGMII Ethernet Design Example for Intel Stratix 10 Devices Figure 31. Block Diagram 10G USXGMII Ethernet Design Example Design Example (alt_mge_rd) Ethernet channel 0..(n-1) (alt_mge_channel) Avalon-MM S Address Decoder M... M S S LL 10GbE MAC PHY Avalon-ST TX/RX Serial Data 156.25 MHz 312.5 MHz Transceiver Reset Controller ATX PLL (10G) Core PLL Generated with Platform Designer Generated with IP Catalog Reset 10G Input Clock 6.3.1 Design Components Table 17. Design Components Component LL 10GbE MAC PHY Description The Intel FPGA Low Latency Ethernet 10G MAC IP core with the following configuration: Speed: 1G/2.5G/5G/10G (USXGMII) Datapath options: TX & RX Enable ECC on memory blocks: Not selected Enable supplementary address: Selected Enable statistics collection: Selected Statistics counters: Memory-based Use legacy XGMII Interface: Not selected Use legacy Avalon Memory-Mapped Interface: Not selected Use legacy Avalon Streaming Interface: Selected The 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP with the following configuration: Speed: 1G/2.5G/5G/10G Enable SGMII bridge: Not selected Enabled IEEE 1588 Precision Time Protocol: Not Selected Connect to MGBASE-T PHY: Not selected Connect to NBASE-T PHY: Selected VCCR_GXB and VCC_GXB supply voltage for the Tranceiver: 1_0V Reference clock frequency for 10GbE (MHz): 644.53125 Enable Altera Debug Master Endpoint: Not selected Enable capability registers: Not selected Enable control and status registers: Not selected Enable PRBS soft accumulators: Not selected continued... 53

6 10G USXGMII Ethernet Design Example for Intel Stratix 10 Devices Component Channel address decoder Multi-channel address decoder Top address decoder Transceiver Reset Controller ATX PLL Core PLL Description Decodes the addresses of the components in each Ethernet channel. Decodes the addresses of the components used by all channels, such as the Master ToD module. Decodes the addresses of the top-level components, such as the Traffic Controller. The Intel FPGA Transceiver PHY Reset Controller IP core. Resets the transceiver. Generates a TX serial clock for the Intel Stratix 10 transceiver. Generates clocks for all design components. 6.3.2 Clocking Scheme Figure 32. Clocking Scheme for 10G USXGMII Ethernet Design Example PLL User Logic MAC Clock Design Example MAC Channel 0 PHY CDR Reference Clock CSR Clock Transceiver Reset Controller 10G TX Serial Clock 10G PLL 322.265625 MHz Reference Clock Channel 1 User Logic MAC PHY CDR Reference Clock 322.265625 MHz Reference Clock 10G TX Serial Clock (5156.25 MHz) 125 MHz CSR Clock 312.5 MHz MAC Clock 6.3.3 Reset Scheme The global reset signal of the design example is asynchronous and active-high. Asserting this signal resets all channels and their components. Upon power-up, reset the design example. 54

6 10G USXGMII Ethernet Design Example for Intel Stratix 10 Devices Figure 33. Reset Scheme for 10G USXGMII Ethernet Design Example Design Example User Logic Channel 0 MAC XGMII with Data Valid PHY Global Reset Transceiver Reset Controller 10G PLL User Logic MAC XGMII with Data Valid PHY Channel 1 Global Reset Digital Reset Analog Reset 6.4 Simulation The simulation test case performs the following steps: 1. Starts up the example design with an operating speed of 10G. 2. Configures the MAC, PHY, and FIFO buffer for both channels. 3. Waits until the design example asserts the channel_tx_ready and channel_rx_readysignals for both channels. 4. Sends the following packets: 64-byte packet 1518-byte packet 100-byte packet 5. Repeats steps 2 to 4 for 1G, 2.5G, and 5G. When simulation ends, the values of the MAC statistics counters are displayed in the transcript window. The transcript window also displays PASSED if the RX Avalon-ST interface of channel 0 received all packets successfully, all statistics error counters are zero, and the RX MAC statistics counters are equal to the TX MAC statistics counters. 55

6 10G USXGMII Ethernet Design Example for Intel Stratix 10 Devices Figure 34. Sample Simulation Output 6.5 Hardware Testing Follow the procedure at the provided link to test the design example in the selected hardware. In the Clock Control tool, which is part of the development kit, set the following frequencies: Y1 644.53125 MHz U5, OUT 8 125 MHz Related Links 6.5.1 Test Procedure Compiling and Testing the Design in Hardware on page 12 Follow these steps to test the design examples in hardware: 1. Run the following command in the system console to start the test. 56

6 10G USXGMII Ethernet Design Example for Intel Stratix 10 Devices TEST_EXT_LB <channel> <speed> <burst_size> Example: TEST_EXT_LB 0 10G 80000000 Table 18. Command Parameters Parameter Valid Values Description channel 0, 1 The channel number to test. speed 1G, 2.5G, 5G, 10G The PHY speed. burst_size An integer value The number of packets to generate for the test. 2. When the test is completed, observe the output displayed. The following diagrams show excerpts of the output, which shows that the packet monitor block receives the same number of packets generated without error, and the TX and RX statistics counters. Figure 35. Sample Output Packet Monitor 57

6 10G USXGMII Ethernet Design Example for Intel Stratix 10 Devices Figure 36. Sample Output TX and RX Statistics Counters 6.6 Interface Signals Figure 37. Interface Signals of the 10G USXGMII Ethernet Design Example Avalon-ST Transmit Data Interface Avalon-ST Transmit Flow Control Interface Avalon-ST Transmit Status Interface Avalon-ST Receive Data Interface Avalon-ST Receive Status Interface 10G USXGMII Ethernet Design Example avalon_st_tx_startofpacket[n] avalon_st_tx_endofpacket[n] avalon_st_tx_valid[n] avalon_st_tx_ready[n] avalon_st_tx_error[n] avalon_st_tx_data[n][64] avalon_st_tx_empty[n][3] avalon_st_pause_data[n][2] avalon_st_tx_status_valid[n] avalon_st_tx_status_data[n][40] avalon_st_tx_status_error[n][7] avalon_st_rx_startofpacket[n] avalon_st_rx_endofpacket[n] avalon_st_rx_valid[n] avalon_st_rx_ready[n] avalon_st_rx_error[n][6] avalon_st_rx_data[n][64] avalon_st_rx_empty[n][3] avalon_st_rx_status_valid[n] avalon_st_rx_status_data[n][40] avalon_st_rx_status_error[n][7] n: Number of channels csr_clk refclk_10g mac32b_clk mac64_clk rx_pma_clkout[ n] reset tx_digitalreset[ n] rx_digitalreset[ n] csr_mch_read[n] csr_mch_readdata[n][32] csr_mch_write[n] csr_mch_writedata[32] csr_mch_address[n][20] csr_mch_waitrequest[n] tx_serial_data[ n] rx_serial_data[ n] channel_tx_ready channel_rx_ready rx_block_lock led_an Clock and Reset Avalon-MM Interface PHY Interface Status Interface 58